CH32F1 support

ch32-data-serde/src/chip.rs

@@ -64,9 +64,17 @@ pub struct Doc {
     pub url: String,
 }
 
+#[derive(Copy, Clone, Debug, Eq, PartialEq, Hash, PartialOrd, Ord, Serialize, Deserialize)]
+#[serde(rename_all = "lowercase")]
+pub enum Arch {
+    Riscv,
+    Arm,
+}
+
 #[derive(Clone, Debug, Eq, PartialEq, Hash, PartialOrd, Ord, Serialize, Deserialize)]
 pub struct Core {
     pub name: String,
+    pub arch: Arch,
     #[serde(default)]
     pub peripherals: Vec<core::Peripheral>,
     #[serde(default)]

ch32-metapac-gen/res/Cargo.toml

@@ -29,13 +29,18 @@ flavors = [
     { regex_feature = "ch32v3.*", target = "riscv32imacf-unknown-none-elf" },
     { regex_feature = "ch32x0.*", target = "riscv32imac-unknown-none-elf" },
     { regex_feature = "ch32l1.*", target = "riscv32imac-unknown-none-elf" },
+    { regex_feature = "ch32f1.*", target = "thumbv7m-none-eabi" },
 ]
 
 [dependencies]
-riscv = "0.12.0"
-# riscv-rt = { version = "0.12.2", optional = true }
 vcell = "0.1"
 
+[target.'cfg(target_arch = "riscv32")'.dependencies]
+riscv = "0.12.0"
+
+[target.'cfg(target_arch = "arm")'.dependencies]
+cortex-m = "0.7"
+
 [features]
 default = ["pac"]
 

ch32-metapac-gen/src/chip.rs

@@ -8,7 +8,7 @@ use std::path::Path;
 use chiptool::{generate, ir, transform};
 use regex::Regex;
 
-use crate::data::{Chip, Core, MemoryOption};
+use crate::data::{Arch, Chip, Core, MemoryOption};
 use crate::dump::split_prefixes_from_names;
 use crate::memory::{
     flash_write_size, gen_memory_files, memory_select_cfg_attrs, primary_flash_regions,
@@ -138,19 +138,42 @@ fn build_chiptool_ir(
     (ir, peripheral_versions, extra)
 }
 
-fn postprocess_pac_rs(s: String) -> String {
+fn postprocess_pac_rs(s: String, arch: Arch) -> String {
     let data = s.replace("] ", "]\n");
-    // FIXME: conversion
+    // Both arches drop the cortex-m-rt re-export; bins bring their own runtime.
     let data = data.replace("pub use cortex_m_rt :: interrupt ;", "");
-    let data = data.replace("cortex_m :: interrupt ", "crate ");
-    let data = data.replace("cortex_m", "riscv"); // FIXME
 
-    // match riscv-rt interrupt name
-    let data = data.replace(
-        ".vector_table.interrupts",
-        ".vector_table.external_interrupts",
-    );
-    let data = data.replace("__INTERRUPTS", "__EXTERNAL_INTERRUPTS");
+    let data = match arch {
+        Arch::Riscv => {
+            // No RISC-V InterruptNumber standard; redirect to our local trait.
+            let data = data.replace("cortex_m :: interrupt ", "crate ");
+
+            // match riscv-rt interrupt name
+            let data = data.replace(
+                ".vector_table.interrupts",
+                ".vector_table.external_interrupts",
+            );
+            data.replace("__INTERRUPTS", "__EXTERNAL_INTERRUPTS")
+        }
+        // Cortex-M NVIC uses CMSIS IRQ numbers (WWDG = 0); shift discriminants.
+        Arch::Arm => {
+            let data = Regex::new(r#"([A-Z][A-Z0-9_]*) = (\d+) ,"#)
+                .unwrap()
+                .replace_all(&data, |caps: &regex::Captures| {
+                    let n: i32 = caps[2].parse().unwrap();
+                    format!("{} = {} ,", &caps[1], n - 16)
+                })
+                .to_string();
+            Regex::new(r#"# \[doc = "(\d+) - "#)
+                .unwrap()
+                .replace_all(&data, |caps: &regex::Captures| {
+                    let n: i32 = caps[1].parse().unwrap();
+                    format!(r#"# [doc = "{} - "#, n - 16)
+                })
+                .to_string()
+        }
+    };
+
     // trim system vector, 0 to 15
     let data = Regex::new(r#"\[(Vector \{ _reserved : 0 \} , ){16}"#)
         .unwrap()
@@ -315,7 +338,7 @@ impl Gen {
 
         // pac.rs
         let rendered = generate::render(&ir, &gen_opts()).unwrap().to_string();
-        let pac = postprocess_pac_rs(rendered);
+        let pac = postprocess_pac_rs(rendered, core.arch);
         let mut file = File::create(chip_dir.join("pac.rs")).unwrap();
         file.write_all(pac.as_bytes()).unwrap();
         file.write_all(extra.as_bytes()).unwrap();

ch32-metapac-gen/src/data.rs

@@ -430,9 +430,17 @@ pub enum MemoryRegionKind {
     Ram,
 }
 
+#[derive(Copy, Debug, Eq, PartialEq, Clone, Deserialize)]
+#[serde(rename_all = "lowercase")]
+pub enum Arch {
+    Riscv,
+    Arm,
+}
+
 #[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
 pub struct Core {
     pub name: String,
+    pub arch: Arch,
     pub peripherals: Vec<Peripheral>,
     #[serde(default)]
     //pub nvic_priority_bits: Option<u8>,

data/chips/CH32F103C6T6.yaml

@@ -0,0 +1,28 @@
+name: CH32F103C6T6
+family: ARM Cortex-M-based, general-purpose MCU
+subfamily: General-purpose
+product_type: Cortex-M3 core, basic version, main frequency <= 72M
+device_id: 0
+packages:
+  - name: CH32F103C6T6
+    package: LQFP48
+include_memory: ../memory/CH32V1.yaml
+memory_sizes: { USR_1: 32K, RAM: 10K }
+docs:
+  - type: homepage
+    title: Homepage
+    name: ""
+    url: http://www.wch.cn/products/CH32F103.html
+cores:
+  - name: cortex-m3
+    arch: arm
+    peripherals: []
+    include_peripherals:
+      - "../family/CH32F1.yaml"
+      - "../peripherals/FV2x_V3x_I2C1.yaml"
+      - "../peripherals/FV2x_V3x_SPI1.yaml"
+      - "../peripherals/V1x_V2x_ADV_TIM1.yaml"
+      - "../peripherals/V1x_GP16_TIM23.yaml"
+    include_interrupts: "../interrupts/CH32V1.yaml"
+    include_dma_channels:
+      DMA1: "../dma/CH32V103.yaml"

data/chips/CH32F103C8T6.yaml

@@ -0,0 +1,30 @@
+name: CH32F103C8T6
+family: ARM Cortex-M-based, general-purpose MCU
+subfamily: General-purpose
+product_type: Cortex-M3 core, basic version, main frequency <= 72M
+device_id: 0x20004102
+packages:
+  - name: CH32F103C8T6
+    package: LQFP48
+include_memory: ../memory/CH32V1.yaml
+memory_sizes: { USR_1: 64K, RAM: 20K }
+docs:
+  - type: homepage
+    title: Homepage
+    name: ""
+    url: http://www.wch.cn/products/CH32F103.html
+cores:
+  - name: cortex-m3
+    arch: arm
+    peripherals: []
+    include_peripherals:
+      - "../family/CH32F1.yaml"
+      - "../peripherals/FV2x_V3x_I2C1.yaml"
+      - "../peripherals/FV2x_V3x_I2C2.yaml"
+      - "../peripherals/FV2x_V3x_SPI1.yaml"
+      - "../peripherals/FV2x_V3x_SPI2.yaml"
+      - "../peripherals/V1x_V2x_ADV_TIM1.yaml"
+      - "../peripherals/FV2x_V3x_GP16_TIM234.yaml"
+    include_interrupts: "../interrupts/CH32V1.yaml"
+    include_dma_channels:
+      DMA1: "../dma/CH32V103.yaml"

data/chips/CH32F103R8T6.yaml

@@ -0,0 +1,30 @@
+name: CH32F103R8T6
+family: ARM Cortex-M-based, general-purpose MCU
+subfamily: General-purpose
+product_type: Cortex-M3 core, basic version, main frequency <= 72M
+device_id: 0x2000410F
+packages:
+  - name: CH32F103R8T6
+    package: LQFP64M
+include_memory: ../memory/CH32V1.yaml
+memory_sizes: { USR_1: 64K, RAM: 20K }
+docs:
+  - type: homepage
+    title: Homepage
+    name: ""
+    url: http://www.wch.cn/products/CH32F103.html
+cores:
+  - name: cortex-m3
+    arch: arm
+    peripherals: []
+    include_peripherals:
+      - "../family/CH32F1.yaml"
+      - "../peripherals/FV2x_V3x_I2C1.yaml"
+      - "../peripherals/FV2x_V3x_I2C2.yaml"
+      - "../peripherals/FV2x_V3x_SPI1.yaml"
+      - "../peripherals/FV2x_V3x_SPI2.yaml"
+      - "../peripherals/V1x_V2x_ADV_TIM1.yaml"
+      - "../peripherals/FV2x_V3x_GP16_TIM234.yaml"
+    include_interrupts: "../interrupts/CH32V1.yaml"
+    include_dma_channels:
+      DMA1: "../dma/CH32V103.yaml"

data/chips/CH32L103C8T6.yaml

@@ -19,6 +19,7 @@ docs:
     url: https://www.wch.cn/products/CH32L103.html
 cores:
   - name: qingke-v4c
+    arch: riscv
     peripherals: []
     include_peripherals:
       - "../family/CH32L1.yaml"

data/chips/CH32L103F7P6.yaml

@@ -19,6 +19,7 @@ docs:
     url: https://www.wch.cn/products/CH32L103.html
 cores:
   - name: qingke-v4c
+    arch: riscv
     peripherals: []
     include_peripherals:
       - "../family/CH32L1.yaml"

data/chips/CH32L103F8P6.yaml

@@ -19,6 +19,7 @@ docs:
     url: https://www.wch.cn/products/CH32L103.html
 cores:
   - name: qingke-v4c
+    arch: riscv
     peripherals: []
     include_peripherals:
       - "../family/CH32L1.yaml"

data/chips/CH32L103F8U6.yaml

@@ -19,6 +19,7 @@ docs:
     url: https://www.wch.cn/products/CH32L103.html
 cores:
   - name: qingke-v4c
+    arch: riscv
     peripherals: []
     include_peripherals:
       - "../family/CH32L1.yaml"

data/chips/CH32L103G8R6.yaml

@@ -18,6 +18,7 @@ docs:
     url: https://www.wch.cn/products/CH32L103.html
 cores:
   - name: qingke-v4c
+    arch: riscv
     peripherals: []
     include_peripherals:
       - "../family/CH32L1.yaml"

data/chips/CH32L103K8U6.yaml

@@ -18,6 +18,7 @@ docs:
     url: https://www.wch.cn/products/CH32L103.html
 cores:
   - name: qingke-v4c
+    arch: riscv
     peripherals: []
     include_peripherals:
       - "../family/CH32L1.yaml"

data/chips/CH32M007x8x6.yaml

@@ -21,6 +21,7 @@ docs:
     url: https://www.wch-ic.com/products/CH32M007.html
 cores:
   - name: qingke-v2c
+    arch: riscv
     peripherals: []
     include_peripherals:
       - "../family/CH32V00X.yaml"

data/chips/CH32V002x4x6.yaml

@@ -31,6 +31,7 @@ docs:
     url: http://www.wch.cn/products/CH32V002.html
 cores:
   - name: qingke-v2c
+    arch: riscv
     peripherals: []
     include_peripherals:
       - "../family/CH32V00X.yaml"

data/chips/CH32V003A4M6.yaml

@@ -15,6 +15,7 @@ docs:
     url: http://www.wch.cn/products/CH32V003.html
 cores:
   - name: qingke-v2a
+    arch: riscv
     peripherals: []
     include_peripherals:
       - "../family/CH32V003.yaml"

data/chips/CH32V003F4P6.yaml

@@ -15,6 +15,7 @@ docs:
     url: http://www.wch.cn/products/CH32V003.html
 cores:
   - name: qingke-v2a
+    arch: riscv
     peripherals: []
     include_peripherals:
       - "../family/CH32V003.yaml"

data/chips/CH32V003F4U6.yaml

@@ -15,6 +15,7 @@ docs:
     url: http://www.wch.cn/products/CH32V003.html
 cores:
   - name: qingke-v2a
+    arch: riscv
     peripherals: []
     include_peripherals:
       - "../family/CH32V003.yaml"

data/chips/CH32V003J4M6.yaml

@@ -15,6 +15,7 @@ docs:
     url: http://www.wch.cn/products/CH32V003.html
 cores:
   - name: qingke-v2a
+    arch: riscv
     peripherals: []
     include_peripherals:
       - "../family/CH32V003.yaml"

data/chips/CH32V003x4x6.yaml

@@ -23,6 +23,7 @@ docs:
     url: http://www.wch.cn/products/CH32V003.html
 cores:
   - name: qingke-v2a
+    arch: riscv
     peripherals: []
     include_peripherals:
       - "../family/CH32V003.yaml"

data/chips/CH32V004x6x1.yaml

@@ -19,6 +19,7 @@ docs:
     url: http://www.wch.cn/products/CH32V004.html
 cores:
   - name: qingke-v2c
+    arch: riscv
     peripherals: []
     include_peripherals:
       - "../family/CH32V00X.yaml"

data/chips/CH32V005x6x6.yaml

@@ -25,6 +25,7 @@ docs:
     url: http://www.wch.cn/products/CH32V006.html
 cores:
   - name: qingke-v2c
+    arch: riscv
     peripherals: []
     include_peripherals:
       - "../family/CH32V00X.yaml"

data/chips/CH32V006x8x6.yaml

@@ -25,6 +25,7 @@ docs:
     url: http://www.wch.cn/products/CH32V006.html
 cores:
   - name: qingke-v2c
+    arch: riscv
     peripherals: []
     include_peripherals:
       - "../family/CH32V00X.yaml"

data/chips/CH32V007x8x6.yaml

@@ -19,6 +19,7 @@ docs:
     url: http://www.wch.cn/products/CH32V007.html
 cores:
   - name: qingke-v2c
+    arch: riscv
     peripherals: []
     include_peripherals:
       - "../family/CH32V00X.yaml"

data/chips/CH32V103C6T6.yaml

@@ -15,6 +15,7 @@ docs:
     url: http://www.wch.cn/products/CH32V103.html
 cores:
   - name: qingke-v3
+    arch: riscv
     peripherals: []
     include_peripherals:
       - "../family/CH32V1.yaml"

data/chips/CH32V103C8T6.yaml

@@ -15,6 +15,7 @@ docs:
     url: http://www.wch.cn/products/CH32V103.html
 cores:
   - name: qingke-v3
+    arch: riscv
     peripherals: []
     include_peripherals:
       - "../family/CH32V1.yaml"

data/chips/CH32V103C8U6.yaml

@@ -15,6 +15,7 @@ docs:
     url: http://www.wch.cn/products/CH32V103.html
 cores:
   - name: qingke-v3
+    arch: riscv
     peripherals: []
     include_peripherals:
       - "../family/CH32V1.yaml"