CH32F1 support

[aq1018]

No description provided.

[andelf]

This might conflict with riscv releated settings

[aq1018]

@andelf

Yes, definitely. This is not merged into main. It's merged into #36. I will make sure #36 is very well tested before merging, and ideally have you review it if you have the time.

The reason I'm adding F1 support is so that I can cover the F1 support in probe-rs. But for the F1/cortex-m addition, it's actually easier than I thought, and basically just the following steps:

1. Pulling in riscv or cortex-m crate in cargo based on the compiler arch.
2. Modifying postprocess_pac_rs to be arch aware.
3. Make sure interrupts play nice.
4. Add F1 yamls and make sure we only include peripherals that are compatible.

I diff'ed generated code on a few riscv chips (v003 and v103 I think), and didn't see any differences. I will make sure they work with ch32-hal and test it out with the chips I have. (v003, v006, v103, v307) to make sure they are working.

If there are anything I missed, please let me know, and I'll make the changes.