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Previous AXI4ToLite only accepted MMIO writes when aw.valid and w.valid arrived in the same cycle. But legal AXI traffic from XS may send AW before W, or W before AW, so bridges that split the channels could drop IMSIC writes. This change keep the same-cycle path and cache the first AW or W until the other channel is accepted. The cached pair then performs one regmap write, while the pending channel deasserts ready so each side has at most one outstanding request. Also mark AXIRegIMSIC_WRAP REE/TEE slaves non-interleaving so TLToAXI4 can bridge the MMIO path.
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Previous AXI4ToLite only accepted MMIO writes when aw.valid and w.valid arrived in the same cycle. But legal AXI traffic from XS may send AW before W, or W before AW, so bridges that split the channels could drop IMSIC writes.
This change keep the same-cycle path and cache the first AW or W until the other channel is accepted. The cached pair then performs one regmap write, while the pending channel deasserts ready so each side has at most one outstanding request.
Also mark AXIRegIMSIC_WRAP REE/TEE slaves non-interleaving so TLToAXI4 can bridge the MMIO path.