Hold switchboard transactors in reset while the design is in reset

[lanserge]

autowrap generated a "rstvec" shift register for the DUT's resets, but never passed it to the transactors, so every transactor ran with its reset input tied to 1'b0. A DUT whose ready signals are high during reset (common for simple AXI-Lite register interfaces) accepts those transactions and never responds, hanging the simulation.

Pass rstvec[max_rst_dly] to each transactor macro. That bit is the last one to de-assert, so it is the logical OR of every reset driven into the design, keeping the transactors quiet until the whole design is out of reset. The reset vector is now emitted before the interfaces, since the transactors reference it.

The SB_AXI macros had no reset argument at all, leaving sb_axi_m's reset port unconnected; add one, along with QUEUE_TO_SB_SIM/SB_TO_QUEUE_SIM. All default to 1'b0, so testbenches are unaffected.

Add an "axil_reset" example as a regression test: its DUT models a register interface whose handshake logic ignores reset, so all three ready signals are high from time zero, and it counts the transactions accepted while reset was asserted. With the fix that count is 0; with the fix reverted it is 1 and the test fails.

Also fixes a missing "idw" argument in the SB_AXI_S invocation, wires up the reset in the axil_ram testbench, and adds a test that checks the generated wrapper holds each transactor in reset.

Fixes #275