Feat/ecsm update#753
Conversation
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Benchmark — ethrex 20 transfers (median of 3)Table parallelism: auto (cores / 3)
Commit: 1cb8988 · Baseline: cached · Runner: self-hosted bench |
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Codex Code ReviewFindings
Open Question
No higher-severity safety, VM semantics, or performance issues found in the PR diff. I did not build or test, per the review constraints. |
Review — Feat/ecsm updateReviewed the EC_SCALAR→ECSM inlining, the xG<p range check, the disjoint memory timestamps, the The substantive changes look correct and sound:
Minor — stale doc comments not updated by this PR:
No blocking issues. |
AI ReviewPR #753 · 16 changed files Findings
Status column reflects the verdict from the verifier: deepseek-verifier (openrouter/deepseek/deepseek-v4-pro). AI-001: Executor comment about "k bit" terminology may be misleading
Claim The comment "overlapping addresses would cause the same memory byte to serve as both an xG limb and a k bit" uses "k bit" to mean a byte of k (since the new design stores k as bytes in memory but as bits in the AIR trace). The terminology matches the new design but could be misread. Evidence The executor reads k as 4 doublewords (32 bytes total) from memory. The new ECSM design then decomposes k bytes into 256 individual bit columns for the AIR constraint. The "k bit" wording aligns with the new constraint model but the byte-level memory access and the bit-level constraint reference the same scalar in different forms. Suggested fix Consider clarifying: "would cause the same memory byte to serve as both an xG limb (in the yG carry relation) and a k limb (whose bits feed the k<N overflow check and the Bit bus receives)". This is purely documentation; the underlying check is correct. AI-002: Hardcoded id=0 in ecdas_tuple is single-curve assumption
Claim The Evidence ecdas_tuple line 596: Suggested fix For now this is fine — only secp256k1 is supported. Consider documenting this constraint near the function. No code change needed unless multi-curve support is added. AI-003: ECS MEMW op count cap mismatch with potential count
Claim
Evidence Looking at lines 680-758: the code emits exactly 15 MEMW ops (1 register + 4 xG + 1 register + 4 k + 1 register + 4 xR). The pre-allocation matches. Suggested fix No action needed; the cap matches. Just noting for future maintainers: if you add MEMW ops to this function, update the capacity. AI-004: BusId gap at ID 29 after removing ServeK
Claim The BusId enum has a numerical gap at ID 29 (ServeK was deleted, leaving the value unused). The adjacent Ecdas=28 and Bit=30 are still consecutive. No external consumer references the ID by numeric value, but the gap is undocumented in the enum. Evidence Looking at types.rs lines 304-308: Suggested fix Either add a brief comment noting ID 29 was ServeK and is now reserved/unused, or simply note that the gap is intentional. This is a minor stylistic issue, not a correctness bug. Reviewer Lanes
Verification Lanes
Native Codex and Claude reviews run separately and post their own comments. They are not included in this structured provenance report. Raw lane outputs, candidates, final issues, and model metrics are uploaded as workflow artifacts. |
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Benchmark Results for unmodified programs 🚀
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Responses to AI reviewersCouncil of AIs
Codex
Claude
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/ai-review |
Codex Code ReviewFindings: None. I reviewed the PR diff only, focusing on the ECSM/EC_SCALAR removal, ECDAS padding changes, MEMW timestamp shifts, bus interactions, and verifier/prover table shape. I did not find a concrete safety, correctness, or significant performance issue in the changed code. Static review only; I did not build or run tests per the sandbox instructions. |
Review — ECSM spec sync (EC_SCALAR inline, xG<p, disjoint timestamps, padding)I traced the cross-chip logic (Bit bus balance, memory timestamps, padding closures, and the new Verified sound
Minor notes (non-blocking)
Table/AIR bookkeeping ( |
Motivation
The spec received several updates after PR #657 merged. This PR brings the implementation in sync.
Description
EC_SCALAR inlined into ECSM
The separate EC_SCALAR chip is removed. The scalar
kis now stored as 256 individual bit columns inside ECSM instead of 32 bytes. ECSM directly holds and validates all scalar bits via IS_BIT constraints, and interacts with the BIT bus as a receiver (one per bit). The SERVE_K self-referential bus is eliminated.xG range check in the ECSM AIR
Adds a new column
xG_sub_p(U256HL) and provesxG < pvia the same carry-overflow technique already used fork < NandxR < p. Previously this was only enforced in the executor.Disjoint memory timestamps
Separates the xG and k memory reads into different timestamp slots: xG reads at T, k register read and k dword reads at T+1, xR write at T+2.
q1[32] IS_BYTE
The yG quotient's high byte (
q1[32]) was previously constrained by IS_BIT (polynomial). It is now IS_BYTE (bus lookup), fixing a completeness issue for witnesses whereq1[32] > 1.ECDAS padding simplified
Padding rows now use
q0 = q1 = q2 = 0andop = 1. TheR·Pterm in the λ and xR convolution relations is gated withμ, so it vanishes on padding rows and the relations hold at zero carries without needing to pad quotients tor = 3p.Curve identifier in ECDAS bus
A curve identifier
id(Bit, 0 = secp256k1) is prepended to the ECDAS bus tuple in all interactions, enabling future domain separation between curves.