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bc669ec
Merge branch 'master' of https://github.com/vortexgpgpu/vortex into p…
tinebp Jun 15, 2026
7191f03
gfx_v2 §6.5: on-device SW output-merger (gfx_sw.h) + §7 single-source…
tinebp Jun 17, 2026
5105022
gfx_v2: host Binning() coarse-bin migration + OM vx_om4 transition (s…
tinebp Jun 17, 2026
9e541e4
simx/rtu: parity — size context pool by NUM_CTX + charge per-ray setu…
tinebp Jun 17, 2026
944bd50
tests/vulkan/draw3d: HW-exact texel expansion + trace-accurate filter
tinebp Jun 18, 2026
25820cd
rtu: fix BVH scene_bytes header + charge per-instance transform latency
tinebp Jun 18, 2026
f0a0dfa
gfx/rtu: pid-width guard, f0-f7 window assert, config-lane doc fix
tinebp Jun 18, 2026
62edab8
rtu/simx: unbounded traversal stack (no missed hits) + restart cost
tinebp Jun 18, 2026
00a6392
rtu/simx: re-base box/tri PE cost model on the real RTL pipelines
tinebp Jun 18, 2026
b884c64
om/simx: add OmCore same-pixel R-M-W interlock (ROP ordering)
tinebp Jun 18, 2026
5dc96bb
gfx: document host Binning() as a coverage reference, not a bit-exact…
tinebp Jun 18, 2026
4704c29
RTU C2: real binned-SAH BVH builder (internal-node CW-BVH<W>)
tinebp Jun 18, 2026
5fbdabb
RTU B1: RTL RASTER reads gfx_v2 coarse-bin header (rast_bin_header_t)
tinebp Jun 18, 2026
7e7a440
RTU A2: decouple the graphics window from the RTU (standalone GfxWindow)
tinebp Jun 18, 2026
9d6f73a
RTU A1: fix §8 cross-draw depth ordering (OM holds interlock until wr…
tinebp Jun 18, 2026
b3e1ef4
RTU E1: verify + regression-lock NUM_CTX > NUM_LANES ray->context map…
tinebp Jun 18, 2026
dfab2f2
install: ship gfx_frontend_abi.h to kernel/include
tinebp Jun 19, 2026
5e99779
tests/vulkan: add multidraw depth-persistence test
tinebp Jun 20, 2026
77ae8f0
tests/vulkan: add SW output-merger tests (no-OM device builds)
tinebp Jun 20, 2026
fb8ccd6
Merge vortex_ci/ci_v2_clean into prism (CI 2.0 + core/cache/dispatch …
tinebp Jun 20, 2026
68cac3f
sim/raster: gate the producer FSM on the authoritative pending-read set
tinebp Jun 20, 2026
dd26c99
sw/gfx: cooperative prefix-scan for the BBASE binning stage
tinebp Jun 20, 2026
6eed3af
sw/gfx: enforce the libgfx_sw divergence-bbs build contract
tinebp Jun 20, 2026
526f985
tests/vulkan: add indexed-draw test (vkCmdDrawIndexed on Vortex)
tinebp Jun 20, 2026
e29fee9
sim/raster: model the TE/BE walker's quad-emission latency (Sprint B …
tinebp Jun 20, 2026
5726088
sw/gfx: fuse setup compaction — scatter direct to dense primbuf (Spri…
tinebp Jun 20, 2026
95c087a
sim/decode: exact 5-bit RTU window-slot mask (Sprint C5 / kern-P1-2)
tinebp Jun 20, 2026
b014b7e
gfx: P0 interface-law enforcement (SimX doctrine assertion + CI parit…
tinebp Jun 21, 2026
a1e332b
sim/om: fix vx_om4 window-cache corruption under multi-warp × multi-t…
tinebp Jun 21, 2026
7663e08
ci/graphics_parity: drop mis-golden'd evilskull cell; use byte-exact …
tinebp Jun 21, 2026
111783b
tests/gfx_draw3d: regenerate evilskull_ref_32 from device output
tinebp Jun 21, 2026
3f1066b
tests/graphics: return clean non-zero exit on image mismatch (was mas…
tinebp Jun 21, 2026
9f6a898
tests/gfx_raster: bin at BIN_LOGSIZE (coarse-bin migration miss)
tinebp Jun 21, 2026
302eb58
sim/raster: static screen-space tile→core ownership (P2 increment 1)
tinebp Jun 21, 2026
664b581
Merge remote-tracking branch 'vortex_ci/ci_v2_clean' into prism
tinebp Jun 22, 2026
b767701
rtl: registered read-address (RADDR_REG) RAM option + TCU/CI cleanups
tinebp Jun 24, 2026
667dadc
cache: native sync-BRAM (OUT_REG=1) for MSHR and replacement stores
tinebp Jun 24, 2026
410d87a
sim/raster: Fragment Work Distributor — push/launch dispatch (FWD-1, …
tinebp Jun 23, 2026
86f4c7a
rtl: OUT_REG=1 BRAM in cta_dispatch; elastic_buffer SIZE==2 case
tinebp Jun 24, 2026
d6c8f7a
tcu: unify metadata SRAM + factor VX_tcu_core read-side decode
tinebp Jun 24, 2026
95d54fc
cache: bounded per-bank reservation cache for LLC atomics
tinebp Jun 25, 2026
98eb3d2
gfx_v2/raster: FWD-3 v2 — RTL fragment self-pull dispatch (option B)
tinebp Jun 25, 2026
abde840
gfx_v2/raster: SimX vx_frag_fetch model (FWD-4a)
tinebp Jun 25, 2026
d5e7cb3
config: macro-namespace cleanup — auto-gen _ENABLED, de-prefix derive…
tinebp Jun 25, 2026
8acfe70
gfx_v2/raster: convert gfx_raster + gfx_pipeline_* kernels to frag_fe…
tinebp Jun 25, 2026
6f3b76b
dxa: smem_wr + addr_gen timing fixes for U55C @300MHz (WNS -3.860 -> …
tinebp Jun 25, 2026
9787e7a
gfx_v2/raster: DrawCommands::launch lmem_size (FWD-4c, runtime)
tinebp Jun 25, 2026
b3673fa
gfx_v2/raster: retire legacy vx_rast dispatch — frag_fetch only (FWD-4d)
tinebp Jun 25, 2026
b01c51f
gfx_v2/raster: FWD-5 — vx_frag_fetch payload via the gfx register window
tinebp Jun 25, 2026
fe9fe07
docs/gfx_v2: FWD-6 findings — C4 owner-routing (32->16) + residual co…
tinebp Jun 25, 2026
974be0f
tcu: add VX_CFG_TCU_USE_DSP to map TFR FEDP multipliers onto DSP48
tinebp Jun 25, 2026
92d3d28
core: fix cores>1 kernel-launch premature-idle (CTA-dispatch busy gap)
tinebp Jun 25, 2026
932bf78
docs: CTA-dispatch device-busy gap — bug/root-cause/fix report
tinebp Jun 25, 2026
d9cb208
Fix multi-core kernel-launch failure: CTA-dispatch busy gap
tinebp Jun 25, 2026
c027eca
config: derive cache writeback from is-LLC; disable dirty-byte masks
tinebp Jun 25, 2026
3846ae9
dxa: complete addr_gen timing closure (fix5-7) for U55C @300MHz
tinebp Jun 25, 2026
797341d
dxa: coarse-grain area rebalance (BRAM/DSP) for U55C @300MHz
tinebp Jun 25, 2026
8ef5f11
build: force ccache PCH external checksum for all Verilator builds
tinebp Jun 25, 2026
ca85ec1
gfx: retire dead vx_rast() pull intrinsic + stale comments (FWD-4d tail)
tinebp Jun 25, 2026
668086e
docs: consolidate gfx_v2 proposal/review set into archives/
tinebp Jun 25, 2026
0f91204
Merge remote-tracking branch 'vortex_ci/ci_v2_clean' into prism
tinebp Jun 25, 2026
9fd13ba
gfx/runtime: pool FrontEndPool scratch into one residency slab (P4)
tinebp Jun 25, 2026
557bba5
docs/gfx_v2: correct OM doctrine status + record P4 residency-slab done
tinebp Jun 25, 2026
3b53db8
gfx/rtu: rename shared graphics-window primitives vx_rt_* -> vx_gfx_*
tinebp Jun 26, 2026
7a3807b
gfx: rename vx_frag_fetch -> vx_rast_fetch (raster self-pull dispatch)
tinebp Jun 26, 2026
084c0b4
gfx/tests: migrate kernels off legacy vx_tex -> windowed vx_tex4 (P0 …
tinebp Jun 26, 2026
e5d905b
gfx: P0 batch1.P3 — auto-arm raster + delete legacy vx_tex/vx_rast_begin
tinebp Jun 26, 2026
56ef865
docs: add gfx_v2 bible (cross-layer reference) + P0 7-phase plan
tinebp Jun 26, 2026
a2a1f34
gfx_v2 P0 b2.P4: OP_DRAW device-orchestrated draw (CP + runtime)
tinebp Jun 26, 2026
faf8d74
docs: record Batch 2 (OP_DRAW) status + RTL CP synth-deferral
tinebp Jun 26, 2026
7ffc9ad
docs: P0 Phase 7 — add the four-part cross-layer code-complete review
tinebp Jun 26, 2026
88bf21c
docs: mark gfx_v2 P0 complete (bible + status banners)
tinebp Jun 26, 2026
d56a59d
gfx_v2: cap-gate OP_DRAW with a ring-batch fallback (deferred-item: R…
tinebp Jun 26, 2026
b1646a8
docs: RTL CP OP_DRAW resolved via cap-gated fallback (P0 plan note)
tinebp Jun 26, 2026
bb19966
docs: CTS-readiness note — re-base gfx tests to tolerances; SW fallba…
tinebp Jun 26, 2026
88963dc
gfx_v2 SW fallback: extract tex-sampling math to freestanding tex_sam…
tinebp Jun 26, 2026
a777e36
gfx_v2 §4.2: on-device SW texture sampler + bit-exact parity test
tinebp Jun 26, 2026
fe63a43
gfx_v2 §4.1: shared rasterizer coverage core + ground-truth test
tinebp Jun 26, 2026
5883302
gfx_v2 §6: MSAA software path (4x) — coverage, per-sample ROP, resolve
tinebp Jun 26, 2026
726373a
gfx_v2 §5: on-device software-sampler routing (gfx_tex4 -S) — rtlsim …
tinebp Jun 26, 2026
010edf1
gfx_v2 §5: on-device software output-merger routing (gfx_om -S)
tinebp Jun 26, 2026
26ca801
gfx_v2 §5: on-device software fine-rasterizer routing (gfx_raster -z)
tinebp Jun 26, 2026
a21bdb4
docs: gfx_v2 §5 mesa per-unit HW-vs-SW selection plan
tinebp Jun 26, 2026
f1a60fe
gfx_v2 §5 step 1: software-fallback C ABI (gfx_sw_abi)
tinebp Jun 26, 2026
d8c49ca
gfx_v2 §5: move gfx_sw_abi.h to sw/common (driver-includable)
tinebp Jun 26, 2026
c0432cd
gfx_v2 §5: add gfx_rast_walk_tile_sw C-ABI (SW raster foundation)
tinebp Jun 27, 2026
fcac1a0
docs: gfx_v2 §5 — TEX+OM driver forks done; RASTER wrapper design
tinebp Jun 27, 2026
f6851c9
gfx_v2 §5: iterative SW tile walk + warp-per-tile RASTER fork
tinebp Jun 27, 2026
5e93672
hw: per-bank PLATFORM_MEMORY_OFFSET — fix U250 vx_busy hang
hwirys Apr 30, 2026
5630675
hw: generalize the per-bank offset path — drop the 4-bank assumption
hwirys May 12, 2026
2521efc
cache: elastic bank pipeline with configurable latency + AMO timing fix
tinebp Jun 16, 2026
2f1a848
issue: shorten scoreboard issue-stage critical path
tinebp Jun 18, 2026
736eaa8
added mx datapath
NikhilRout Jun 16, 2026
0cbaad9
tfr optimizations
NikhilRout Jun 16, 2026
05bbb07
terminology fixes
NikhilRout Jun 19, 2026
3c5241c
ci: CI 2.0 — catalog-driven, driver-sliceable test architecture (pytest)
tinebp Jun 19, 2026
0aa6e8c
scheduler: fold CTA storage into VX_cta_dispatch
tinebp Jun 20, 2026
7b5269c
added sgemm_tcu_sp_mx + SF calc refactoring
NikhilRout Jun 20, 2026
f8bdae6
kmu/cta_dispatch: fixed-stride LMEM allocator + docs
tinebp Jun 21, 2026
ad83898
added perf/tcu csvs
NikhilRout Jun 20, 2026
c336727
graphics: relax image-compare tolerance to +-2
tinebp Jun 22, 2026
3f1e178
Revert "graphics: relax image-compare tolerance to +-2"
tinebp Jun 22, 2026
e9a5fa3
rtl: registered read-address (RADDR_REG) RAM option + TCU/CI cleanups
tinebp Jun 24, 2026
5c62fec
rtl: OUT_REG=1 BRAM in cta_dispatch; elastic_buffer SIZE==2 case
tinebp Jun 24, 2026
224978c
config: macro-namespace cleanup — auto-gen _ENABLED, de-prefix derive…
tinebp Jun 25, 2026
79187ab
dxa: smem_wr + addr_gen timing fixes for U55C @300MHz (WNS -3.860 -> …
tinebp Jun 25, 2026
1179fcd
tcu: add VX_CFG_TCU_USE_DSP to map TFR FEDP multipliers onto DSP48
tinebp Jun 25, 2026
bbc96ec
dxa: coarse-grain area rebalance (BRAM/DSP) for U55C @300MHz
tinebp Jun 25, 2026
1bc40cd
dxa: smem_wr barrel-shifter rebalance, -27% smem_wr LUT for U55C @300MHz
tinebp Jun 25, 2026
d2d37f1
tcu: pack two fp8 mantissa products per DSP48 in mul_f8
tinebp Jun 26, 2026
ec2990f
tcu: pack two int4 products per DSP48 in mul_i4 (magnitude decomposit…
tinebp Jun 26, 2026
54cbbdf
tcu: pack fp4 mantissa/term products onto DSP48 in mul_f4
tinebp Jun 26, 2026
f32895d
config: default TCU to FP16-only; other formats opt-in
tinebp Jun 26, 2026
ca4f2d5
ci: TCU format coverage under FP16-only default
tinebp Jun 26, 2026
5f0109e
tcu: unify DSP packing into one generic VX_tcu_tfr_wmul
tinebp Jun 26, 2026
fc4ca01
tcu: default VX_CFG_TCU_USE_DSP on for FPGA synthesis via config
tinebp Jun 26, 2026
3742ac8
fpu: unit-internal vendor FP IP selection + split units + IEEE fixes
tinebp Jun 26, 2026
edf9223
ci: change-aware driver escalation so RTL changes run rtlsim on push
tinebp Jun 26, 2026
4e09b63
fix: L1 dcache must be write-through (multi-core coherence regression)
tinebp Jun 26, 2026
5733193
fix: MX regression apps must enable FP8 (default ITYPE=mxfp8)
tinebp Jun 26, 2026
782cbf5
Remove redundant cache write-back coherence asserts
tinebp Jun 26, 2026
c85d5e5
tcu: gate group_prod on MX float formats in DPI FEDP
tinebp Jun 26, 2026
d125b1a
tcu/dxa: WGMMA bbuf-native flat/block-major B producer
tinebp Jun 27, 2026
df15321
cache: SimX i/d-cache pipeline latency matches RTL (capacity-scaled)
tinebp Jun 27, 2026
dcc09b9
tcu: remove dead wmul2/wmul2s after generic VX_tcu_tfr_wmul unification
tinebp Jun 27, 2026
16885b0
cp: AXI register slice at host/dev AXI boundary for timing closure
tinebp Jun 27, 2026
503e4e8
docs: extend Verilog guideline §12 to parameterized interface instances
tinebp Jun 27, 2026
0c360ad
cache: split dirty bit into a parallel LUTRAM array (tag-store timing)
tinebp Jun 27, 2026
a458b98
docs: require re-configure before building/running (stale VX_config.h…
tinebp Jun 29, 2026
a040c0b
sim: remove dead TCU_META_ENABLE Makefile propagation
tinebp Jun 29, 2026
6c2d948
graphics: SW stack refactor + device-launched fragment dispatch (Stag…
tinebp Jun 30, 2026
6cc3b6a
gfx: raster->SIMT redesign (P1+P2) + multi-engine drain fix + parent …
tinebp Jul 1, 2026
67be5f0
simx/cache: MSHR arrival-order replay (port from vortex_ci 936ea705)
tinebp Jul 1, 2026
3d39378
gfx: P3.1 fixed-point screen-space depth plane (true-GPU FF depth)
tinebp Jul 1, 2026
6d1461d
gfx: P3.2-3.5 SimX raster early-Z (test-only occlusion cull)
tinebp Jul 1, 2026
9472064
docs: untrack gfx_v2_rast_fetch_removal_true_gpu.md (proposals stay u…
tinebp Jul 1, 2026
b2bcff8
ci: expand graphics/vulkan test coverage (early-Z, RT, FF/SW matrix)
tinebp Jul 2, 2026
3594fb4
merge: pull latest shared fixes from vortex_ci (ci_v2_clean)
tinebp Jul 2, 2026
0a976d8
docs: untrack proposals (keep on disk), except mmu_optimization_proposal
tinebp Jul 2, 2026
e84f83c
core: revert VX_cta_dispatch to match vortex_ci (ci_v2_clean)
tinebp Jul 2, 2026
a8090a6
merge: complete vortex_ci shared merges (f1c661c5 + override CONFIGS)
tinebp Jul 2, 2026
d205650
rtu/fpu: FTZ reciprocals, divide-only recip, and §12 instantiation style
tinebp Jul 2, 2026
df66c2a
gfx: bundle the graphics-window ports into SystemVerilog interfaces
tinebp Jul 2, 2026
3eb9f07
gfx: rasterizer Early-Z (P3) with strict-behind occlusion cull
tinebp Jul 2, 2026
435d202
tcu: shorten TFR norm/round abs via fused (x^sign)+sign
tinebp Jul 2, 2026
1e69e2f
rvc: fix decompressor straddler deadlock (false redirect on continuat…
tinebp Jul 2, 2026
e840b25
dxa: register LMEM write-address at the DXA boundary; tidy DCR distri…
tinebp Jul 2, 2026
5a5699f
docs: refresh graphics design docs for the gfx_v2 architecture
tinebp Jul 2, 2026
4ca2325
ci: clear graphics/vulkan known_issue markers
tinebp Jul 2, 2026
b14984f
docs: refresh graphics/CP/vortexpipe design docs to current architect…
tinebp Jul 3, 2026
1548755
docs: untrack docs/archives (kept on disk, gitignored)
tinebp Jul 3, 2026
9078b93
simx: fix same-line memory ordering in the write-back dcache model
tinebp Jul 4, 2026
226861c
gfx: saturate the Q7.24 depth word to the 24-bit zbuf range
tinebp Jul 4, 2026
88d6b76
raster: derive the fragment warp's startup PC from the KMU startup DCR
tinebp Jul 4, 2026
b545b12
gfx: latch the vx_om4 payload at capture; coverage drop inside the SW OM
tinebp Jul 4, 2026
d2d9562
faster_cache: sectored caches + word-size dcache banking for MLP
tinebp Jun 29, 2026
5faf447
kernel: hoistable CSR reads + asm volatile/clobber correctness
tinebp Jun 29, 2026
8238f54
chore: misc cleanup (sim Makefile, build docs, changelog)
tinebp Jun 29, 2026
084a00d
config: default TCU type to TFR on all platforms
tinebp Jun 30, 2026
411c913
config: coherence-safe write-back policy + line-driven sector sizing
tinebp Jul 1, 2026
e9ae85c
simx/cache: port AMO to sectored model + MSHR arrival-order replay
tinebp Jul 1, 2026
6466e88
fpu: rename SNORM_ENABLE parameter to SUBNORM_ENABLE
tinebp Jul 2, 2026
fa5dad0
rvc: fix decompressor straddle/divergence/multi-CTA correctness (NT4/…
tinebp Jul 3, 2026
38dcf9a
docs: add the SimX Cardinal Rule — modules communicate only through c…
tinebp Jul 4, 2026
7d9864f
tests: model the tensor core's fused accumulation in the sgemm_tcu go…
tinebp Jul 4, 2026
4e02bea
ci: add dxa_kmajor_check to the dxa category
tinebp Jul 4, 2026
d603a12
tcu: compute FEDP norm LZC in parallel with the abs carry chain
tinebp Jul 4, 2026
b3d0269
dxa: narrow descriptor DCR offset decode to the window width
tinebp Jul 4, 2026
10a794f
docs: interface buffering ownership rule in Verilog guidelines
tinebp Jul 4, 2026
9cbb092
simx: enforce MSHR chain ordering at bank admission
tinebp Jul 4, 2026
31acbe4
simx: route TCU metadata through an LSU client port; delete memory ba…
tinebp Jul 4, 2026
e97a287
tcu: repair metadata-SRAM unification lost in a duplicate mx-datapath…
tinebp Jul 4, 2026
51462b5
simx: add the sector field to the rtcache config (sectored-cache merge)
tinebp Jul 4, 2026
6450fdb
kmu: do not start the CTA walk on an empty grid
tinebp Jul 4, 2026
c4d2330
tests/graphics: regenerate box/evilskull references
tinebp Jul 4, 2026
f5e96a7
gfx: early-Z requires blending disabled
tinebp Jul 4, 2026
681da5e
om: fix write-path deadlock, phantom writes, and device-drain holes
tinebp Jul 4, 2026
a8c41d2
dxa: incremental tiled addressing in the SMEM writer
tinebp Jul 5, 2026
d4c402f
gfx_v2: Phase-0 graphics + ray_query implementation (RTL + SimX + SW …
tinebp Jul 7, 2026
11fc0d0
core: consolidate LSU address generation into VX_lsu_agu
tinebp Jul 5, 2026
826a11d
hw: reorganize AXI/mem adapter & interconnect library; CP multi-outst…
tinebp Jul 6, 2026
0cf4c5c
hw/cache: derive bank mem-req/core-rsp queue depths; native-BRAM mem_…
tinebp Jul 7, 2026
dc6a0b0
tests/opencl: port 15 Rodinia benchmarks + wire into CI
tinebp Jul 7, 2026
7179aba
config: audit config/package definitions; derive helpers in owning pa…
tinebp Jul 7, 2026
0c7331b
tests/raytracing: rename rtu_* smoke tests to rt_* prefix
tinebp Jul 7, 2026
6e4eb20
ci: add simx<->rtlsim cycle-parity checks (pipeline + per-extension)
tinebp Jul 7, 2026
3e9a731
cache: fix AMO writeback queue dropping same-line, different-word ato…
tinebp Jul 7, 2026
72d9856
ci: run hybridsort on rtlsim now that same-line scatter atomics work
tinebp Jul 7, 2026
f759750
sim: gate DRAM command trace behind DRAM_TRACE env var
tinebp Jul 7, 2026
08763e8
tests: expand graphics/vulkan/raytracing coverage; unmask graphics pa…
tinebp Jul 7, 2026
f6b55e9
tests, synth: dump device perf counters; wire gfx/RTU synth sources
tinebp Jul 7, 2026
c99839d
simx: align TCU MMA uop latency with the tensor-PE pipeline depth
tinebp Jul 8, 2026
5b8b764
hw/syn: factor extension-source wiring into shared extensions.mk
tinebp Jul 8, 2026
0dbf847
simx: align memory-path and TEX timing with hardware hop structure
tinebp Jul 8, 2026
3c6b20d
tests/opencl: add OpenCL image tests + CI
tinebp Jul 8, 2026
e5b6c22
sgem optimization using loop unrolling
tinebp Jul 8, 2026
72e95af
simx: align raster wave packing and walk order with hardware
tinebp Jul 8, 2026
d1d1d0a
opencl: Tier-A FF image tests + CI, TEX clamp fix, changelog
tinebp Jul 8, 2026
d2bd36b
ci(apptainer): provision pytest/pyyaml in the container image
tinebp Jul 8, 2026
4191d98
treewide: remove the unimplemented RISC-V Vector (V) extension
tinebp Jul 8, 2026
4d5f5ef
ci: model_parity + perf_gate checks, cadence tiers, benchmark expansion
tinebp Jul 9, 2026
98b1762
simx: fix wgather source-lane aliasing and LSU direct-commit backpres…
tinebp Jul 9, 2026
469b832
core: mask RV64 is_w for compressed branches
tinebp Jul 9, 2026
c087403
core,simx: preserve running mask on privilege-switch MRET
tinebp Jul 9, 2026
ca97761
dxa: static-assert descriptor-meta fields fit the 32-bit ABI word
tinebp Jul 9, 2026
9e39a43
tex: index the filter-enable bit for scalar conditions
tinebp Jul 9, 2026
7c6cca1
unittest: track committed RTL interface changes
tinebp Jul 9, 2026
e279d87
unittest(tcu): drop dead TFR top override and stale LANE_MASK param
tinebp Jul 9, 2026
a617529
ci: pin model_parity and perf_gate gates to 32-bit only
tinebp Jul 9, 2026
4d8839e
rtu: elaborate geometry-PE FP units as hardened vendor IP on FPGA
tinebp Jul 9, 2026
5a5ca86
rtu: precompute nearest-first child order and register the decoded node
tinebp Jul 9, 2026
7c1ea5f
raster: add gfx window package to the standalone DUT build
tinebp Jul 9, 2026
4e55b15
cache: honor CORE_OUT_BUF/MEM_OUT_BUF on the output crossbars
tinebp Jul 9, 2026
7dbf73b
docs(verilog): require modules to register their outgoing external in…
tinebp Jul 9, 2026
10b5555
tests/gfx_draw3d: build kernel with -ffp-contract=off
tinebp Jul 9, 2026
dd9d0eb
ci: expand perf_gate coverage to 27 gated benchmarks
tinebp Jul 9, 2026
a09975d
simx: model LSU coalescer's two-cycle issue cadence
tinebp Jul 9, 2026
290b783
hw/graphics: rename g_*_unit genblocks to g_*_core
tinebp Jul 9, 2026
9d75afd
rtu: register outgoing bus and cache interfaces at their source
tinebp Jul 9, 2026
80b66d8
syn: per-SLR pblock floorplan for multi-SLR devices
tinebp Jul 9, 2026
cf66c1a
hw/sfu: reorder VX_gfx_window params to match module port order
tinebp Jul 9, 2026
b8fb9f1
ci: add model_parity twins for perf_gate benchmarks
tinebp Jul 9, 2026
8f8e122
raster: silence unused upper frag_param bits in non-debug builds
tinebp Jul 10, 2026
312f943
ci/tensor_wg: switch dense WGMMA perf_gate from int8 to fp16
tinebp Jul 10, 2026
f33a035
cache: advance the repl look-ahead read every non-stalled cycle
tinebp Jul 10, 2026
ba89f5f
runtime,cp: gate CMD_LAUNCH_QMD on a CP capability bit
tinebp Jul 10, 2026
60a49ff
rtu: lint-clean the RTU RTL and add it to the AFU sim builds
tinebp Jul 10, 2026
a6de415
kmu,raster: delegate grid-less draw launches from the KMU to the rast…
tinebp Jul 10, 2026
91c1351
agents,raster: document the SimX/RTL timing-lockstep rule
tinebp Jul 10, 2026
77f4b98
cache: fill-forwarding of the MSHR pending chain
tinebp Jul 10, 2026
0b1db06
tests/hip: point pocl at the shipped llvm-spirv translator
tinebp Jul 10, 2026
bf7f3ba
cache: narrow the bank pipeline payload to one word
tinebp Jul 10, 2026
fd40ddd
cache: order plain accesses against the atomic writeback window
tinebp Jul 10, 2026
ed61857
lsu: decouple the outstanding-request pool from the staging queue
tinebp Jul 10, 2026
a9f3688
ci: refresh perf baselines for the LSU outstanding pool
tinebp Jul 10, 2026
46a3210
docs: refresh documentation tree
tinebp Jul 10, 2026
b4b7306
gfx_window: memory-backed window + beat-serial RTU bus
tinebp Jul 10, 2026
5b2800b
syn: make SLR floorplan capacity-aware and fail-safe
tinebp Jul 10, 2026
e4acb0f
simx: order same-address requests against pending atomics
tinebp Jul 11, 2026
51aaa2d
cache: hold requests behind an atomic pending in the MSHR
tinebp Jul 11, 2026
bad6e97
tex: fix read-latency prologue and writeback double-push
tinebp Jul 11, 2026
2be0e3a
cache: register cache_bypass external outputs (fix dropped OUT_BUF re…
tinebp Jul 11, 2026
1dccf7b
ci: mark model_parity rtlsim<->simx divergences as known_issue
tinebp Jul 11, 2026
239a9ce
core: order the icache flush behind the dcache flush
tinebp Jul 11, 2026
432da29
simx: claim the RTU ray-pool slot at issue
tinebp Jul 11, 2026
7565e17
ci: mark the LSU-pool model_parity cycle gaps as known_issue
tinebp Jul 11, 2026
21e374a
ci: refresh the draw3d perf baseline for the memory-backed gfx window
tinebp Jul 11, 2026
8770824
readme: drop GoogleTest from the toolchain dependency list
tinebp Jul 11, 2026
4800687
rtu: size the scene address and the fncp results to their ports
tinebp Jul 12, 2026
ce7044a
Merge branch 'master' into prism
tinebp Jul 12, 2026
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7 changes: 5 additions & 2 deletions .github/workflows/apptainer-ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -100,8 +100,11 @@ jobs:
mkdir -p build32 && cd build32
../configure --tooldir=$APPTAINER_TOOLDIR --xlen=32
make software -s
make tests -s
pip install --quiet pytest pyyaml
# Build only the regression category the smoke actually runs.
# `make tests` also builds the opencl category, which links
# -lOpenCL from the (ICD-less prebuilt pocl) toolchain and fails
# in the container -- and the smoke never runs those tests.
make -C tests regression -s
chmod -R +x .
VX_XLEN=32 python3 -m pytest ci -m "regression and simx" --strict-markers -v
EOF
Expand Down
33 changes: 29 additions & 4 deletions .github/workflows/ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@ on:
description: "comma list: simx,rtlsim,xrtsim,opaesim (blank = all)"
default: ""
tier:
description: "comma list: smoke,fast,slow,nightly (blank = all)"
description: "comma list: smoke,full,nightly (blank = all)"
default: ""

env:
Expand Down Expand Up @@ -68,15 +68,17 @@ jobs:
IN_DRIVERS: ${{ github.event.inputs.drivers }}
IN_TIER: ${{ github.event.inputs.tier }}
TOOLCHAIN_CACHE_HIT: ${{ steps.tc.outputs.cache-hit }}
PUSH_BEFORE: ${{ github.event.before }}
PR_BASE: ${{ github.event.pull_request.base.sha }}
run: |
set -euo pipefail
# Driver/tier policy by event (workflow_dispatch overrides).
case "$EVENT" in
schedule) DRIVERS=""; TIER="" ;; # everything
pull_request) DRIVERS="simx,rtlsim"; TIER="smoke,fast,slow" ;;
push) DRIVERS="simx"; TIER="smoke,fast" ;;
pull_request) DRIVERS="simx,rtlsim"; TIER="smoke,full" ;;
push) DRIVERS="simx"; TIER="smoke" ;;
workflow_dispatch) DRIVERS="$IN_DRIVERS"; TIER="$IN_TIER" ;;
*) DRIVERS="simx"; TIER="smoke,fast" ;;
*) DRIVERS="simx"; TIER="smoke" ;;
esac
# Toolchain (re)built -> 100% coverage. If the toolchain cache missed
# (deleted / out-of-date / evicted / key changed / first run) the build
Expand All @@ -90,6 +92,21 @@ jobs:
DRIVERS=""; TIER=""
fi
fi
# Change-aware driver escalation: simx is a separate C++ model and cannot
# exercise the RTL, so a change under hw/rtl, hw/dpi, sim/rtlsim|xrtsim|
# opaesim, or vendored RTL must force the matching sim driver in even on a
# push (which is otherwise simx-only). An indeterminate diff (zero/missing
# base, e.g. a new branch or force-push) escalates to full coverage.
if { [ "$EVENT" = "push" ] || [ "$EVENT" = "pull_request" ]; } && [ -n "$DRIVERS" ]; then
BASE="$PUSH_BEFORE"; [ "$EVENT" = "pull_request" ] && BASE="$PR_BASE"
ESC=$(python3 ci/testcase.py drivers --changed-from="$BASE" || echo ALL)
if [ "$ESC" = "ALL" ]; then
echo "indeterminate diff -> full driver coverage"; DRIVERS=""
elif [ -n "$ESC" ]; then
DRIVERS=$(printf '%s\n' "$DRIVERS" "$ESC" | tr ',' '\n' | grep . | sort -u | paste -sd,)
echo "RTL-affecting change -> drivers=$DRIVERS"
fi
fi
F=""
[ -n "$DRIVERS" ] && F="$F --drivers=$DRIVERS"
[ -n "$TIER" ] && F="$F --tier=$TIER"
Expand Down Expand Up @@ -185,6 +202,14 @@ jobs:
chmod -R +x .
EXPR="${{ matrix.category }}"
[ "${{ matrix.driver }}" != "host" ] && EXPR="$EXPR and ${{ matrix.driver }}"
# model_parity / perf_gate are cross-cutting check markers with
# their own dedicated cells; exclude them from every other category's
# cell so a distributed check spec runs once (in its check cell), not
# twice (also in its owning category's cell).
case "${{ matrix.category }}" in
model_parity|perf_gate) ;;
*) EXPR="$EXPR and not model_parity and not perf_gate" ;;
esac
VX_XLEN=${{ matrix.xlen }} python3 -m pytest ci -m "$EXPR" --strict-markers \
-v \
--junitxml="$GITHUB_WORKSPACE/junit-${{ matrix.category }}-${{ matrix.driver }}-${{ matrix.xlen }}.xml"
Expand Down
4 changes: 3 additions & 1 deletion .gitignore
Original file line number Diff line number Diff line change
@@ -1,2 +1,4 @@
/build*
/.*
/.*
# Archived/superseded docs — kept on disk, never tracked
docs/archives/
7 changes: 6 additions & 1 deletion AGENTS.md
Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,8 @@ See [docs/install_vortex.md](docs/install_vortex.md) for the full recipe. The no
```
- **Separate build dirs per major variant** (`build32/`, `build64/`, `build_fpga64/`, ...) to avoid config/tool contamination. Never reuse one build dir for incompatible configurations.
- **`configure` generates a runnable tree** by copying and instantiating `ci/`, `runtime/`, `sim/`, and `tests/` into `build/`. For execution and test automation, *always* prefer the generated scripts/Makefiles under `build/` over the source-tree `.in` files.
- **Re-`../configure` from `build/`** whenever you `git pull`, edit source Makefiles, or add/remove a build-participating directory. Symptom of forgetting this: stale binaries, missing targets, or "I edited this Makefile and nothing happened."
- **Re-`../configure` from `build/`** whenever you `git pull`, edit source Makefiles, edit `VX_config.toml` / any `*.toml`, or add/remove a build-participating directory. Symptom of forgetting this: stale binaries, missing targets, or "I edited this Makefile and nothing happened."
- **Always ensure the build is current before running any test or app** — re-run `../configure` from `build/` first. `configure` regenerates `<build>/sw/VX_config.h` and `<build>/hw/*.vh` from `VX_config.toml`, but only when the toml is newer (it guards on mtime). The simx/RTL **cores `#include` this generated header**, so a stale header makes a core compile against old config values and silently diverge from the toml — and from the runtime/RTL, which re-expand the config every build. This is a real footgun: a stale `VX_config.h` once made SimX run a write-back D-cache while the toml/RTL were write-through, producing SimX-only wrong results. **Never** work around such a divergence by injecting `-DVX_CFG_*` overrides into a Makefile — that masks the stale artifact and fights the config system. The toml is the single source of truth; fix it by re-`configure`-ing.
- **`ccache` can serve stale objects on `fmt`-version mismatches** (typical symptom: `fmt::v8` undefined-reference link errors in sim builds). Before deep-diving, retry with `CCACHE_DISABLE=1`.

---
Expand Down Expand Up @@ -83,6 +84,8 @@ See [docs/testing.md](docs/testing.md) and [docs/debugging.md](docs/debugging.md
- **`--rebuild=1` forces a driver rebuild** even if the hardware configuration is unchanged. Use it when iterating on the driver itself; `--rebuild=0` suppresses rebuild regardless.
- **RTL coverage path is `xrt`, not `rtlsim`.** When discussing or planning RTL verification, `xrt` is the canonical path — `rtlsim` bypasses the AFU surface. `rtlsim` remains useful for fast iteration on processor RTL; `xrt` is what proves the full integration.
- **`ci/regression.sh` is the canonical source of tested configurations.** Use it to discover supported parameter combinations before inventing ad hoc ones.
- **Perf-regression baselines (`ci/perf/baselines/*.json`) are golden data — never hand-edit them, and never "fix" a red perf gate by bumping the number.** They are regenerated only by `pytest ci -m perf_gate --update-baselines` (a human-run, reviewed step), and CI must never pass that flag. A `perf_gate` failure means real cycles moved: root-cause it, or — if the change is intended — regenerate the baseline so the diff shows the perf delta for review. Same rule as image goldens and `known_issue:`.
- **SimX is the RTL's timing model — keep them in lockstep.** Any change that moves RTL cycles (pipeline structure, arbitration, queue depths, cache/memory behavior) must land together with the matching SimX timing-model update, and vice-versa. The `model_parity` CI gate enforces this: a `check: model_parity` case (`ci/testcases/model_parity.yaml` + per-extension parity categories) runs the same app/args/configs on simx and rtlsim and asserts exact retired-instruction match plus cycle agreement within the case tolerance (default 5%). Never widen a tolerance to absorb a divergence — model the behavior. When adding a hardware feature, add or extend a parity case that exercises it.
- **When RTL debugging stalls, switch to the SimX-as-oracle pattern.** For numerical bugs, deep pipeline races, or any failure mode where rtlsim is "close but wrong": (1) build/extend the SimX C++ model so it mirrors the *new* RTL architecture and gets to PASS; (2) add matching trace dumps to both SimX and RTL (cycle, FU events, SRAM addresses+data, hazards) — same CSV format on both sides; (3) diff trace files — the first divergence is the bug. Don't keep guessing from output values; localize via trace diff. See [docs/debugging.md](docs/debugging.md#simx-as-oracle-for-rtl-debug).

### Smoke tests
Expand Down Expand Up @@ -111,6 +114,8 @@ make -C tests/opencl run-rtlsim

- **Align with mainstream CUDA, HIP, OpenCL, and Vulkan API and driver stacks.** For any design question — driver surface, command-processor model, memory model, scheduling — pick the solution those stacks would use. This keeps Vortex's externals familiar to mainstream software and avoids one-off abstractions.

- **SimX Cardinal Rule — modules communicate *only* through channels.** A `SimObject` may observe or mutate another module's state *only* via its bound `SimChannel` ports (`MemReq`/`MemRsp`, `result_if`, …). **Never reach across the ownership hierarchy** to touch another object directly (`core_->processor()->memsim()`, `parent()->child()->field`, a leaf unit grabbing the global `Memory`). See [docs/simobject.md](docs/simobject.md#the-cardinal-rule).

---

## 6. Coding Conventions
Expand Down
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