32-bit Superscalar RISC-V CPU

KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi

CPU Benchmarks Set

CoreMark 1.0 ported to WebAssembly

LEVEL: Open-source RV32IMC RISC-V processor core with pipelined microarchitecture, cache support, SoC peripherals and verification framework.

This repository utilizes CoreMark as the benchmarking core for evaluating microcontrollers.

STM32CubeMX Pack for Easy Integration of CoreMark

A 6-Stage RISC-V RV32IM Core on FPGA (263.7 CoreMark, 91.0 DMIPS@100MHz)

Minimalist Kernel Providing Test Environment

Forth language port of CoreMark benchmark (https://www.eembc.org/coremark)

This work presents the design and implementation of high performance and low power 32-bit RISC-V processor 4-stage pipelined for non-load and 5-stage for load operations, also extending its capabilities as system on chip (SoC) design. RV32I with M extension designed for FPGA and ASIC

Examples for cyancore framework

ArduinoCoreMark is a CPU performance benchmark for Arduino platform based on EEMBC CoreMark.

Architecture and Performance Evaluation of EEMBC::CoreMark benchmark on BOOM CPUs (Small & Large).

A stable version of nexus-am (created by jyy).

Raspberry Pi Pico Coremark

Port Coremark to the LP Core of ESP32-C6

CoreMark's primary goals are simplicity and providing a method for testing only a processor's core features.

Coremark for iMXRT1170 Dual Core

Demo Project for ZES RISC-V IC