Serial port library written in C++.

Serial port communication in Java - FTDI D2XX, HID API, X/Y modem

Terminal emulator with Serial and TCP socket capabilities

Python Interface to Array 3710A DC Electronic Load

Serial terminal app for connecting to serial devices with profiles.

Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.

codes of my IUT FPGA LAB

第三届电磁大数据挑战赛码元宽度回归预测参考例程，实现了码元宽度盲估计

TahakomAVRLib is a C++ library to program Atmel AVR microcontrollers

This is a project of a fully software UART protocol implementation for low speed bauds where you can enter a float type value of baudrate (1.1 baud tested). It uses any digital OI pins as Rx and Tx. No interrupts used.

Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.

UART 8-Bit Verilog Simple Realization

Advanced UART core on Spartan-3E FPGA using Verilog, featuring FSM-based TX/RX logic, FIFO buffering, and configurable baud rate generation, built and tested on Ubuntu Linux using Xilinx ISE.

A simple chat application built for 8086 assembly that uses a serial communication (UART) interface to send and receive text. The program splits the screen into two parts for bi-directional messaging, allowing you to chat with another terminal via serial port.

Fully parameterizable uart (data width, clock frequency, parity bit [ON/OFF];[ODD/EVEN], stop bit length, baud rate, seniority [DESC/ASC])

A simple BaudRate Checker to avoid manual Testing of BuadRates

Interactive pyserial-based RS-232 probe for COM port baud/framing/flow-control discovery, validation, and reporting on legacy hardware.

Baud Rate Generator in VHDL for FPGA-based UART communication. The generator produces a periodic tick signal at 153,600 Hz (16x oversampling for a 9,600 baud rate) from a 50 MHz input clock. This is targeted for Spartan 3E FPGA.