An ultra-low latency, hardware-accelerated market data processing and order book engine implemented on the Altera DE1-SoC (Cyclone V). By bypassing the OS, kernel network stack, and CPU entirely, this system parses NASDAQ ITCH 5.0 feeds, filters tickers on-the-fly, and maintains the order book entirely in SystemVerilog FPGA fabric at 100 MHz.
This project splits processing between the ARM Hard Processor System (HPS) running Linux and the FPGA fabric, connected via high-bandwidth AXI bridges.
+-------------------------------------------------------------------------+
| HPS (ARM Cortex-A9 Linux) |
| |
| [ NASDAQ ITCH Binary ] [ C Reference Model ] |
| (itch_load) (itch_arm) |
+-----------|--------------------------------------|----------------------+
| |
| AXI Bridge (Ping-Pong BRAM) | Benchmarking
v | & Validation
+-----------|--------------------------------------|----------------------+
| FPGA Fabric (100 MHz) | |
| | |
| [ buffered_ingest.sv ] | |
| | | |
| v | |
| [ itch_parser.sv ] | |
| | | |
| | (Combinational Ticker Filter) | |
| v | |
| < Match? > | |
| / \ | |
| Yes / \ No | |
| v v | |
| [ hash_table.sv ] ---> [ Dropped (0 stall) ] | |
| (16,384-slot LP) | |
| | | |
| | Insert / Delete / | |
| | Replace / Execute | |
| v | |
| [ pla.sv (Price Level Array) ] | |
| (1024 1c Buckets/Side/Stock) | |
| | | |
| v | |
| [ bbo_bitmap.sv ] | |
| (2-Stage Priority Enc.) | |
+-------|------------------------------------------|----------------------+
| |
v v
+-------|------------------------------------------|----------------------+
| Peripherals | |
| v |
| [ VGA Controller ] <------------------ [ Compare Latency & BBO ] |
| (Live Order Book & Stats) |
| |
| * Diagnostic metrics also routed to VGA from hash_table.sv & bbo |
+-------------------------------------------------------------------------+
- Zero-Latency Parse-Time Filtering: incoming ITCH messages are combinationally matched against 4 programmed ticker IDs. Non-matching messages are dropped instantly before they touch the hash table, avoiding any performance degradation.
- Deterministic Hardware Order Book: a 16,384-slot open-addressed, linear-probing hash table manages active orders in on-chip M10K BRAM. Includes backward-shift deletion to avoid tombstone fragmentation.
- Hardware Best Bid/Offer (BBO) Engine: price-level arrays track aggregate resting quantities at 1-cent resolution across a $10.24 window, backed by a 2-stage combinational priority encoder to extract BBO inside 2 clock cycles.
- Live VGA Status Dashboard: renders real-time diagnostics directly from the hardware counters, exposing total messages, parser errors, hash table load factors, maximum collision probe depths, and active BBO metrics.
- ARM Userspace Reference Model: a software reference implementation running on the dual-core Cortex-A9 CPU to validate the accuracy of the FPGA logic and measure latency comparisons.
The repository is structured into two main components:
Contains the SystemVerilog RTL, Platform Designer (Qsys) system configs, and the Quartus Prime project files.
- Go to: Hardware Build & Register Reference
- Quick Compilation:
cd hw/quartus make qsys # Generate Platform Designer system make quartus # Run full Quartus compilation to SOF make rbf # Generate raw binary file for SD card boot
Contains HPS userspace programs, benchmark utilities, and verification tests.
- Go to: Software Compilation & Running Guide
- Quick Run:
cd sw/userspace make # Build itch_load, itch_arm, and vga_writer # Run ingestion of test stream for ticker 'AAPL' sudo ./itch_load input/stress_500.bin AAPL # Launch the live VGA display dashboard (run in a separate terminal) sudo ./vga_writer
We run rigorous stress tests to validate our pipeline, ranging from mixed-workload churn to adversarial collision saturation. See sw/userspace/README.md#3-test-files-input for the full test suite matrix and expectations.