GICv3 emulation

libsel4arm-vmm/CMakeLists.txt

@@ -40,12 +40,22 @@ file(
     GLOB
         sources
         src/*.c
-        src/arch/arm/*/*.c
         src/images/*.c
         src/devices/*.c
         src/plat/${KernelPlatform}/*/*.c
         src/sel4_arch/${KernelSel4Arch}/*.c
 )
+list(APPEND
+           sources
+           src/arch/arm/devices/vram.c
+)
+
+if(KernelPlatformImx8mq-evk)
+    list(APPEND sources src/arch/arm/devices/vgic_v3.c)
+else()
+    # currently every other supported core uses the gicv2.
+    list(APPEND sources src/arch/arm/devices/vgic_v2.c)
+endif()
 
 add_library(sel4arm-vmm STATIC EXCLUDE_FROM_ALL ${sources})
 target_include_directories(sel4arm-vmm PUBLIC include plat_include/${KernelPlatform})

libsel4arm-vmm/include/sel4arm-vmm/devices.h

@@ -25,8 +25,10 @@ typedef struct vm vm_t;
 enum devid {
     DEV_RAM,
     DEV_VGIC_DIST,
-    DEV_VGIC_CPU,
-    DEV_VGIC_VCPU,
+    DEV_VGIC_V2_CPU,
+    DEV_VGIC_V2_VCPU,
+    DEV_VGIC_V3_REDIST,
+    DEV_VGIC_V3_REDIST_SGI,
     DEV_IRQ_COMBINER,
     DEV_PWM_TIMER,
     DEV_WDT_TIMER,

libsel4arm-vmm/include/sel4arm-vmm/fault.h

@@ -29,6 +29,13 @@ enum fault_width {
 #define CPSR_THUMB                 BIT(5)
 #define CPSR_IS_THUMB(x)           ((x) & CPSR_THUMB)
 
+typedef enum {
+    DATA,
+    PREFETCH,
+    WFI,
+    SMC
+} fault_type_t;
+
 /**
  * Data structure representating a fault
  */
@@ -50,10 +57,8 @@ struct fault {
     seL4_Word data;
 /// Fault status register (IL and ISS fields of HSR cp15 register)
     seL4_Word fsr;
-/// 'true' if the fault was a prefetch fault rather than a data fault
-    bool is_prefetch;
-/// 'true' if we should wait for an interrupt before finishing the fault
-    bool is_wfi;
+/// type of the fault
+    fault_type_t type;
 /// For multiple str/ldr and 32 bit access, the fault is handled in stages
     int stage;
 /// If the instruction requires fetching, cache it here
@@ -85,6 +90,9 @@ fault_t *fault_init(vm_t *vm);
  */
 int new_wfi_fault(fault_t *fault);
 
+/** As per new_wfi_fault, but set the type to SMC
+ */
+int new_smc_fault(fault_t *fault);
 /**
  * Populate an initialised fault structure with fault data obtained from
  * a pending fault IPC message. The reply cap to the faulting TCB will

libsel4arm-vmm/include/sel4arm-vmm/psci.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright 2019, Data61
+ * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
+ * ABN 41 687 119 230.
+ *
+ * This software may be distributed and modified according to the terms of
+ * the BSD 2-Clause license. Note that NO WARRANTY is provided.
+ * See "LICENSE_BSD2.txt" for details.
+ *
+ * @TAG(DATA61_BSD)
+ */
+
+#pragma once
+
+/* Values in this file are taken from the:
+ * ARM Power State Coordination Interface
+ * Platform Design Document
+ * Issue D
+ */
+
+typedef enum psci {
+    PSCI_VERSION = 0x0,
+    PSCI_CPU_SUSPEND = 0x1,
+    PSCI_CPU_OFF =     0x2,
+    PSCI_CPU_ON  =     0x3,
+    PSCI_AFFINTY_INFO = 0x4,
+    PSCI_MIGRATE   =   0x5,
+    PSCI_MIGRATE_INFO_TYPE = 0x6,
+    PSCI_MIGRATE_INFO_UP_CPU =       0x7,
+    PSCI_SYSTEM_OFF   =     0x8,
+    PSCI_SYSTEM_RESET  =    0x9,
+    PSCI_FEATURES = 0xa,
+    PSCI_CPU_FREEZE = 0xb,
+    PSCI_CPU_DEFAULT_SUSPEND = 0xc,
+    PSCI_NODE_HW_STATE = 0xd,
+    PSCI_SYSTEM_SUSPEND = 0xe,
+    PSCI_SET_SUSPEND_MODE = 0xf,
+    PSCI_STAT_RESIDENCY = 0x10,
+    PSCI_STAT_COUNT = 0x11,
+    PSCI_SYSTEM_RESET2 = 0x12,
+    PSCI_MEM_PROTECT = 0x13,
+    PSCI_MEM_PROTECT_CHECK_RANGE = 0x14,
+    PSCI_MAX = 0x1f
+} psci_id_t;
+
+/* psci return codes */
+#define PSCI_SUCCESS 0
+#define PSCI_NOT_SUPPORTED -1
+#define PSCI_INVALID_PARAMETERS -2
+#define PSCI_DENIED -3
+#define PSCI_ALREADY_ON -4
+#define PSCI_ON_PENDING -5
+#define PSCI_INTERNAL_FAILURE -6
+#define PSCI_NOT_PRESENT -7
+#define PSCI_DISABLED -8
+#define PSCI_INVALID_ADDRESS -9

libsel4arm-vmm/include/sel4arm-vmm/smc.h

@@ -0,0 +1,75 @@
+/*
+ * Copyright 2019, Data61
+ * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
+ * ABN 41 687 119 230.
+ *
+ * This software may be distributed and modified according to the terms of
+ * the BSD 2-Clause license. Note that NO WARRANTY is provided.
+ * See "LICENSE_BSD2.txt" for details.
+ *
+ * @TAG(DATA61_BSD)
+ */
+#pragma once
+
+/* Values in this file are taken from:
+ * SMC CALLING CONVENTION
+ * System Software on ARM (R) Platforms
+ * Issue B
+ */
+
+#define SMC_CALLING_CONVENTION BIT(31)
+#define SMC_CALLING_CONVENTION_32 0
+#define SMC_CALLING_CONVENTION_64 1
+#define SMC_FAST_CALL BIT(31)
+
+#define SMC_SERVICE_CALL_MASK 0x3F
+#define SMC_SERVICE_CALL_SHIFT 24
+
+#define SMC_FUNC_ID_MASK 0xFFFF
+
+/* SMC and HVC function identifiers */
+typedef enum {
+    SMC_CALL_ARM_ARCH = 0,
+    SMC_CALL_CPU_SERVICE = 1,
+    SMC_CALL_SIP_SERVICE = 2,
+    SMC_CALL_OEM_SERVICE = 3,
+    SMC_CALL_STD_SERVICE = 4,
+    SMC_CALL_STD_HYP_SERVICE = 5,
+    SMC_CALL_VENDOR_HYP_SERVICE = 6,
+    SMC_CALL_TRUSTED_APP = 48,
+    SMC_CALL_TRUSTED_OS = 50,
+    SMC_CALL_RESERVED = 64,
+} smc_call_id_t;
+
+static inline smc_call_id_t smc_get_call(uintptr_t func_id)
+{
+    seL4_Word service = ((func_id >> SMC_SERVICE_CALL_SHIFT) & SMC_SERVICE_CALL_MASK);
+    assert(service >= 0 && service <= 0xFFFF);
+
+    if (service <= SMC_CALL_VENDOR_HYP_SERVICE) {
+        return service;
+    } else if (service < SMC_CALL_TRUSTED_APP) {
+        return SMC_CALL_RESERVED;
+    } else if (service < SMC_CALL_TRUSTED_OS) {
+        return SMC_CALL_TRUSTED_APP;
+    } else if (service < SMC_CALL_RESERVED) {
+        return SMC_CALL_TRUSTED_OS;
+    } else {
+        return SMC_CALL_RESERVED;
+    }
+}
+
+static inline bool smc_call_is_32(uintptr_t func_id)
+{
+    return !!(func_id & SMC_CALLING_CONVENTION) == SMC_CALLING_CONVENTION_32;
+}
+
+static inline bool smc_call_is_atomic(uintptr_t func_id)
+{
+    return !!(func_id & SMC_FAST_CALL);
+}
+
+static inline uintptr_t smc_get_function_number(uintptr_t func_id)
+{
+    return (func_id & SMC_FUNC_ID_MASK);
+}

libsel4arm-vmm/plat_include/imx8mq-evk/sel4arm-vmm/plat/device_map.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright 2018, Data61
+ * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
+ * ABN 41 687 119 230.
+ *
+ * This software may be distributed and modified according to the terms of
+ * the BSD 2-Clause license. Note that NO WARRANTY is provided.
+ * See "LICENSE_BSD2.txt" for details.
+ *
+ * @TAG(DATA61_BSD)
+ */
+
+#pragma once
+
+/***** Physical Map ****/
+#define RAM_BASE  0x80000000
+#define RAM_END   0x88000000
+#define RAM_SIZE (RAM_END - RAM_BASE)

libsel4arm-vmm/plat_include/imx8mq-evk/sel4arm-vmm/plat/devices.h

@@ -0,0 +1,21 @@
+/*
+ * Copyright 2018, Data61
+ * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
+ * ABN 41 687 119 230.
+ *
+ * This software may be distributed and modified according to the terms of
+ * the BSD 2-Clause license. Note that NO WARRANTY is provided.
+ * See "LICENSE_BSD2.txt" for details.
+ *
+ * @TAG(DATA61_BSD)
+ */
+
+#pragma once
+
+#include <sel4arm-vmm/plat/device_map.h>
+#include <sel4arm-vmm/vm.h>
+
+#define GIC_DIST_PADDR    0x38800000
+#define GIC_REDIST_PADDR  0x38880000
+#define MAX_VIRQS         512
+extern const struct device dev_vram;

libsel4arm-vmm/sel4_arch_include/aarch64/sel4arm-vmm/sel4_arch/fault.h

@@ -22,3 +22,13 @@ static inline bool sel4arch_fault_is_thumb(fault_t *f)
 {
     return CPSR_IS_THUMB(fault_get_ctx(f)->spsr);
 }
+
+static inline seL4_Word smc_get_function_id(seL4_UserContext *u)
+{
+    return u->x0;
+}
+
+static inline seL4_Word smc_set_return_value(seL4_UserContext *u, seL4_Word val)
+{
+    u->x0 = val;
+}

libsel4arm-vmm/sel4_arch_include/arm_hyp/sel4arm-vmm/sel4_arch/fault.h

@@ -22,3 +22,13 @@ static inline bool sel4arch_fault_is_thumb(fault_t *f)
 {
     return CPSR_IS_THUMB(fault_get_ctx(f)->cpsr);
 }
+
+static inline seL4_Word smc_get_function_id(seL4_UserContext *u)
+{
+    return u->r0;
+}
+
+static inline seL4_Word smc_set_return_value(seL4_UserContext *u, seL4_Word val)
+{
+    u->r0 = val;
+}

libsel4arm-vmm/src/arch/arm/devices/gicv2.h

@@ -0,0 +1,90 @@
+/*
+ * Copyright 2017, Data61
+ * Commonwealth Scientific and Industrial Research Organisation (CSIRO)
+ * ABN 41 687 119 230.
+ *
+ * This software may be distributed and modified according to the terms of
+ * the BSD 2-Clause license. Note that NO WARRANTY is provided.
+ * See "LICENSE_BSD2.txt" for details.
+ *
+ * @TAG(DATA61_BSD)
+ */
+
+#pragma once
+
+#include <assert.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#define GIC_DIST_PADDR       (GIC_PADDR + 0x1000)
+#define GIC_CPU_PADDR        (GIC_PADDR + 0x2000)
+#define GIC_VCPU_CNTR_PADDR  (GIC_PADDR + 0x4000)
+#define GIC_VCPU_PADDR       (GIC_PADDR + 0x6000)
+
+#define GIC_ENABLED 1
+
+/* Memory map for GICv2 distributer */
+struct gic_dist_map {
+    uint32_t enable;                /* 0x000 */
+    uint32_t ic_type;               /* 0x004 */
+    uint32_t dist_ident;            /* 0x008 */
+    uint32_t res1[29];              /* [0x00C, 0x080) */
+
+    uint32_t security[32];          /* [0x080, 0x100) */
+
+    uint32_t enable_set[32];        /* [0x100, 0x180) */
+    uint32_t enable_clr[32];        /* [0x180, 0x200) */
+    uint32_t pending_set[32];       /* [0x200, 0x280) */
+    uint32_t pending_clr[32];       /* [0x280, 0x300) */
+    uint32_t active[32];            /* [0x300, 0x380) */
+    uint32_t res2[32];              /* [0x380, 0x400) */
+
+    uint32_t priority[255];         /* [0x400, 0x7FC) */
+    uint32_t res3;                  /* 0x7FC */
+
+    uint32_t targets[255];            /* [0x800, 0xBFC) */
+    uint32_t res4;                  /* 0xBFC */
+
+    uint32_t config[64];             /* [0xC00, 0xD00) */
+
+    uint32_t spi[32];               /* [0xD00, 0xD80) */
+    uint32_t res5[20];              /* [0xD80, 0xDD0) */
+    uint32_t res6;                  /* 0xDD0 */
+    uint32_t legacy_int;            /* 0xDD4 */
+    uint32_t res7[2];               /* [0xDD8, 0xDE0) */
+    uint32_t match_d;               /* 0xDE0 */
+    uint32_t enable_d;              /* 0xDE4 */
+    uint32_t res8[70];               /* [0xDE8, 0xF00) */
+
+    uint32_t sgi_control;           /* 0xF00 */
+    uint32_t res9[3];               /* [0xF04, 0xF10) */
+    uint32_t sgi_pending_clr[4];    /* [0xF10, 0xF20) */
+    uint32_t res10[40];             /* [0xF20, 0xFC0) */
+
+    uint32_t periph_id[12];         /* [0xFC0, 0xFF0) */
+    uint32_t component_id[4];       /* [0xFF0, 0xFFF] */
+};
+
+typedef struct gic_dist_map vgic_reg_t;
+
+static inline struct gic_dist_map *priv_get_dist(void *priv)
+{
+    return (struct gic_dist_map *) priv;
+}
+
+static inline bool gic_dist_is_enabled(struct gic_dist_map *gic_dist)
+{
+    return gic_dist->enable;
+}
+
+static inline void gic_dist_enable(struct gic_dist_map *gic_dist) {
+	gic_dist->enable = 1;
+}
+
+static inline void gic_dist_disable(struct gic_dist_map *gic_dist)
+{
+    gic_dist->enable = 0;
+}
+
+extern const struct device dev_vgic_vcpu;
+extern const struct device dev_vgic_cpu;