Upgrade Cheshire (64-bit CVA6)

[Xeratec]

Upgrades the Cheshire host to a recent main-based version (64-bit CVA6) and rebases
Chimera onto the v0.2.0 template line. Chimera-specific Cheshire changes live on
wiesep/chimera-main.

Rebased onto pulp-platform/chimera:main; supersedes the earlier #82-based version.

The generic (non-Chimera) parts of the Cheshire changes — 32-bit/XLEN parametrization and
the SerialLink-disabled fix — are being upstreamed in pulp-platform/cheshire#287.
Once that merges, wiesep/chimera-main can be rebased on top of it.

Dependencies (Bender.yml / new Bender.local)

• cheshire: pinned commit → wiesep/chimera-main branch
• axi: colluca/axi multicast branch → pinned commit bd1abffc
• common_cells: 1.39.0, overridden in Bender.local to the snitch branch (ca9d577f)
• register_interface: 0.4.3 → 0.4.7
• memory_island: pinned commit → main
• hyperbus: aottaviano/nonfree branch → 0.0.9
• Add Bender.local overrides (common_cells, axi); remove workspace.package_links

Changes

• Switch host to 64-bit: CHS_XLEN=64, cv64a6_imafdchsclic_sv39_wb (was cv32a6_convolve)
• Cheshire AxiDataWidth → 64; add MemIslRegionLength; 64-bit-aware fast preload
• Connect HyperBus to the LLC AXI port and enable the Cheshire LLC
• Fix CVA6 stall error; regenerate Snitch bootrom; fix HyperBus test
• Sim: configurable CHIM_HYPERBUS_SDF_PATH, -suppress 8386

To-do

• Sanity-check the Cheshire changes on wiesep/chimera-main
• Confirm the cheshire commit hash is pinned before merge (currently a branch ref)
• Rebase wiesep/chimera-main onto feat: parametrize Cheshire for 32-bit cores + SerialLink fix cheshire#287 once it lands

[phsauter]

At this point we might want to consider directly moving to the incoming version with CVA6 v3