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Signal Generator - VHDL to SystemVerilog Translation
Behavioral XPM FIFO model and various houskeeping
bram files and comments
Revert "Behavioral XPM FIFO model and various houskeeping"
Behavioral Model of XPM FIFO module and various housekeeping
Emulator nb interface
Updated file names and replaced xilinx IP instantiations
Axis sig gen v6
tb dac+ sig gen set up
sync qick_lab
sig_gen dac tb
…aths to submodules.
…aks the emulator.
using our dac_adc_loopback module
…n avg buffer and tproc, adressed delay issues
Feature/qick emulator pr
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