Update from task cdf7a3e5-93eb-47e5-8875-a11899703d3f - #3
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mathcode220-math merged 1 commit intoJul 27, 2026
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Key features implemented: - Add AXI4-Lite control interface module with timeout protection and register mapping - Implement HDC distance core with pipelined Hamming distance calculation and assertions - Create HDC n-gram encoder with configurable size and circular shift registers - Add parameterized systolic array with processing elements and overflow protection - Implement ReLU activation with signed input handling and saturation - Create fixed-point softmax core with proper division and expanded LUT - Add SRAM skew buffer for systolic array timing management - Integrate top-level module connecting all subsystems with AXI control - Include comprehensive testbenches for matrix multiply and AXI control - Add CI workflow with linting and compilation checks - Create architecture documentation and project Makefile - Establish proper RTL directory structure organized by subsystem This commit establishes a complete foundational hardware design with proper testing and build infrastructure. The modules are now correctly structured and the critical softmax division bug has been fixed.
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This PR was created by qwen-chat coder for task cdf7a3e5-93eb-47e5-8875-a11899703d3f.