CS4223 Cache Coherence Simulator

Requirements

• Python 3.10 or higher

Usage

Part 1: Single Core Simulation

python3 coherence.py <simulator> <trace_file> <cache_size> <associativity> <block_size>

Example

python3 coherence.py single_core ./blackscholes_four/blackscholes_1.data 4096 4 16

Part 2: Multi Core MESI Simulation

python3 coherence.py mesi <trace_folder> <cache_size> <associativity> <block_size>

Example

python3 coherence.py mesi blackscholes_four 8192 16 16

Part 3: Multi Core DRAGON Simulation

python3 coherence.py dragon <trace_folder> <cache_size> <associativity> <block_size>

Example

python3 coherence.py dragon blackscholes_four 8192 16 16

Advanced Task: Multi Core MOESI Simulation

python3 coherence.py moesi <trace_folder> <cache_size> <associativity> <block_size>

Example

python3 coherence.py moesi blackscholes_four 8192 16 16

Parameters

• simulator —
  Specifies the cache simulator type to use.
  Supported options:

  • single_core — Basic single-core cache simulator
  • new_single_core — Updated single-core model with bus broadcast delay
  • mesi — Multi-core simulator implementing the MESI coherence protocol
  • moesi — Multi-core simulator implementing the MOESI coherence protocol
  • dragon — Multi-core simulator implementing the Dragon coherence protocol

• trace_file: Path to the trace file (e.g., blackscholes_0.data)

• trace_folder: Path to the trace folder containing trace files (e.g., blackscholes_four)

• cache_size: Cache size in bytes

• associativity: Cache associativity (e.g., 4 for 4-way set associative)

• block_size: Block size in bytes

Output

The simulation output the following metrics:

• Overall Execution Cycle - Maximum cycle count across all cores
• Compute Cycles per Core - Cycles spent on non-memory operations
• Load/Store Instructions per Core - Count of memory operations
• Idle Cycles per Core - Cycles waiting for cache/memory
• Cache Hit/Miss Counts - Per core statistics
• Data Traffic - Total bytes transferred on the bus
• Invalidations/Updates - Bus transaction counts
• Private vs Shared Data Access per Core - Distribution of access patterns

MESI

Idea

• Memory is also a node on the bus
• Memory will snoop on the bus transactions
• Writes backs from cache will broadcast the line onto the bus, which memory will listen to for the write
• Memory is asynchronous. Writeback to memory is performed asynchronously from the processor
• Non split transaction bus
• data broadcasts does not stall the core. it only occupies the bus.
• address phase is 1 cycle
• memory has single infinite length queue to serve read and write
• everything tracks cycle time e.g cylce time it started/ended
• bus is separate from scheduler.