Booth-Multiplier

• To Program an Application Specific Integrated Chip using Verilog to multiply two 4-Bit numbers using the Booth Multiplication algorithm.
• Booth Multiplication involves the multiplication of two signed binary numbers using their 2's complement notation.
• The simulation was run on Cadence using Genus and the final implementation was planned on Innovus, which also generated area, power usage and timing reports.
• Computation of the product of two N-bit numbers using booth algorithm led to a significant reduction of time complexity from O(N^2) to O(N)
• Technologies Used: Verilog, Cadence.