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1. Real-Time-Image-Enhancement-using-FPGA Real-Time-Image-Enhancement-using-FPGA Public

   This project implements a real-time, hardware-accelerated image processing pipeline on the PYNQ-Z2 (Zynq-7020) FPGA. It leverages an AXI4-Stream architecture to fetch video frames from memory, proc…

   Verilog

2. APB-Packet-Modeling-using-SystemVerilog-OOP APB-Packet-Modeling-using-SystemVerilog-OOP Public

   Forked from Arunkumar-UCEK/APB-Packet-Modeling-using-SystemVerilog-OOP

   Design and verification of an APB (Advanced Peripheral Bus) packet model using SystemVerilog object-oriented programming concepts.

3. CNN_based_FPGA_on_pynq_z2_7020 CNN_based_FPGA_on_pynq_z2_7020 Public

   Verilog 1

4. Assertion-Based-Verification-of-I-C-Protocol-Timing-and-Handshaking-Sequences- Assertion-Based-Verification-of-I-C-Protocol-Timing-and-Handshaking-Sequences- Public

   Forked from Arunkumar-UCEK/Assertion-Based-Verification-of-I-C-Protocol-Timing-and-Handshaking-Sequences-

5. Vlsi_cadence_projects Vlsi_cadence_projects Public

6. UART-APR UART-APR Public

   Forked from Navaneetha-sec/UART-APR