mh_sha1: add an mh_sha1 assembly implementation with vector extension for riscv64

[HeliC829]

This PR added an mh_sha1 assembly implementation with vector extension for riscv64.

Origin C implementation:

mh_sha1_update_base_warm: runtime =     247264 usecs, bandwidth 31 MB in 0.2473 sec = 132.52 MB/s
isal_mh_sha1_update_warm: runtime =    2464763 usecs, bandwidth 312 MB in 2.4648 sec = 132.95 MB/s

Assembly implementation with vector extension :

mh_sha1_update_base_warm: runtime =     213991 usecs, bandwidth 31 MB in 0.2140 sec = 153.13 MB/s
isal_mh_sha1_update_warm: runtime =     863086 usecs, bandwidth 312 MB in 0.8631 sec = 379.66 MB/s

[pablodelara]

This will be merged after the new release is out next month, thanks

[HeliC829]

kindly ping for merge.

[pablodelara]

Sorry @HeliC829 for keeping you waiting. @sunyuechi could you review this PR? Thanks!

[sunyuechi]

0001-mh_sha1-process-all-16-segments-per-pass-in-the-risc.patch

The loop runs many times but vl=4 instead of something big， looks like
fixed-width SIMD usage.

You could use vl=16 and pick m1/m2/m4 based on vlen to cut the iteration
count. I tried it and got another 2-3x.

Maybe amend on top of this patch and see if anything else is worth changing，
If vl=4 is really needed, a comment would help.