chore(runtime): bump simpler to c032e07e#2119
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added 2 commits
July 23, 2026 02:19
Advance the simpler submodule to latest hw-native-sys/simpler main (c032e07e, "make dense dependency diagnostics debug-only" hw-native-sys#1448), covering predicated dispatch for host_build_graph, polling completion scheduler, A5 URMA deferred completion, and TMR early-dispatch port.
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July 23, 2026 23:29
… worker id simpler hw-native-sys#1436 made NEXT_LEVEL placement explicit: submit_next_level requires a non-negative worker id and no longer selects one for the caller. pypto-side adaptations: - _submit_chip routes a comm-less dispatch (worker<0 DFX sentinel) to the local chip worker 0; the -1 still drives the DFX rank_local label. - test_unconstrained_worker_suffixed_as_rank_local expects worker 0 forwarded to simpler (was -1). - test_l3_manual's hand-written orch passes worker=0 to submit_next_level.
Three pto.make_tensor_view emit sites produced `{layout=...}:` (no space
between the attr-dict `}` and the type-signature `:`), while the canonical
MLIR printer always emits `} :`. The non-standard form surfaced as a PTOAS
`expected ':'` diagnostic on CI (reduce_step.pto:24:44) for the allreduce
intrinsic distributed ST.
Align all three sites with EmitCommRemoteView's existing `} :` form:
- pto_codegen.cpp: EmitMakeTensorViews (tensor param views)
- pto_ops_memory.cpp: make_tensor_view emit
- pto_ops_datamove.cpp: DN view emit
…ement regions PTOAS's pto.cmo.cacheinvalid assembly requires a typed operand (`%addr single_cache_line : type`), but the all-ones-sizes scalar-write branch emitted a bare addptr pointer with no type annotation — `pto.cmo.cacheinvalid %ptr single_cache_line` — which PTOAS rejects with "expected ':'". Delete the scalar-write ptr branch so every region (single-element or larger) lowers through partition_tensor_view, matching tile.store's outs() operand. This is the path InsertCommFence (hw-native-sys#2076) hits for a [1,1] signal window, which surfaced as the test_l3_tensor_allreduce_intrinsic[2-1] failure once the runtime bump pulled in a PTOAS that registers cmo.cacheinvalid. Update the cacheinvalid UTs to assert the partition-view form instead of the rejected ptr form.
simpler's NEXT_LEVEL scheduling is directed — submit_next_level takes an explicit non-negative worker id and the runtime never selects one for the caller. pypto's "comm-less" path (chip_orch without device=) worked around this by passing worker=-1 and translating it back to 0 in _submit_chip, which is exactly the negative id simpler's _require_next_level_worker_id exists to reject. Drop the comm-less concept entirely: - codegen errors (CHECK_SPAN) on a chip dispatch with no device= instead of emitting worker=-1 - _submit_chip forwards the caller's worker verbatim; the worker<0->0 translation and the rank_local DFX namespace are removed - the six single-card L3 programs that relied on comm-less now pin device=0 explicitly; rank-pinned dispatch (per-rank for-loop with device=r) is unchanged — r was always a real worker id
The previous commit made chip dispatch require an explicit device=, but missed two distributed programs under examples/ that the CI dist-checkout covers: - examples/runtime/multi_program_kv_cache.py (@pl.jit style): prefill/ decode host kernels now pass device=0 to prefill_chip/decode_chip - examples/runtime/distributed_callback.py (@pl.program style): host_orch passes device=0 to chip_orch Both are single-card L3 programs (device_ids=[0]), so worker 0 is the correct target. inspect_result (SubWorker) is unchanged.
pl.at(level=CHIP, ...) inlines chip orchestration in host_orch, but the synthesised chip dispatch carried no device= attr — it relied on the comm-less (worker=-1) path that simpler's directed NEXT_LEVEL scheduling (hw-native-sys#1436) removed. Multi-chip pl.at programs (two pl.at(CHIP) blocks bound to different cards) had no way to name a target worker. Thread device=<rank> through the pl.at path: - at()/AtContext accept device; the parser stashes it on _AtKwargState and writes it to the Hierarchy scope's "device" attr - the scope outliner copies that attr onto the synthesised Call/Submit's kAttrDevice, so distributed codegen's ResolveRankExpr recovers a real worker id (same path as self.chip_orch(..., device=r)) The two multi-chip inline programs (L3DependencyInlineProgram, L3MultiChipProgram) now pin device=0/1 on their pl.at(CHIP) blocks.
The comm-less removal made chip dispatch require device=, but several UT programs still used self.chip_orch(...) without it. Add device=0 (all single-card programs) to: - tests/ut/codegen/test_distributed_codegen.py (9 chip_orch call sites) - tests/ut/ir/test_distributed_compiled_program.py (fixture program) Also drop the test_comm_less_dispatch_routes_through_submit_chip_unconstrained case (tested the removed -1 path) and the stale comm-less bullet in the test_host_orch_distributed module docstring. test_decorator's chip_orch(a, c) calls are left as-is: those tests exercise _get_deps()/_bind_args() only, no distributed compile.
…hared_zeros The previous sed pass matched only `self.chip_orch(` and missed the `chip_orch_add` / `chip_orch_sub` call sites (different suffix), leaving test_create_tensor_shared_zeros_for_multiple_tensors without device=.
…lated to comm-less)
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Summary
runtime(simpler) submodule to the latesthw-native-sys/simplermain atc032e07e("make dense dependency diagnostics debug-only", simpler [Pass Bug] UP_DOWN split + dynamic valid_rows > HALF silently drops subblock 1 writes #1448)8cdb306c(# [Bug]tile.castandtile.row_sumget wrongvalid_shape#1401)host_build_graph(a2a3), polling completion scheduler, A5 URMA deferred completion, TMR early-dispatch port, Remote L3 startup deadline hardening, singleTaskAttrsbyte consolidationTesting