Cannot synthesize arith-ops outside always blocks & weird bitwidths

[PigBrainOverflow]

/* Generated Module */
module sub_mul_3_stage_16_bit (
    input clk,
    input [15:0] d,
    input [15:0] a,
    input [15:0] b,
    output [15:0] out
);

    // declarations
    wire [15:0] wire_0;
    wire [15:0] wire_1;
    wire [15:0] wire_3;
    wire [15:0] wire_5;
    wire [15:0] wire_7;
    reg [15:0] reg_2;
    reg [15:0] reg_4;
    reg [15:0] reg_6;
    assign wire_0 = d - a;
    assign wire_1 = wire_0 * b;
    assign wire_3 = reg_2;
    assign wire_5 = reg_4;
    assign wire_7 = reg_6;
    assign out = wire_7;

    always @ (posedge clk) begin
        reg_2 <= wire_1;
        reg_4 <= wire_3;
        reg_6 <= wire_5;
    end

endmodule

Lakeroad cannot synthesize it though it is behaviorally equivalent to the example sub_mul.sv.

[PigBrainOverflow]

Not a must but good to be able to synthesize code like this.

[PigBrainOverflow]

Update: After tuning timeout option, Lakeroad can synthesize arith-ops outside always blocks (though very slow). It's still unknown to me how to config pipeline registers' bitwidths.

[gussmith23]

What do you mean by "configure pipeline registers' bitwidths"? In general, you don't need to do any configuration regarding the internals of the module you're compiling -- you just need to describe the externally-visible behavior (pipeline depth, input and output bitwidth, functionality)