Add Yosys STA for frequency estimation

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Librelane https://www.zerotoasiccourse.com/terminology/librelane/ uses the Sky130 PDK

[avikde]

OpenLANE uses ABC's stime -p inside abc -script for timing estimates, not Yosys's sta

[avikde]

As of 805e717 we have a Delay output from STA. current 3.5% over.

Potential experiments at this stage:

1. Array size scaling (SIM_ROWS/SIM_COLS)
Since every PE has a pipeline register at its output, the critical path is entirely inside one PE (the weight_r * data_in mult → acc_in + mult_result add → mux → register). Vary size from 4×4 up to 64×64 — you should see constant timing regardless of array size, confirming the design scales.

for size in 4 8 16 32 64; do
  cmake -B build -DSIM=ON -DSIM_ROWS=$size -DSIM_COLS=$size
  cmake --build build --target synth
  grep "Delay" build/synth_outputs/synth_timing.rpt
done

2. Clock period sweep (CLOCK_PERIOD_NS)
ABC maps to faster (larger) cells under tighter timing. Sweep 2ns → 20ns at a fixed array size and watch the area vs. frequency tradeoff in synth_stats.txt (total cell count or gate area).

for period in 2 3 5 10 20; do
  cmake -B build -DSIM=ON -DCLOCK_PERIOD_NS=$period
  cmake --build build --target synth
done

3. Data width (DATA_WIDTH in pe.sv)
The 8×8→32 multiplier is the timing bottleneck. You'd need to edit synth.cmake (lines 49–50: DW/AW) to try 4-bit or 16-bit PEs. Expect delay to scale roughly linearly with width — easy to script once you expose it as a CMake variable.

4. Pipeline depth (edit pe.sv)
Add a pipeline register after the multiplier (mult_r <= weight_r * data_in) to split the critical path into mult + add pipeline stages. Then re-synthesize to see the period halve (at the cost of 2× latency and more flip-flops). This is the classic architectural tradeoff between throughput and area/timing.

The array size experiment (1) is the most immediately satisfying — it directly validates the systolic architecture's scalability claim. The clock period sweep (2) is the next best for exploring ABC's technology mapping behavior.

[avikde]

With size

4x4: Delay = 10483.05 ps
8x8: Delay = 10483.05 ps
16x16: Delay = 10483.05 ps
32x32: Delay = 10483.05 ps

[avikde]

The sweep scripts are not working properly yet.

• Try to just run one at a time and manually tabulate results