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489 mixed writeback sync#10

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and0d0 wants to merge 25 commits into
489-mergefrom
489-mixed-writeback-sync
Open

489 mixed writeback sync#10
and0d0 wants to merge 25 commits into
489-mergefrom
489-mixed-writeback-sync

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@and0d0 and0d0 commented Jul 16, 2026

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@and0d0
and0d0 force-pushed the 489-mixed-writeback-sync branch from f93dff1 to 84d211b Compare July 17, 2026 03:07
TaoTao-real and others added 8 commits July 17, 2026 11:26
…mory-consistency-pass

Remove automatic memory consistency pass
删除 @pto.simt 装饰器的 max_regs 参数,不再作为对外公开接口。
simt-max-registers 已由 VPTO 后端根据 max_threads 自动推导(hw-native-sys#949),
无需用户手工指定,PTODSL 侧同步删除对应参数。

变更:
- _subkernels.py: 从 SubkernelSpec、_SubkernelSurface、simt() 等
  删除 max_regs 参数和相关逻辑
- _tracing/session.py: 删除 pto.simt_max_regs 的 MLIR 属性发射
- test_jit_compile.py: 更新测试,移除 max_regs 相关断言
- 设计文档和用户指南: 移除 max_regs 描述,标注寄存器预算自动推导

保留 include/PTO/IR/PTO.h 中的属性定义,保证已有 IR 向后兼容。

相关 hw-native-sys#527
…-max-regs-api

refactor(ptodsl): Remove max_regs parameter from @pto.simt decorator
…-native-sys#924)

* fix(TileOps): correct nd2nz/dn2nz src_inner_stride to use src physical stride in bytes

* fix(TileOps): correct tstore acc2gm src/dst stride to use tile rows and GM physical stride

* resolve commet

* Update new tilelib framwork
@and0d0
and0d0 force-pushed the 489-mixed-writeback-sync branch 5 times, most recently from 18103b4 to 89183a6 Compare July 19, 2026 19:29
@and0d0
and0d0 force-pushed the 489-mixed-writeback-sync branch from 89183a6 to 9d426e7 Compare July 20, 2026 17:42
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8 participants