A fix and future proofing for the sc598 clk pll driver

[ukleinek]

PR Description

While trying to update the adsp-6.18.31-y branch to a newer upstream version (here: 7.2-rc3) I found that the pll driver needs an adaption for a clk subsystem change that happend during the v7.1 merge window (specifically commit dc652a33cf08 ("clk: remove round_rate() clk ops"). While looking at the .round_rate() callback I spotted the issues fixed in the first commit.

PR Type

• Bug fix (a change that fixes an issue)
• New feature (a change that adds new functionality)
• Breaking change (a change that affects other repos or cause CIs to fail)

PR Checklist

• I have conducted a self-review of my own code changes
• I have compiled my changes, including the documentation
• I have tested the changes on the relevant hardware
• I have updated the documentation outside this repo accordingly
• I have provided links for the relevant upstream lore

[github-actions]

LLM review

This series fixes multiple bugs in the ADI SC5xx CGU PLL clock driver related to pll->half_m not being consistently applied, and converts the driver from the deprecated .round_rate() callback to .determine_rate() ahead of its removal in v7.1-rc1.

run: 29411476882

bc824dfe - Fix round rate to consistently consider pll->half_m

The fix is correct and addresses multiple bugs in the original sc5xx_cgu_pll_round_rate():

1. After updating prate via clk_hw_round_rate() (when m > pll->max), m was not recalculated — meaning the subsequent early-exit check and new_rate computation used a stale m.
2. The m > pll->max fallback return was missing the half_m multiplier: returned prate * pll->max instead of prate * pll->max * 2.
3. The m == 0 error path reported and returned prate instead of prate * (half_m ? 2 : 1).
4. The alternative parent-halving path used rate / prate2 (no half_m) and prate * m2 (wrong base rate — should be prate2) for nr2.

All fixes are logically sound.

818885e - Convert to .determine_rate()

The conversion is mechanically correct. The single-parent nature of the PLL (num_parents = 1) means req->best_parent_hw is pre-populated by clk_core_init_rate_req() and does not need to be explicitly set by the driver. The CLK_SET_RATE_PARENT flag is retained.

CI warnings

The checkpatch warning for bc824dfe ("Unknown commit id '8f0186bf3f78'") is a false positive: the original introducing commit is not present in this downstream fork's git history. No action needed.

The CI note "Smatch not found, skipped" is an infrastructure limitation and does not affect the review.

Verification data

• Compiled drivers/clk/adi/clk-adi-pll.o with gcc_aarch64 (sc598-som-ezkit_defconfig) and gcc_arm via make W=1 — no warnings or errors.
• scripts/checkpatch.pl --strict run on both patches individually; only the false-positive Fixes-tag warning was emitted.
• clk_rate_request struct, clk_core_init_rate_req(), and clk_calc_new_rates() reviewed in drivers/clk/clk.c to confirm API usage is correct.