Simons version

README.md

@@ -1,64 +1,79 @@
-# Vivado MODULE NAME
+# AXI Stream compatible Skidbuffer in VHDL
+---
 
-This repo contains scripts to recreate **DESCRIBE THE MODULE HERE**. The project is setup for Zedboard, although it would be easy to change to other boards assuming you have some basic TCL skills.
+## AXI4 to AXIS converter
 
-# Module/IP design
+The purpose of the entire project is to build an IP core to convert the AXI4 write channel to AXIS interface.
+To achieve this, the incomming AXI4 slave port must be registered. Registering a handshake bus protocol comes with the requirement for a skidbuffer.
+See below for the details on the skidbuffer implementation.
+Once the skidbuffer is operational, the AXI4 write channel can just be passed to an AXIS master interface (including handshake compatibility with `tready` and `wready` signals).
+However, the AXI4 port still requires some additional features like aknowledging requests on the AW channel and sending positive write responses on the B channel (`bresp`). All of this is taken care of in this IP core.
 
-Describe here your module interface and protocols.
+### Features
 
-![Place here a nice picture of your design](my-awesome-module.png)
+- accepts `S_AXI4` write request handshakes on AW-channel
+	+ accepts up to one additional AW request while a write burst is still in progress allowing for...
+	+ back-to-back write transactions
+- supports full AXI4 thorughput for burst transfers without wait cycles
+- `S_AXI4` W to `M_AXIS` conversion
+- supports `tready` backpressure forwarded to upstream `S_AXI4` (both `wready` and `awready`)
+- `S_AXI4` write acknowledgement (`bresp` = OK) after burst transfer (after `tlast`)
 
-# How to use this repository
+![img/gtkwave_axi-to-axis.png](img/gtkwave_axi-to-axis.png)
 
-These scripts presented here are quite reusable if you keep the same dir structure. It should be useful for other Vivado/SDK projects with minor efforts. For this reason this repository is a template. Just click in **Use this Template** button to replicate it for your own project.
+---
+## Skidbuffer Idea
 
-In command line, create an empty repository called *<your-reponame>* in github and follow these steps to use it as a template:
+### Passthrough Skid Buffer
 
-```
-mkdir <my-new-project>
-cd <my-new-project>
-git clone https://github.com/amamory/vivado-base-project.git .
-rm -rf .git
-git init
-git remote set-url origin https://github.com/<your-username>/<your-reponame>
-git add * .gitignore
-git commit -m "my initial commit"
-git push origin master
-```
+Only the reply signal from downstream slave to upstream master (`tready`) is pipelined.
 
-Each directory has instructions related to the kind of file you have to place in them.
+All other signals from upstream master to downstream slave (`tvalid`, `tdata`, `tlast`) are *combinatorial*.
+It therefore has 0 latency in the best case and maximum 1 clock cycle latency in case of a stall.
+However, it increases combinatorial logic in the master -> slave path which can make it harder to meet timing requirements.
 
-# How to run it
+#### Schematic
+![img/skidbuf_passthru.png](img/skidbuf_passthru.png)
 
-These scripts are assuming Linux operation system (Ubuntu 18.04) and Vivado 2018.2.
+#### Waveform
+![img/skidbuf_passthru_wave.svg](img/skidbuf_passthru_wave.svg)
+![img/gtkwave_passthru.png](img/gtkwave_passthru.png)
 
-Follow these instructions to recreate the Vivado and SDK projects:
- - Open the **build.sh** script and edit the first lines to setup these environment variables:
-    - **VIVADO**: path to the Vivado install dir;
-    - **VIVADO_DESIGN_NAME**: mandatory name of the design;
-    - **XIL_APP_NAME**: used only in projects with software;
-    - **VIVADO_TOP_NAME**: set the top name (optional).  
- - run *build.sh*
+### Fully Pipelined Skid Buffer
 
-These scripts will recreate the entire Vivado project, compile the design, generate the bitstream, export the hardware to SDK, create the SDK projects, import the source files, build all projects, and finally download both the bitstream and the elf application. Hopefully, all these steps will be executed automatically.
+With registered outputs for all signals.
+It therefore has a minimum latency of 1 clock cycle and a maximum of 2 clock cycles in case of a stall.
+This is a pipeline register to help reach timing closure.
 
-# How to update the scripts
+#### Schematic
+![img/skidbuf_fullreg.png](img/skidbuf_fullreg.png)
 
-These scripts come from a template repository and they get updated and improved over time. If you wish to get the latest script version, then follow these steps:
+#### Waveform
+![img/skidbuf_fullreg_wave.svg](img/skidbuf_fullreg_wave.svg)
+![img/gtkwave_fullreg.png](img/gtkwave_fullreg.png)
 
+## Simulation
+
+Assuming `ghdl` and `gtkwave` installed on Windows.
+
+Run in powershell:
+
+```batch
+.\compile.bat
 ```
-git remote add template https://github.com/amamory/vivado-base-project.git
-git fetch --all
-git merge --no-commit --no-ff template/master --allow-unrelated-histories
-```
 
-Solve any conflict manually and then commit.
+# Acknowledgements
+
+https://zipcpu.com/blog/2019/05/22/skidbuffer.html
+
+
+### Anti-Acknowledgements
+
+This article did **NOT** help: it is confusing since the code does not match the schematic.
 
-# Future work
+https://www.itdev.co.uk/blog/pipelining-axi-buses-registered-ready-signals
 
- - update the scripts to Vitis
- - support or test with Windows (help required !!! :D )
+# Tools
 
-# Credits
+Simulated using GHDL 3.7 / implemented and tested with Xilinx Vivado 2021.2
 
-The scripts are based on the excellent scripts from [fpgadesigner](https://github.com/fpgadeveloper/zedboard-axi-dma) plus few increments from my own such as project generalization, support to SDK project creation and compilation and other minor improvements.