tmrctr: initialize PWM and timer state variables#383
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- Split XPmSubsystem_GetSubSysIdByIpiMask() into a core helper and a redundant wrapper guarded by XSECURE_REDUNDANT_CALL. Explicitly handle zero IPI mask and return PM_SUBSYS_INVALID on mismatch to mitigate fault-injection glitches. No functional change in normal operation. Signed-off-by: Trung Tran <trung.tran@amd.com> Acked-by: Nicole Baze <amanda.baze@amd.com>
- Replace XPm_Out32 with XSECURE_REDUNDANT_IMPL in XPm_LockPcsr - Improves robustness against fault injection on PCSR lock write - Affects versal_2ve_2vm/xpm_common.c; no functional change expected Signed-off-by: Trung Tran <trung.tran@amd.com> Acked-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>
Add redundant validation in IOCTL_READ_REG and IOCTL_MASK_WRITE_REG cases to detect fault injection attacks. Use volatile variables to prevent compiler optimizations that could weaken security checks. Signed-off-by: Trung Tran <trung.tran@amd.com> Acked-by: Nicole Baze <amanda.baze@amd.com>
Implement redundant validation using XSECURE_REDUNDANT_CALL macro to protect against single fault injection attacks in IOCTL device ID validation. Signed-off-by: Trung Tran <trung.tran@amd.com> Acked-by: Izhar Ameer Shaikh <izhar.ameer.shaikh@amd.com>
Implement security hardening and code quality improvements in the AMS trim module. The primary change adds temporal checking to prevent potential security vulnerabilities in the cache copy operation. Changes include: - Wrap AmsTrim_CopyCache with XSECURE_TEMPORAL_CHECK macro - Define constants for all TSENS delta offsets and bit positions - Replace numeric literals with self-documenting constants - Add explicit cache read state definitions - Include loop iteration verification for robustness - Mark loop counter as volatile for security No functional changes to the AMS trim algorithm. Signed-off-by: Trung Tran <trung.tran@amd.com> Acked-by: Nicole Baze <amanda.baze@amd.com>
Replace hardcoded array indices and magic numbers in AddDevAttributes() with descriptive macros. This improves code readability and makes the argument structure explicit. Changes include: - Define ARG_IDX_DEVATTR_* macros for argument array positions - Replace hardcoded '9U' and '12U' with DEVATTR_ARG_MIN/MAX_LEN - Define bit shift and mask constants for security, coherency, and virtualization attributes Signed-off-by: Trung Tran <trung.tran@amd.com> Acked-by: Izhar Ameer Shaikh <izhar.ameer.shaikh@amd.com>
Map PM_HNICX_NPI_DATA_XFER to a no-op warning handler and drop the XPm_DoHnicxDataXfer() helper. Remove unused HNICX power up/down stubs and HNICX_NPI register definitions. This trims unused code paths for 2VE/2VM builds and simplifies maintenance. No functional change for supported platforms. Signed-off-by: Trung Tran <trung.tran@amd.com> Acked-by: Nicole Baze <amanda.baze@amd.com>
- Sync ReduceCfuClkFreq() from xilpm library - Sync RestoreCfuClkFreq() from xilpm library - Update xpm_regs.h: add CRP_CFU_REF_CTRL_DIVISOR0_MASK_MSB to match xilpm - No functional change intended Signed-off-by: Trung Tran <trung.tran@amd.com> Acked-by: Nicole Baze <amanda.baze@amd.com>
- Make Status volatile in FpdAmsTrim to avoid optimization issues in embedded contexts - Declare loop index i separately to enable post-loop iteration validation - Reset Status to XST_FAILURE before XPm_ApplyAmsTrim to catch failures - Apply AMS trim to FPD SysMon instances; on failure set DbgErr XPM_INT_ERR_AMS_TRIM - Add glitch check: ensure i == XPM_NODEIDX_MONITOR_SYSMON_FPD_3 + 1; else error - Improve debug reporting via XPm_PrintDbgErr; no intended functional change Signed-off-by: Trung Tran <trung.tran@amd.com> Acked-by: Nicole Baze <amanda.baze@amd.com>
- Add static inline XPmRequirement_IsAllocated to check Reqm->Allocated - Use XSECURE_REDUNDANT_CALL in XPmDevice_CheckPermissions for glitch detection - Make Status/StatusTmp volatile; treat any mismatch as no access - No functional change. Signed-off-by: Trung Tran <trung.tran@amd.com> Acked-by: Nicole Baze <amanda.baze@amd.com>
- Use XSECURE_REDUNDANT_CALL to invoke SysmonVoltageCheck when thresholds are not programmed - Add volatile XStatus variables (Status, StatusTmp) to support redundancy patterns - Treat either-call failure as error; set DbgErr to XPM_INT_ERR_POWER_SUPPLY and exit - Improves robustness and error reporting; no expected functional change in normal cases Signed-off-by: Trung Tran <trung.tran@amd.com> Acked-by: Nicole Baze <amanda.baze@amd.com>
- Define voltage code constants (VOLT_CODE_0_66V, VOLT_CODE_0_745V, VOLT_CODE_1_40V) for SysMon threshold comparisons - Replace hardcoded hex values in RailVoltageTable with named constants to improve code readability and maintainability - Apply consistent formatting to the voltage table entries - No functional changes, only code cleanup Signed-off-by: Trung Tran <trung.tran@amd.com> Acked-by: Nicole Baze <amanda.baze@amd.com>
Refactor the node access handling logic to be idempotent, ensuring that multiple calls to set access rules do not create duplicate entries. The `XPmAccess_UpdateTable` function is modified to implement an "update or append" behavior. It now searches for an existing aperture with the same offset and size. If found, it updates the access field; otherwise, it appends a new aperture. This change simplifies the calling code in `XPm_DoSetNodeAccess`, which no longer needs to manage `XPm_NodeAccess` allocations, improving encapsulation and robustness. Signed-off-by: Trung Tran <trung.tran@amd.com> Acked-for-series: Izhar Ameer Shaikh <izhar.ameer.shaikh@amd.com>
Convert PmNodeAccessTable to an init-data array sized by XPM_NODE_ACCESS_TABLE_SIZE and include it in XPmInitData EXPORT_DS to support IPU (Impactless PLM Update) state export/restore. Include xpm_access.h and switch references to index 0. No functional change. Signed-off-by: Trung Tran <trung.tran@amd.com> Acked-for-series: Izhar Ameer Shaikh <izhar.ameer.shaikh@amd.com>
- Introduce CUSTOM_COMPILE_OPTIONS with -Wall, -Wextra, -Wconversion, -Wundef, -fno-common, etc. - Append options to CMAKE_C_FLAGS to strengthen checks for xilpm_ng sources - Improve build-time diagnostics to catch UB, truncation, and API misuse earlier - No functional changes; build configuration only Signed-off-by: Trung Tran <trung.tran@amd.com> Acked-for-series: Nicole Baze <amanda.baze@amd.com>
- Add missing prototypes in domain headers; include headers in xpm_powerdomain.c - Mark internal functions static; include missing xpm_device_fsm.h - Fix types/casts and apply masks for apertures; use unsigned suffixes where needed - Adjust macro guards for XIicPs; narrow XPmRail_Control mode to u8 - Drop unused variables/externs; update copyright years - No functional change; warning fixes only Signed-off-by: Trung Tran <trung.tran@amd.com> Acked-for-series: Nicole Baze <amanda.baze@amd.com>
Replace hardcoded array indices and magic numbers in AddMemRegnDevice() with descriptive macros. This improves code readability and makes the argument structure explicit. Changes include: - Define ARG_IDX_* macros for argument array positions - Replace hardcoded '5U' with MEM_REG_ARG_MAX_LEN - Replace hardcoded '32' with SHIFT_TO_HIGH_U32 Signed-off-by: Trung Tran <trung.tran@amd.com> Acked-by: Izhar Ameer Shaikh <izhar.ameer.shaikh@amd.com>
Include PUF_RSVD efuse in PUF user data programming. Before this patch valid index of puf efuse was 1 to 127. After including PUF_RSVD new index will be 0 to 127. This patch will increase no of user data efuse from 127 to 128. Signed-off-by: Harsh Jain <h.jain@amd.com> Acked-by: Durga Challa <durga.challa@amd.com>
Fix the folowing compiler warnings in xpm_subsystem.c:
xpm_subsystem.c:622:1: error: "/*" within comment [-Werror=comment]
622 | /****************************************************************************/
|
cc1.real: all warnings being treated as errors
While at it, add a non-empty default case just to avoid any misra
warnings.
Signed-off-by: Izhar Ameer Shaikh <izhar.ameer.shaikh@amd.com>
Acked-by: Trung Tran<trung.tran@amd.com>
Updated Changelog for components axicdma, axidma, can, canfd, xilffs, xilmailbox and more Signed-off-by: Bhawana Sahu <bhawana.sahu@amd.com> Acked-by : Siva Addepalli<saddepal@amd.com>
In the previous code, block length is updated based on the hash length provided. Invalid block length is being updated when SHAKE operation with hash length greater than 32 bytes is provided. Now, updating the block length based on the ShaMode. Signed-off-by: Palakurthy Yogitha <palakurthy.yogitha@amd.com> Acked-by: Sai Srinivas Sirimisetty <SaiSrinivas.Sirimisetti@amd.com>
Added temporal redundancy for AES countermeasure configuration to protect against single glitch attacks. Signed-off-by: Ankush Mehtre <ankush.mehtre@amd.com> Acked-for-series: Sai Srinivas Sirimisetty <SaiSrinivas.Sirimisetti@amd.com=
Updated the comment with the correct timeout value. Signed-off-by: Ankush Mehtre <ankush.mehtre@amd.com> Acked-for-series: Sai Srinivas Sirimisetty <SaiSrinivas.Sirimisetti@amd.com=
Minimum KeyLen check condition in XAsu_ValidateKdfParamete is removed as this restriction is removed in HMAC. Signed-off-by: Koushik Parlapalli <koushik.parlapalli@amd.com> Acked-for-series: Sai Srinivas Sirimisetty <SaiSrinivas.Sirimisetti@amd.com=
In the interest of code space and security, calcultaing iterations using integer math Signed-off-by: Koushik Parlapalli <koushik.parlapalli@amd.com> Acked-for-series: Sai Srinivas Sirimisetty <SaiSrinivas.Sirimisetti@amd.com=
… checking for auto_proc mode This now uses 5ms time-out to avod potentially getting stuck Signed-off-by: Koushik Parlapalli <koushik.parlapalli@amd.com> Acked-for-series: Sai Srinivas Sirimisetty <SaiSrinivas.Sirimisetti@amd.com=
…emoved set KAT status as passed in RTCA area Initialised SaltAddr and SaltLen parameters to 0 in XAsufw_EciesOperationKat() function and removed setting KAT status as passed in RTCA area Signed-off-by: Koushik Parlapalli <koushik.parlapalli@amd.com> Acked-for-series: Sai Srinivas Sirimisetty <SaiSrinivas.Sirimisetti@amd.com=
Defined macros for offsets used in XAsufw_ChangeEndianness() Signed-off-by: Koushik Parlapalli <koushik.parlapalli@amd.com> Acked-for-series: Sai Srinivas Sirimisetty <SaiSrinivas.Sirimisetti@amd.com=
For Versal_2ve_2vm, when we send error injection linux sysfs interface. It is injecting error in different locations than the given given locations. So, CE/UE/CRC errors are not coming correctly. The command processing has issue for other commands also where we send some arguments in the payload buffer Signed-off-by: GayathriM <gayathri.m@amd.com>
… generation API. Moved random number generation inside the sign generation APIs in both xecc.c and xrsa_ecc.c files. Signed-off-by: Palakurthy Yogitha <palakurthy.yogitha@amd.com> Acked-by: Sai Srinivas Sirimisetty <SaiSrinivas.Sirimisetti@amd.com> Acked-by: Mounika Akula <mounika.akula@amd.com>
Update driver version to 1.22 Signed-off-by: Srikanth Boyapally <srikanth.boyapally@amd.com> Acked-for-series: Srinivas Goud <srinivas.goud@amd.com>
When cache coherency is enabled, cache maintenance operations should still be performed unless the application is running in EL1 non-secure mode. In EL3 mode, cache operations are always required because AXI WPRTCN/RPRTCN is configured for non-secure transactions to support EL1_NS use cases. Therefore, explicit cache maintenance is necessary in EL3 regardless of the cache coherency setting. Signed-off-by: Srikanth Boyapally <srikanth.boyapally@amd.com> Acked-for-series: Srinivas Goud <srinivas.goud@amd.com>
When cache coherency is enabled, cache maintenance operations should still be performed unless the application is running in EL1 non-secure mode. In EL3 mode, cache operations are always required because AXI WPRTCN/RPRTCN is configured for non-secure transactions to support EL1_NS use cases. Therefore, explicit cache maintenance is necessary in EL3 regardless of the cache coherency setting. Signed-off-by: Srikanth Boyapally <srikanth.boyapally@amd.com> Acked-for-series: Srinivas Goud <srinivas.goud@amd.com>
Ensure TRBs, endpoint buffers, and setup data are always flushed or invalidated when EL1_NONSECURE is not defined. Previously, cache maintenance relied solely on the IsCacheCoherent flag, which is insufficient in this context. Without proper flush/invalidate, USB DMA operations could consume stale data, causing erratic control, bulk, and link TRB transfers. These changes ensure reliable USB operation in all contexts when hardware coherency is guaranteed. Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com> Acked-by: Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
The input rate detection is supported only in clkx5. In the xsct flow there is no way to differenciate the clkx5. For SDT we are using the compatible to differenciate. So this feature are not supported in xsct flow. Compile XClk_Wiz_GetInputRate conditionally. While at it also change the Assert to nonvoid. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Acked-by: Srinivas Goud <srinivas.goud@amd.com>
updated changelog for dcsub, mmdip and libmetal_xlnx_extension Signed-off-by: Bhawana Sahu <bhawana.sahu@amd.com> Acked-by : Siva Addepalli<saddepal@amd.com>
Updated the VEK385 example design to support Rev B board Signed-off-by: S Shreesh <s.shreesh@amd.com> Acked-for-series: Kapil Usgaonkar <kapil.usgaonkar@amd.com>
Updated the VEK385 example design to support Rev B board Signed-off-by: S Shreesh <s.shreesh@amd.com> Acked-for-series: Kapil Usgaonkar <kapil.usgaonkar@amd.com>
Updated the PLL selected for RX to VPHY_RX_PLL_TYPE in VPhy init Signed-off-by: S Shreesh <s.shreesh@amd.com> Acked-by: Kapil Usgaonkar <kapil.usgaonkar@amd.com>
Add conditional cache ops for EL1_NS and EL3 modes for ZDMA Signed-off-by: Golla Nagendra <nagendra.golla@amd.com> Acked-for-series: Harini Katakam <harini.katakam@amd.com>
Add conditional cache ops for EL1_NS and EL3 modes for MCDMA and update the driver version Signed-off-by: Golla Nagendra <nagendra.golla@amd.com> Acked-for-series: Harini Katakam <harini.katakam@amd.com>
Add the missing examples of SDP, MST and 4K HBR3 in Vitis GUI when importing examples for dcsub. Signed-off-by: Vishal Sagar <vishal.sagar@amd.com> Acked-by: Varunkumar Allagadapa <varunkumar.allagadapa@amd.com>
… EL1_NS/EL3 Implement if-else logic where cache flush and invalidate operations always take place if current execution level is EL3 or the processor is from ARM Cortex-R5, MicroBlaze and RISC-V. If current execution level is EL1_NS, then based on whether cache coherency is enabled or not, cache flush and invalidate operations should be executed. Update version register read (CSU_VERSION) logic to support all execution levels for ZynqMP. Signed-off-by: Tarun Maddipatla <Tarun.MaddipatlaVenkataSaiKrishna@amd.com> Acked-by: Harini Katakam <harini.katakam@amd.com>
Fixed PDISrc value for proper UFS Fallback Boot Support Signed-off-by: Sreedhar Kundella <sreedhar.kundella@amd.com> Acked-by: Gajulapally, Nandanikhil <Nandanikhil.Gajulapally@amd.com>
…ze processor Added support for building xilnvm, xilsecure, xilpuf and xilocp examples for PL microblaze in SDT flow. Signed-off-by: Rishitha Pudutha <rishitha.pudutha@amd.com> Acked-by: Harsha <harsha.harsha@amd.com>
Updated Changelog for components dfeparch, zynqmp_fsbl Signed-off-by: Bhawana Sahu <bhawana.sahu@amd.com>
When EL1_NONSECURE is not defined, data cache is always flushed or invalidated. Previously, cache maintenance depended solely on the IsCacheCoherent flag, which is no longer sufficient. Signed-off-by: Akhil Thumma <Akhil.Thumma@amd.com> Acked-by: Harini Katakam <harini.katakam@amd.com> Acked-by: Venkatesh Odela <venkatesh.odela@amd.com>
…address Replaced the XSecure_IsNonZeroBuffer function with an inline non-zero buffer check within the RSA operation, this avoids redundant calls. XSecure_InByte64() is used to safely read data from the 64-bit DMA address of the modulus exponent buffer. Signed-off-by: Mounika Botcha <mounika.botcha@amd.com> Acked-by: Durga Challa <durga.challa@amd.com>
The register can take u32 value. So modify the function prototype to accept u32 data type limit instead of u16. This helps the aux part track correct duration of time. Signed-off-by: Vishal Sagar <vishal.sagar@amd.com> Acked-for-series: Varunkumar Allagadapa <varunkumar.allagadapa@amd.com>
Configure the MMI DC and DP Tx for quad pixel per clock DC Bypass example correctly. This includes - 1 - configuring the AVPATGEN, MMI DC and DP Tx in quad pixel per clock, 2 - fix the clock wizard configuration to accurately generate 25.175 MHz / 2 3 - fix the DC vid clock src to PL video clock 4 - fix the other parameters like hblank interval, avg bytes per TU, etc. 5 - Add app version information and set app version to 1.0 With this the example runs at HBR 2.7 Gbps 1 Lanes to display quad pixel per clock 640x480-60 fps. Signed-off-by: Vishal Sagar <vishal.sagar@amd.com> Acked-for-series: Varunkumar Allagadapa <varunkumar.allagadapa@amd.com>
Updated Changelog for components sdps, mcdma, nandpsu, qspispu Signed-off-by: Bhawana Sahu <bhawana.sahu@amd.com>
During PUF regeneration on demand, the generated black key and PUF ID did not match those from PUF registration. This issue occurred due to unnecessary endian swapping of PUF_TrimHD, Chash, and Aux values, and an additional shift applied to the already shifted AUX data during regeneration. Removed redundant endian conversion and corrected AUX assignment to ensure consistent PUF outputs across registration and regeneration. Signed-off-by: Mounika Botcha <mounika.botcha@amd.com> Acked-by: Harsha <harsha.harsha@amd.com>
The TRNG wrapper functions were incorrectly interpreting states other than INITIALIZED as UNINITIALIZED. TRNG has multiple valid intermediate states, and the wrapper should only detect the explicit UNINITIALIZED state. This patch updates the state checks to correctly identify the UNINITIALIZED state without misclassifying other valid states. Signed-off-by: Dasari Sharath Kumar <sharath.kumar.dasari@amd.com> Acked-by: Sreedhar Kundella <sreedhar.kundella@amd.com>
Update embeddedsw license Signed-off-by: Manikanta Sreeram <manikanta.sreeram@amd.com>
This reverts commit f8e8b0d159103a6014204e26a399bf04d60fd49f. Standart library memcpy() API used in Xil_SMemCpy() failed to copy data. Acked-by: Mohan Marutirao Dhanawade <mohan.dhanawade@amd.com>
Signed-off-by: Bhawana Sahu <bhawana.sahu@amd.com>
A lot of people are trying to send pull requests via github but this is not the right channel to use. Linux project is doing review over emails that's why use git@xilinx.com if you want to contribute changes to this repository. Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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@FloofyJin Thanks for reporting it. We will check and fix if this turns to be a real issue. |
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XTmrCtr_CfgInitialize() does not initialize IsStartedTmrCtr0, IsStartedTmrCtr1, or IsPwmEnabled.
When XTmrCtr instances are allocated on the stack, these members may contain indeterminate values.
This can cause XTmrCtr_PwmEnable() to return without enabling PWM because IsPwmEnabled is non-zero.
Reproduction:
The issue disappears if the application performs memset(&Timer, 0, sizeof(Timer)) prior to initialization. This patch initializes the driver state variables inside XTmrCtr_CfgInitialize() which will essentially do the same thing.