eyeriss: regenerate FakeRAM macros with current bsg_fakeram (fixes #234)

[mguthaus]

Fixes #234.

Root cause

eyeriss was the only design whose FakeRAM cfgs lived at
designs/<platform>/eyeriss/sram/fakeram_<platform>.cfg instead of the standard
designs/src/<design>/dev/generated/ path that tools/regenerate_sram.sh reads.

The mass regeneration in 94296798 — the bump to bsg_fakeram c83ecb4 that fixed the
wd_in LEF pin-direction bug — therefore skipped eyeriss silently. Its committed LEFs kept
declaring the upper half of every rw*/w*_wd_in bus as DIRECTION OUTPUT while Liberty
correctly said input, which is what @bugraonal hit as floating bits in gate-level sim.

I audited every design: eyeriss was the only one with an off-path cfg, and the only one with
bad LEFs.

Changes

• Cfgs moved to designs/src/eyeriss/dev/generated/, so future sweeps pick eyeriss up.
• LEF/LIB regenerated on all three platforms with the pinned bsg_fakeram c83ecb4.
• tools/check_sram_lef.sh + a grep-only PR workflow: a wd_in pin is an input by
  definition, so DIRECTION OUTPUT on one is always this bug. Verified it fails on the old
  files and passes on the regenerated set.

Beyond the direction fix the macros were stale on a second axis — they predate the asap7 area
calibration and the sky130hd analytical path:

platform	Δ macro area	cause
nangate45	0.0 %, byte-identical	CACTI path unchanged; direction fix only
asap7	+80 % … +389 %	2.5× periphery overhead + dynamic column mux calibration
sky130hd	−16 % … −55 %	analytical bitcell (OpenRAM) replaces scaled CACTI

Re-validation

Built on this branch's toolchain, which is identical to master (bazel-orfs 6c1bbca /
OpenROAD b65c274c; MODULE.bazel is byte-identical to origin/main).
All three platforms reach 6_final with 0 DRC and 0 setup violations.

Baseline column is fde02b5d from results.html, which was generated back at 553c1c3 and
never refreshed for eyeriss after the ab36853f upgrade — so it carries toolchain drift as
well as the macro change. nangate45 is the clean control, since its geometry did not move.

	asap7	nangate45	sky130hd
die area µm²	226 900 → 421 713 (+86 %)	8 406 380 → 8 407 450 (+0.0 %)	53 040 900 → 37 526 200 (−29 %)
util %	30.8 → 30.7	38.5 → 38.5	31.9 → 32.3
logic cells	301 728 → 307 541 (+1.9 %)	307 758 → 307 635 (−0.0 %)	222 577 → 224 313 (+0.8 %)
setup WNS	+138.4 → +141.3 ps	+102.8 → +247.5 ps	+1348.4 → +147.2 ps
DRC	0	0	0

• nangate45 reproduces the baseline to within 0.05 % on every area/cell figure, confirming
  the CACTI geometry is untouched. Its +145 ps setup gain is therefore pure toolchain drift.
• asap7 trades die area for correctness as expected: calibrated macros are 2–4× larger, so
  at an unchanged util target the die nearly doubles. Timing, util and cell count are flat.
  The CORE_UTILIZATION 40→30 MPL-0040 workaround is still needed.
• sky130hd shrinks 29 %, but setup margin falls to +147 ps against an unchanged 25 ns
  clock (period_min 24.85 ns → set/period_min ≈ 1.006 vs the 1.10 guardband). The control
  shows drift went the other way, so this is the new macro aspect ratios giving RTLMP a
  different floorplan. It closes cleanly; relaxing the clock toward 27.5 ns would restore the
  guardband at the cost of reported Fmax — left at 25 ns, as that's a PPA call.
• Hold: asap7 clean (+23.1 ps); nangate45 −16.3 ps (3 violations), sky130hd −374.2 ps
  (52 violations). These run with SKIP_INCREMENTAL_REPAIR + SKIP_LAST_GASP, and the
  baseline never recorded hold, so they are not attributed — settling it needs an A/B
  against a pre-change build on this same toolchain pin.

Full write-up in designs/src/eyeriss/DECISIONS.md.