Implement basic CSR infrastructure and Zicsr instruction support

[Dazhou-20383]

Add initial Zicsr CSR support

Added:

• A dedicated CSR register file
• Support for csrrw, csrrs, and csrrc
• CSR read-data propagation through the normal pipeline to writeback
• Build-time gating via UTOSS_RISCV__ZICSR_ENABLED

Design notes:

• CSRs are implemented separately from the GPR register file.
• CSR instructions are decoded in the decode stage, where the CSR address and source operands are already available.
• CSR read data flows through the existing pipeline datapath and is selected during writeback.
• funct3 is used to distinguish CSR instruction variants.

Future work:

• Immediate CSR forms (csrrwi, csrrsi, csrrci)
• Trap and privilege-level handling
• CSR-specific semantics and access restrictions
• Dedicated CSR tests

[TheDeepestSpace]

thanks for making sure to gate everything on this flag; can you add it to our build-config here:

risc-v/Makefile

Lines 18 to 25 in 2a95e8f

	# =============
	# Build config
	# =============
	UTOSS_RISCV_CONFIG ?= RV32I
	UTOSS_RISCV_VERILATOR_DEFINES := $(if $(findstring B,$(UTOSS_RISCV_CONFIG)),-DUTOSS_RISCV_ENABLE_B_EXT)
	UTOSS_RISCV_RISCOF_VERILATOR_DEFINES := -DUTOSS_PIPELINE_LOGGER

[DanielTaoHuang123]

directly determine csr_write_enable in decode could potentially cause hazards (update CSRfile too early). Maybe do something like csr_write_enable_D and pass it to the next stage?

[DanielTaoHuang123]

probably need separate read_addr and write_addr, since CSRfile reading and writing can be done in different addr if they are in different stages at the same time

[DanielTaoHuang123]

probably need to change csr_write_enable in decode and separate addr in CSRfile. read the comments for details