ppl: avoid boundary PDN shapes when placing pins

[eder-matheus]

Summary

place_pins and place_pin ignored boundary power grid geometry, so signal IO
pins were placed on top of or abutting -extend_to_boundary straps and the
power/ground BPins pdngen creates there, causing shorts and spacing violations
found only at detailed route. Special net wires were never inspected on the die
edges, and fixed pins were only checked by a point test against the slot center
with no spacing margin.

Blocking shapes are now padded by the pin footprint plus the required spacing
(including the width dependent PARALLELRUNLENGTH rules for wide straps) and
shapes within pin reach of an edge are included, since pin shapes extend into
the die. Also fixed here: mirrored pins could still land on blocked slots,
excluded intervals were never applied to polygon die slots, place_pin -force_to_die_boundary was unaware of this geometry, and its offset search was
unbounded, which could push a pin outside the die area when an entire edge is
blocked (now reported as PPL-122).

First of three stacked PRs; the follow ups add routing obstructions, via landing
pads and top layer support, then the MINSPACING/EFFECTIVEWIDTH attributes.

Type of Change

• Bug fix

Impact

Slots too close to boundary PDN geometry become unavailable, so IO pin positions
change in designs with boundary PDN. The ram tests show the expected effect:
available slots 270 -> 262 and I/O HPWL 310.66 -> 311.15 um (+0.16%), which
shifts two instances and the routing in their golden files. Designs without
boundary PDN geometry are unaffected. A pin that cannot fit on its edge now
fails with PPL-82 or PPL-122 instead of overlapping the power grid or leaving
the die.

Verification

• I have verified that the local build succeeds (./etc/Build.sh).
• I have run the relevant tests and they pass.
• My code follows the repository's formatting guidelines.
• I have included tests to prevent regressions.
• I have signed my commits (DCO).

162/162 ppl tests pass, including 10 new ones, plus the ram tests that consume
place_pins.

Related Issues

N/A

[gemini-code-assist]

Code Review

This pull request updates the IOPlacer to prevent placing pins on slots blocked by boundary Power Delivery Network (PDN) shapes, modifying Hungarian matching to avoid blocked mirrored slots, and adding several integration tests. The review feedback highlights potential application crashes due to std::out_of_range exceptions when using .at() on layer maps, as well as potential null pointer dereferences and division-by-zero errors. It is recommended to implement safe helper functions to retrieve minimum widths and areas with proper fallbacks and bounds checking.

[eder-matheus]

@maliberty this PR partially solves a bug on our private PDKs. I'll have two other PRs to complete the fix, but this one is ready for review.