fix: avoid vector loads during restore#12
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Pull request overview
This PR updates the RVV restore path to avoid vector memory loads from the flash/MMIO-backed checkpoint region (which XiangShan can’t handle), by switching to scalar loads plus vector register construction using vector ALU instructions.
Changes:
- Add an initial
vsetvlito establish a temporarySEW=64, LMUL=1, VL=2configuration for restore-time vector ops. - Replace
vl1re64.vwhole-register loads withld+vmv.v.x/vslide1down.vxto populate vector registers without vector memory accesses. - Refactor the vector restore sequence using a new
RESTORE_VECTOR_REGmacro.
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XiangShan does not support vector loads from the flash/MMIO region used by GCPT restore. Restoring vector registers with vl1re64.v from that region can fail during checkpoint restore. Load each saved vector register with scalar loads first, then move the data into the vector register with vector move/slide instructions. This keeps the restore path compatible with both flash and DRAM backed checkpoints.
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XiangShan does not support vector loads from the flash/MMIO region used by GCPT restore. Restoring vector registers with vl1re64.v from that region can fail during checkpoint restore.
Load each saved vector register with scalar loads first, then move the data into the vector register with vector move/slide instructions. This keeps the restore path compatible with both flash and DRAM backed checkpoints.