FPGA-NCO-DDS

FPGA-based Numerically Controlled Oscillator (DDS) using Verilog HDL and Xilinx Vivado.

This project implements a configurable Numerically Controlled Oscillator (DDS) featuring precise frequency and amplitude control using fixed-point arithmetic and RTL design principles.

---

Table of Contents

• Features
• Tools Used
• Project Structure
• Usage
• Waveform Output
• Applications

---

Features

• 32-bit phase accumulator
• 256-point sine lookup table
• Runtime frequency control using phase increment
• Amplitude control using fixed-point multiplier
• Behavioral simulation using Vivado

---

Tools Used

• Verilog HDL
• Xilinx Vivado
• Fixed-point arithmetic

---

Project Structure

• rtl/ 📝 – Verilog RTL design files
  • nco.v
  • sine_lut.v
• sim/ 🧪 – Testbench files
  • nco_tb.v
• mem/ 💾 – Sine LUT memory file
  • sine256.hex

---

Usage

Simulation Steps (Vivado)

1. Open Xilinx Vivado
2. Create a new RTL Project
3. Add RTL files from the rtl/ directory
4. Add the testbench file from the sim/ directory
5. Add the LUT memory file from the mem/ directory
6. Run Behavioral Simulation
7. View sine waveform, frequency tuning, and amplitude scaling in the waveform window

---

Waveform Output

Below is an example waveform generated from the NCO during simulation:

---

Applications

• Signal generation
• Software Defined Radio (SDR)
• Communication systems