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Add transaction-safe BrickKV cache runtime - #3

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samkwak188 wants to merge 19 commits into
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feature/brickkv-managed-cache
Open

Add transaction-safe BrickKV cache runtime#3
samkwak188 wants to merge 19 commits into
mainfrom
feature/brickkv-managed-cache

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@samkwak188

@samkwak188 samkwak188 commented Aug 31, 2026

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Summary

  • adds opt-in, transaction-safe KV-cache lineage through Brick, the GenieX shim, Agent Lab diagnostics, and a C++20 replay tool
  • reconciles managed caching with Qualcomm GenieX's current automatic append-only continuation behavior
  • uses protocol version 2: only EOS-complete generations may remain reusable; truncation, cancellation, disconnect, timeout, failure, branch, session switch, or parent mismatch reset safely
  • keeps cache mode off by default and confines raw legacy cache retention to synthetic test tooling
  • adds deterministic Snapdragon and CHTC study runners with strict correctness, provenance, and publication gates

Verified state

Brick head: 198acc6d0daf5538827fb5549f39340ab2096d16

  • local Windows ARM64 regression: 1,423 passed, 14 documented skips, 0 failed
  • Brick CI: run 33673962790, green across ASan/UBSan, Windows x64, and Python 3.9, 3.10, 3.11, 3.12, and 3.13
  • native C++ lineage gate: 1,000 randomized branch mutations plus 1, 2, 4, and 8-session canary campaigns
  • QAIRT plugin: clean Windows ARM64 build of 517/517 targets and 223/223 CTests at b3b85ab16c5106a7048ca2f24a3c9e4a8089cba7
  • GenieX: run 33668959554, all 26 jobs passed at code commit 6af9fee645de67dda649e487785d633b97b98ab4
  • exact-range security review of 2929a657..6af9fee6: all 18 changed source files inventoried, two independent reviews, zero reportable findings

Snapdragon correctness result

The corrected protocol ran through the real Windows ARM64 QAIRT production path with the installed Qwen 3 0.6B development bundle.

  • 30 completed tasks compared; 1 intentional disconnect excluded
  • 18 managed cache hits; all 18 reduced prompt-token work
  • reset mode: 19/30 exact-task passes
  • managed mode: 30/30 exact-task passes
  • 0 managed regressions
  • 11 oracle-proven improvements
  • 0 uncontrolled differences when both modes had the same task outcome

This passes the development NPU task non-regression gate. The evidence paths and SHA-256 values are recorded in docs/BRICKKV_NPU_READINESS.md.

Upstream dependencies

Before GenieX PR 1414 merges, its .gitmodules entry must be changed back from the temporary fork URL to Qualcomm's QAIRT plugin URL after PR 50 is available upstream.

Claim boundary

  • the measured Qwen 3 0.6B run is a correctness and protocol smoke test, not the final model study
  • no Llama 3.1 8B Snapdragon timing matrix has run because the licensed QAIRT model artifact and Qualcomm credentials are not present on this machine
  • no L40S or A100 CHTC matrix has run because this environment has no CHTC SSH identity or condor_submit access
  • therefore this PR makes no latency improvement claim and no final benchmark claim
  • model inference remains local, and no production Brix data or connector code is part of this work

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