[Buffering] Adapt CFDFC extraction for FTD circuits

[AyaElAkhras]

Summary

This PR adapts CFDFC extraction for FTD circuits.

The existing extraction strategy models a CFG cycle using only channels that
correspond directly to edges in that cycle. This underrepresents FTD circuits,
which may contain valid channels between basic blocks without a corresponding
CFG edge.

The updated extraction:

• includes channels whose source and destination blocks both belong to the
  selected CFG cycle;
• identifies backward channels in cyclic regions of the dataflow circuit;
• includes a backward channel only when it corresponds to an edge of the CFG
  cycle currently being modeled;

This more accurately represent FTD circuits while preserving the current main buffer
placement implementation.

Notes

This remains a CFG-cycle-based heuristic. A future circuit-level model should represent FTD circuits without relying on basic block membership or CFG structure.