From bd26e070d05a2851e2a244d98b9ca3a74ae186a6 Mon Sep 17 00:00:00 2001
From: petergrossmann21 <peter@zeroasic.com>
Date: Wed, 5 Aug 2026 13:36:00 -0400
Subject: [PATCH 1/4] Add adder techmap pass

---
 src/synth_fpga.cc | 77 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 77 insertions(+)

diff --git a/src/synth_fpga.cc b/src/synth_fpga.cc
index c05bf86..7fbb3a2 100644
--- a/src/synth_fpga.cc
+++ b/src/synth_fpga.cc
@@ -98,6 +98,10 @@ struct SynthFpgaPass : public ScriptPass {
   dict<string, string> ys_dsps_parameter_string;
   string ys_dsps_pack_command = "";
 
+  // Adders (carry chain)
+  //
+  string ys_adders_techmap = "";
+
   // Methods
   //
   SynthFpgaPass() : ScriptPass("synth_fpga", "Zero Asic FPGA synthesis flow") {}
@@ -415,6 +419,11 @@ struct SynthFpgaPass : public ScriptPass {
     dict<string, string> dsps_parameter_string;
     string dsps_pack_command;
 
+    //
+    // Adder (carry chain) related
+    //
+    string adders_techmap;
+
   } config_type;
 
   // The global config object
@@ -498,6 +507,9 @@ struct SynthFpgaPass : public ScriptPass {
     log("  DSP pack_command   : \n");
     log("                       %s\n", (G_config.dsps_pack_command).c_str());
 
+    log("  ADDER techmap      : \n");
+    log("                       %s\n", (G_config.adders_techmap).c_str());
+
     log(" ====================================================================="
         "=====\n");
   }
@@ -595,6 +607,18 @@ struct SynthFpgaPass : public ScriptPass {
         ys_dsps_pack_command = G_config.dsps_pack_command;
       }
 
+      // Adder (carry chain) techmap setting.  Resolved relative to root_path
+      // just like the DSP/BRAM/DFF techmaps.
+      //
+      if (G_config.adders_techmap == "") {
+
+        ys_adders_techmap = "";
+
+      } else {
+
+        ys_adders_techmap = G_config.root_path + "/" + G_config.adders_techmap;
+      }
+
       // We call the 'dsp_tech' through the config file mechanism as 'config'
       // (why not ? ;-)
       //
@@ -1253,6 +1277,30 @@ struct SynthFpgaPass : public ScriptPass {
       G_config.dsps_pack_command = dsps_pack_command->data_string;
     }
 
+    // adders (optional carry-chain hard adder techmap)
+    //
+    JsonNode *adders = NULL;
+    if (root.data_dict.count("adders") != 0) {
+      adders = root.data_dict.at("adders");
+      if (adders->type != 'D') {
+        log_error("'adders' must be a dictionnary.\n");
+      }
+    }
+
+    // Adder techmap file (optional : absence leaves adders in soft logic).
+    //
+    if (!adders || (adders->data_dict.count("techmap") == 0)) {
+      G_config.adders_techmap = "";
+
+    } else {
+
+      JsonNode *adders_techmap = adders->data_dict.at("techmap");
+      if (adders_techmap->type != 'S') {
+        log_error("'techmap' associated to 'adders' must be a string.\n");
+      }
+      G_config.adders_techmap = adders_techmap->data_string;
+    }
+
     log_header(yosys_get_design(),
                "Reading config file '%s' done with success !\n",
                config_file.c_str());
@@ -2865,6 +2913,29 @@ struct SynthFpgaPass : public ScriptPass {
     }
   }
 
+  // -------------------------
+  // infer_adders
+  // -------------------------
+  //
+  // Map arithmetic ($alu, produced by 'alumacc') onto the target hard
+  // carry-chain 'adder' primitive using the config-provided techmap file.
+  // Deliberately independent of DSP inference (not gated by 'no_dsp'), and must
+  // be called AFTER 'alumacc' (which creates the $alu cells) and BEFORE the
+  // generic 'techmap -map +/techmap.v' (which would otherwise lower $alu to
+  // soft gates).  A no-op when no adder techmap is configured.
+  //
+  void infer_adders() {
+    if (ys_adders_techmap == "") {
+      return;
+    }
+
+    run("stat");
+
+    run("techmap -map " + ys_adders_techmap);
+
+    run("stat");
+  }
+
   // -------------------------
   // resynthesize
   // -------------------------
@@ -3538,6 +3609,12 @@ struct SynthFpgaPass : public ScriptPass {
     //
     run("pmux2shiftx");
 
+    // Map $alu onto the target hard carry-chain 'adder' primitive (if a config
+    // adder techmap is provided) before the generic techmap lowers it to soft
+    // gates.  No-op otherwise.
+    //
+    infer_adders();
+
     run("techmap -map +/techmap.v");
 
     // BRAM inference

From 01766a99cb69fea1f4c1cddf37d63126fa95ca11 Mon Sep 17 00:00:00 2001
From: petergrossmann21 <peter@zeroasic.com>
Date: Wed, 5 Aug 2026 13:36:11 -0400
Subject: [PATCH 2/4] Update docs to describe adder techmapping

---
 README.md | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 2cfd16d..8cee917 100644
--- a/README.md
+++ b/README.md
@@ -221,11 +221,14 @@ The configuration format is still work in progress. A draft format specification
                         "<str, name of define>": <str or int, value of define>
                 }
                 "pack_command": "DSP packing command" (optional)
+        },
+        "adders": { (optional)
+                "techmap": <path, relative path to yosys hard carry-chain adder tech mapping file>
         }
 }
 ```
 
-Sections version, partname, lut_size, flip-flops, are required. Sections root_path, brams,and dsps are optional. If "root_path" is not specified, it will correspond to the path where the config file is located.
+Sections version, partname, lut_size, flip-flops, are required. Sections root_path, brams, dsps, and adders are optional. If "root_path" is not specified, it will correspond to the path where the config file is located. The "adders" techmap (applied after `alumacc` and before the generic techmap, independently of DSP inference) maps `$alu` onto a hard carry-chain adder primitive; when absent, adders remain in soft logic.
 
 ### Logic Only Example: No BRAMs or DSPs
 

From 3200a30a338b2d8ade4b00ea9c0a2e05ec2d9ea4 Mon Sep 17 00:00:00 2001
From: Thierry Besson <thierry@zeroasic.com>
Date: Tue, 11 Aug 2026 15:19:20 -0400
Subject: [PATCH 3/4] Update build.yml

---
 .github/workflows/build.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index dd066bd..3f85cf8 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -46,7 +46,7 @@ jobs:
           sudo apt-get install -y git build-essential pkg-config cmake ccache gperf bison flex \
             libreadline-dev gawk tcl-dev libffi-dev graphviz xdot python3 \
             libboost-system-dev libboost-python-dev libboost-filesystem-dev \
-            zlib1g-dev libfl-dev
+            zlib1g-dev libfl-dev libsodium-dev nlohmann-json3-dev
 
       - uses: actions/checkout@v4
         with:

From 5c634ac468f59499616f02626f8192e9be83bc1a Mon Sep 17 00:00:00 2001
From: petergrossmann21 <peter@zeroasic.com>
Date: Fri, 21 Aug 2026 10:39:29 -0400
Subject: [PATCH 4/4] Add unit tests

---
 .gitignore                                    |  1 +
 tests/CMakeLists.txt                          | 17 +++++
 .../carrychain-no_techmap-soft_logic.ys       | 29 ++++++++
 .../unit/carrychain/carrychain-show_config.ys | 29 ++++++++
 .../carrychain/carrychain-techmap-abspath.ys  | 31 +++++++++
 .../carrychain-techmap-accumulator.ys         | 40 +++++++++++
 .../carrychain-techmap-add_carry_in.ys        | 34 +++++++++
 .../carrychain-techmap-add_signed.ys          | 30 ++++++++
 .../carrychain-techmap-add_unsigned.ys        | 36 ++++++++++
 .../carrychain/carrychain-techmap-compare.ys  | 28 ++++++++
 .../carrychain-techmap-increment.ys           | 29 ++++++++
 .../carrychain-techmap-min8_narrow.ys         | 26 +++++++
 .../carrychain-techmap-min8_wide.ys           | 30 ++++++++
 .../unit/carrychain/carrychain-techmap-sub.ys | 29 ++++++++
 .../carrychain-techmap-two_adders.ys          | 37 ++++++++++
 ...carrychain-techmap-undeclared_primitive.ys | 31 +++++++++
 .../carrychain/carrychain-techmap-wide_add.ys | 30 ++++++++
 .../carrychain/carrychain-techmap-with_dsp.ys | 33 +++++++++
 .../carrychain-techmap-with_no_dsp.ys         | 35 ++++++++++
 tests/unit/data/carrychain/carrychain.json    | 23 +++++++
 .../data/carrychain/carrychain_abspath.json   | 23 +++++++
 .../unit/data/carrychain/carrychain_dsp.json  | 44 ++++++++++++
 .../unit/data/carrychain/carrychain_min8.json | 23 +++++++
 .../data/carrychain/carrychain_no_adders.json | 20 ++++++
 .../unit/data/carrychain/models/tech_carry.v  | 21 ++++++
 tests/unit/data/carrychain/tech_adder.v       | 65 +++++++++++++++++
 tests/unit/data/carrychain/tech_adder_min8.v  | 69 +++++++++++++++++++
 27 files changed, 843 insertions(+)
 create mode 100644 tests/unit/carrychain/carrychain-no_techmap-soft_logic.ys
 create mode 100644 tests/unit/carrychain/carrychain-show_config.ys
 create mode 100644 tests/unit/carrychain/carrychain-techmap-abspath.ys
 create mode 100644 tests/unit/carrychain/carrychain-techmap-accumulator.ys
 create mode 100644 tests/unit/carrychain/carrychain-techmap-add_carry_in.ys
 create mode 100644 tests/unit/carrychain/carrychain-techmap-add_signed.ys
 create mode 100644 tests/unit/carrychain/carrychain-techmap-add_unsigned.ys
 create mode 100644 tests/unit/carrychain/carrychain-techmap-compare.ys
 create mode 100644 tests/unit/carrychain/carrychain-techmap-increment.ys
 create mode 100644 tests/unit/carrychain/carrychain-techmap-min8_narrow.ys
 create mode 100644 tests/unit/carrychain/carrychain-techmap-min8_wide.ys
 create mode 100644 tests/unit/carrychain/carrychain-techmap-sub.ys
 create mode 100644 tests/unit/carrychain/carrychain-techmap-two_adders.ys
 create mode 100644 tests/unit/carrychain/carrychain-techmap-undeclared_primitive.ys
 create mode 100644 tests/unit/carrychain/carrychain-techmap-wide_add.ys
 create mode 100644 tests/unit/carrychain/carrychain-techmap-with_dsp.ys
 create mode 100644 tests/unit/carrychain/carrychain-techmap-with_no_dsp.ys
 create mode 100644 tests/unit/data/carrychain/carrychain.json
 create mode 100644 tests/unit/data/carrychain/carrychain_abspath.json
 create mode 100644 tests/unit/data/carrychain/carrychain_dsp.json
 create mode 100644 tests/unit/data/carrychain/carrychain_min8.json
 create mode 100644 tests/unit/data/carrychain/carrychain_no_adders.json
 create mode 100644 tests/unit/data/carrychain/models/tech_carry.v
 create mode 100644 tests/unit/data/carrychain/tech_adder.v
 create mode 100644 tests/unit/data/carrychain/tech_adder_min8.v

diff --git a/.gitignore b/.gitignore
index 5fbcefb..760071a 100644
--- a/.gitignore
+++ b/.gitignore
@@ -2,3 +2,4 @@
 .o
 build/
 netlist_synth_fpga.verilog
+tiny_area_lut4.blif
diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt
index 6488c8a..09b0a6d 100644
--- a/tests/CMakeLists.txt
+++ b/tests/CMakeLists.txt
@@ -31,6 +31,23 @@ set(ALL_TESTS
     unit/dsp/mae-techmap-efpga_mult_addc_regi_unsigned.ys
     unit/dsp/mae-techmap-efpga_mult_addc_rego_unsigned.ys
     unit/dsp/mae-techmap-efpga_mult_addc_regio_unsigned.ys
+    unit/carrychain/carrychain-techmap-add_unsigned.ys
+    unit/carrychain/carrychain-techmap-add_signed.ys
+    unit/carrychain/carrychain-techmap-add_carry_in.ys
+    unit/carrychain/carrychain-techmap-sub.ys
+    unit/carrychain/carrychain-techmap-increment.ys
+    unit/carrychain/carrychain-techmap-compare.ys
+    unit/carrychain/carrychain-techmap-accumulator.ys
+    unit/carrychain/carrychain-techmap-wide_add.ys
+    unit/carrychain/carrychain-techmap-two_adders.ys
+    unit/carrychain/carrychain-techmap-undeclared_primitive.ys
+    unit/carrychain/carrychain-techmap-with_dsp.ys
+    unit/carrychain/carrychain-techmap-with_no_dsp.ys
+    unit/carrychain/carrychain-techmap-abspath.ys
+    unit/carrychain/carrychain-techmap-min8_wide.ys
+    unit/carrychain/carrychain-techmap-min8_narrow.ys
+    unit/carrychain/carrychain-no_techmap-soft_logic.ys
+    unit/carrychain/carrychain-show_config.ys
 )
 
 foreach(test_script ${ALL_TESTS})
diff --git a/tests/unit/carrychain/carrychain-no_techmap-soft_logic.ys b/tests/unit/carrychain/carrychain-no_techmap-soft_logic.ys
new file mode 100644
index 0000000..f532db9
--- /dev/null
+++ b/tests/unit/carrychain/carrychain-no_techmap-soft_logic.ys
@@ -0,0 +1,29 @@
+# yosys -m wildebeest -s carrychain-no_techmap-soft_logic.ys
+
+#Negative control : the very same adder, synthesized with a config that has
+#no 'adders' section, stays in soft logic.  That config differs from
+#'carrychain.json' by that section only.
+
+read_verilog -lib ../data/carrychain/models/tech_carry.v
+
+read_verilog <<EOF
+module carrychain_no_techmap
+  # (
+     parameter WIDTH = 8
+     )
+   (
+    input [(WIDTH-1):0] a,
+    input [(WIDTH-1):0] b,
+    output [WIDTH:0]    y
+    );
+
+   assign y = a + b;
+
+endmodule
+EOF
+
+synth_fpga -config ../data/carrychain/carrychain_no_adders.json
+
+select -assert-count 0 */t:efpga_carry
+select -assert-count 0 */t:$alu
+select -assert-min 1 */t:$lut
diff --git a/tests/unit/carrychain/carrychain-show_config.ys b/tests/unit/carrychain/carrychain-show_config.ys
new file mode 100644
index 0000000..0d33311
--- /dev/null
+++ b/tests/unit/carrychain/carrychain-show_config.ys
@@ -0,0 +1,29 @@
+# yosys -m wildebeest -s carrychain-show_config.ys
+
+#'-show_config' must report the configured adder techmap, and that same file
+#must then really be handed over to the 'techmap' pass.
+
+logger -expect log ".*ADDER techmap.*" 1
+logger -expect log ".*Verilog-2005 frontend: .*data/carrychain/tech_adder.v.*" 1
+
+read_verilog -lib ../data/carrychain/models/tech_carry.v
+
+read_verilog <<EOF
+module carrychain_show_config
+  # (
+     parameter WIDTH = 8
+     )
+   (
+    input [(WIDTH-1):0] a,
+    input [(WIDTH-1):0] b,
+    output [WIDTH:0]    y
+    );
+
+   assign y = a + b;
+
+endmodule
+EOF
+
+synth_fpga -config ../data/carrychain/carrychain.json -show_config
+
+select -assert-count 9 */t:efpga_carry
diff --git a/tests/unit/carrychain/carrychain-techmap-abspath.ys b/tests/unit/carrychain/carrychain-techmap-abspath.ys
new file mode 100644
index 0000000..ca2627f
--- /dev/null
+++ b/tests/unit/carrychain/carrychain-techmap-abspath.ys
@@ -0,0 +1,31 @@
+# yosys -m wildebeest -s carrychain-techmap-abspath.ys
+
+#The adder techmap path is resolved against 'root_path' like every other
+#techmap path : the leading '/' form must resolve the same way (same idea as
+#'heartbeat-z1010-config-abspath.ys').
+
+read_verilog -lib ../data/carrychain/models/tech_carry.v
+
+read_verilog <<EOF
+module carrychain_abspath
+  # (
+     parameter WIDTH = 8
+     )
+   (
+    input [(WIDTH-1):0] a,
+    input [(WIDTH-1):0] b,
+    output [WIDTH:0]    y
+    );
+
+   assign y = a + b;
+
+endmodule
+EOF
+
+synth_fpga -config ../data/carrychain/carrychain_abspath.json
+
+#The whole adder is in the carry chain : no '$alu' survived and no soft
+#logic was needed.
+select -assert-count 9 */t:efpga_carry
+select -assert-count 0 */t:$alu
+select -assert-count 0 */t:$lut
diff --git a/tests/unit/carrychain/carrychain-techmap-accumulator.ys b/tests/unit/carrychain/carrychain-techmap-accumulator.ys
new file mode 100644
index 0000000..fae0ccb
--- /dev/null
+++ b/tests/unit/carrychain/carrychain-techmap-accumulator.ys
@@ -0,0 +1,40 @@
+# yosys -m wildebeest -s carrychain-techmap-accumulator.ys
+
+#A registered accumulator : the adder goes to the hard carry chain while the
+#state still legalizes onto the flip flops described by the config.
+
+read_verilog -lib ../data/carrychain/models/tech_carry.v
+
+read_verilog <<EOF
+module carrychain_accumulator
+  # (
+     parameter WIDTH = 8
+     )
+   (
+    input                    clk,
+    input                    resetn,
+    input [(WIDTH-1):0]      a,
+    output reg [(WIDTH-1):0] y
+    );
+
+   always @(posedge clk or negedge resetn) begin
+      if (~resetn) begin
+         y <= 'h0;
+      end
+      else begin
+         y <= y + a;
+      end
+   end
+
+endmodule
+EOF
+
+synth_fpga -config ../data/carrychain/carrychain.json
+
+#The whole adder is in the carry chain : no '$alu' survived and no soft
+#logic was needed.
+select -assert-count 8 */t:efpga_carry
+select -assert-count 0 */t:$alu
+select -assert-count 0 */t:$lut
+
+select -assert-count 8 */t:dffr
diff --git a/tests/unit/carrychain/carrychain-techmap-add_carry_in.ys b/tests/unit/carrychain/carrychain-techmap-add_carry_in.ys
new file mode 100644
index 0000000..65c0c23
--- /dev/null
+++ b/tests/unit/carrychain/carrychain-techmap-add_carry_in.ys
@@ -0,0 +1,34 @@
+# yosys -m wildebeest -s carrychain-techmap-add_carry_in.ys
+
+#'a + b + ci' folds the extra term into the 'CI' port of the '$alu', so the
+#'ci' primary input must reach exactly one carry cell : the bottom of the
+#chain.
+
+read_verilog -lib ../data/carrychain/models/tech_carry.v
+
+read_verilog <<EOF
+module carrychain_add_carry_in
+  # (
+     parameter WIDTH = 8
+     )
+   (
+    input [(WIDTH-1):0] a,
+    input [(WIDTH-1):0] b,
+    input               ci,
+    output [WIDTH:0]    y
+    );
+
+   assign y = a + b + ci;
+
+endmodule
+EOF
+
+synth_fpga -config ../data/carrychain/carrychain.json
+
+#The whole adder is in the carry chain : no '$alu' survived and no soft
+#logic was needed.
+select -assert-count 9 */t:efpga_carry
+select -assert-count 0 */t:$alu
+select -assert-count 0 */t:$lut
+
+select -assert-count 1 */w:ci %co */t:efpga_carry %i
diff --git a/tests/unit/carrychain/carrychain-techmap-add_signed.ys b/tests/unit/carrychain/carrychain-techmap-add_signed.ys
new file mode 100644
index 0000000..aa5e1bf
--- /dev/null
+++ b/tests/unit/carrychain/carrychain-techmap-add_signed.ys
@@ -0,0 +1,30 @@
+# yosys -m wildebeest -s carrychain-techmap-add_signed.ys
+
+#A signed adder maps onto the hard carry chain just like the unsigned one :
+#the sign extension is absorbed by the '$pos' conversions of the techmap.
+
+read_verilog -lib ../data/carrychain/models/tech_carry.v
+
+read_verilog <<EOF
+module carrychain_add_signed
+  # (
+     parameter WIDTH = 8
+     )
+   (
+    input signed [(WIDTH-1):0] a,
+    input signed [(WIDTH-1):0] b,
+    output signed [WIDTH:0]    y
+    );
+
+   assign y = a + b;
+
+endmodule
+EOF
+
+synth_fpga -config ../data/carrychain/carrychain.json
+
+#The whole adder is in the carry chain : no '$alu' survived and no soft
+#logic was needed.
+select -assert-count 9 */t:efpga_carry
+select -assert-count 0 */t:$alu
+select -assert-count 0 */t:$lut
diff --git a/tests/unit/carrychain/carrychain-techmap-add_unsigned.ys b/tests/unit/carrychain/carrychain-techmap-add_unsigned.ys
new file mode 100644
index 0000000..fcd9e7c
--- /dev/null
+++ b/tests/unit/carrychain/carrychain-techmap-add_unsigned.ys
@@ -0,0 +1,36 @@
+# yosys -m wildebeest -s carrychain-techmap-add_unsigned.ys
+
+#An unsigned 8 bit + 8 bit -> 9 bit adder must map entirely onto the hard
+#carry chain : one 'efpga_carry' per result bit and nothing left in soft
+#logic.
+
+read_verilog -lib ../data/carrychain/models/tech_carry.v
+
+read_verilog <<EOF
+module carrychain_add_unsigned
+  # (
+     parameter WIDTH = 8
+     )
+   (
+    input [(WIDTH-1):0] a,
+    input [(WIDTH-1):0] b,
+    output [WIDTH:0]    y
+    );
+
+   assign y = a + b;
+
+endmodule
+EOF
+
+synth_fpga -config ../data/carrychain/carrychain.json
+
+#The whole adder is in the carry chain : no '$alu' survived and no soft
+#logic was needed.
+select -assert-count 9 */t:efpga_carry
+select -assert-count 0 */t:$alu
+select -assert-count 0 */t:$lut
+
+#Both operands feed the chain and the chain drives the whole result.
+select -assert-count 8 */w:a %co */t:efpga_carry %i
+select -assert-count 8 */w:b %co */t:efpga_carry %i
+select -assert-count 9 */w:y %ci */t:efpga_carry %i
diff --git a/tests/unit/carrychain/carrychain-techmap-compare.ys b/tests/unit/carrychain/carrychain-techmap-compare.ys
new file mode 100644
index 0000000..9c82365
--- /dev/null
+++ b/tests/unit/carrychain/carrychain-techmap-compare.ys
@@ -0,0 +1,28 @@
+# yosys -m wildebeest -s carrychain-techmap-compare.ys
+
+#'alumacc' implements a magnitude comparison with an '$alu' whose carry out
+#is the result, so a comparison must use the hard carry chain too (the sum
+#bits are simply left unused).
+
+read_verilog -lib ../data/carrychain/models/tech_carry.v
+
+read_verilog <<EOF
+module carrychain_compare
+  # (
+     parameter WIDTH = 8
+     )
+   (
+    input [(WIDTH-1):0] a,
+    input [(WIDTH-1):0] b,
+    output              gt
+    );
+
+   assign gt = (a > b);
+
+endmodule
+EOF
+
+synth_fpga -config ../data/carrychain/carrychain.json
+
+select -assert-count 8 */t:efpga_carry
+select -assert-count 0 */t:$alu
diff --git a/tests/unit/carrychain/carrychain-techmap-increment.ys b/tests/unit/carrychain/carrychain-techmap-increment.ys
new file mode 100644
index 0000000..ce3c7a2
--- /dev/null
+++ b/tests/unit/carrychain/carrychain-techmap-increment.ys
@@ -0,0 +1,29 @@
+# yosys -m wildebeest -s carrychain-techmap-increment.ys
+
+#An incrementer is an '$alu' with a constant operand : it must be mapped onto
+#the hard carry chain rather than onto soft logic.
+
+read_verilog -lib ../data/carrychain/models/tech_carry.v
+
+read_verilog <<EOF
+module carrychain_increment
+  # (
+     parameter WIDTH = 8
+     )
+   (
+    input [(WIDTH-1):0]  a,
+    output [(WIDTH-1):0] y
+    );
+
+   assign y = a + 1'b1;
+
+endmodule
+EOF
+
+synth_fpga -config ../data/carrychain/carrychain.json
+
+#The whole adder is in the carry chain : no '$alu' survived and no soft
+#logic was needed.
+select -assert-count 8 */t:efpga_carry
+select -assert-count 0 */t:$alu
+select -assert-count 0 */t:$lut
diff --git a/tests/unit/carrychain/carrychain-techmap-min8_narrow.ys b/tests/unit/carrychain/carrychain-techmap-min8_narrow.ys
new file mode 100644
index 0000000..bedc55e
--- /dev/null
+++ b/tests/unit/carrychain/carrychain-techmap-min8_narrow.ys
@@ -0,0 +1,26 @@
+# yosys -m wildebeest -s carrychain-techmap-min8_narrow.ys
+
+#A techmap that rejects narrow adders through '_TECHMAP_FAIL_' must leave
+#them to the generic '+/techmap.v' soft logic mapping : a 4 bit adder gets no
+#carry cell at all.
+
+read_verilog -lib ../data/carrychain/models/tech_carry.v
+
+read_verilog <<EOF
+module carrychain_min8_narrow
+   (
+    input [3:0]  a,
+    input [3:0]  b,
+    output [4:0] y
+    );
+
+   assign y = a + b;
+
+endmodule
+EOF
+
+synth_fpga -config ../data/carrychain/carrychain_min8.json
+
+select -assert-count 0 */t:efpga_carry
+select -assert-count 0 */t:$alu
+select -assert-min 1 */t:$lut
diff --git a/tests/unit/carrychain/carrychain-techmap-min8_wide.ys b/tests/unit/carrychain/carrychain-techmap-min8_wide.ys
new file mode 100644
index 0000000..8e240a4
--- /dev/null
+++ b/tests/unit/carrychain/carrychain-techmap-min8_wide.ys
@@ -0,0 +1,30 @@
+# yosys -m wildebeest -s carrychain-techmap-min8_wide.ys
+
+#Same techmap as 'carrychain-techmap-min8_narrow' : an adder that is wide
+#enough must be accepted and fully mapped onto the hard carry chain.
+
+read_verilog -lib ../data/carrychain/models/tech_carry.v
+
+read_verilog <<EOF
+module carrychain_min8_wide
+  # (
+     parameter WIDTH = 8
+     )
+   (
+    input [(WIDTH-1):0] a,
+    input [(WIDTH-1):0] b,
+    output [WIDTH:0]    y
+    );
+
+   assign y = a + b;
+
+endmodule
+EOF
+
+synth_fpga -config ../data/carrychain/carrychain_min8.json
+
+#The whole adder is in the carry chain : no '$alu' survived and no soft
+#logic was needed.
+select -assert-count 9 */t:efpga_carry
+select -assert-count 0 */t:$alu
+select -assert-count 0 */t:$lut
diff --git a/tests/unit/carrychain/carrychain-techmap-sub.ys b/tests/unit/carrychain/carrychain-techmap-sub.ys
new file mode 100644
index 0000000..61f4db4
--- /dev/null
+++ b/tests/unit/carrychain/carrychain-techmap-sub.ys
@@ -0,0 +1,29 @@
+# yosys -m wildebeest -s carrychain-techmap-sub.ys
+
+#A subtraction is an '$alu' with 'BI' (invert B) asserted and a carry in tied
+#to one : the arithmetic must still land on the hard carry chain, only the
+#operand inversion is left to soft logic.
+
+read_verilog -lib ../data/carrychain/models/tech_carry.v
+
+read_verilog <<EOF
+module carrychain_sub
+  # (
+     parameter WIDTH = 8
+     )
+   (
+    input [(WIDTH-1):0]  a,
+    input [(WIDTH-1):0]  b,
+    output [(WIDTH-1):0] y
+    );
+
+   assign y = a - b;
+
+endmodule
+EOF
+
+synth_fpga -config ../data/carrychain/carrychain.json
+
+select -assert-count 8 */t:efpga_carry
+select -assert-count 0 */t:$alu
+select -assert-count 8 */w:a %co */t:efpga_carry %i
diff --git a/tests/unit/carrychain/carrychain-techmap-two_adders.ys b/tests/unit/carrychain/carrychain-techmap-two_adders.ys
new file mode 100644
index 0000000..2e97e9b
--- /dev/null
+++ b/tests/unit/carrychain/carrychain-techmap-two_adders.ys
@@ -0,0 +1,37 @@
+# yosys -m wildebeest -s carrychain-techmap-two_adders.ys
+
+#Two independent adders must give two independent carry chains : all 18
+#result bits are mapped and nothing is left in soft logic.
+
+read_verilog -lib ../data/carrychain/models/tech_carry.v
+
+read_verilog <<EOF
+module carrychain_two_adders
+  # (
+     parameter WIDTH = 8
+     )
+   (
+    input [(WIDTH-1):0] a,
+    input [(WIDTH-1):0] b,
+    input [(WIDTH-1):0] c,
+    input [(WIDTH-1):0] d,
+    output [WIDTH:0]    y0,
+    output [WIDTH:0]    y1
+    );
+
+   assign y0 = a + b;
+   assign y1 = c + d;
+
+endmodule
+EOF
+
+synth_fpga -config ../data/carrychain/carrychain.json
+
+#The whole adder is in the carry chain : no '$alu' survived and no soft
+#logic was needed.
+select -assert-count 18 */t:efpga_carry
+select -assert-count 0 */t:$alu
+select -assert-count 0 */t:$lut
+
+select -assert-count 9 */w:y0 %ci */t:efpga_carry %i
+select -assert-count 9 */w:y1 %ci */t:efpga_carry %i
diff --git a/tests/unit/carrychain/carrychain-techmap-undeclared_primitive.ys b/tests/unit/carrychain/carrychain-techmap-undeclared_primitive.ys
new file mode 100644
index 0000000..f6bb500
--- /dev/null
+++ b/tests/unit/carrychain/carrychain-techmap-undeclared_primitive.ys
@@ -0,0 +1,31 @@
+# yosys -m wildebeest -s carrychain-techmap-undeclared_primitive.ys
+
+#The adder techmap does not need the carry chain primitive to be declared :
+#with no model read in, the same 9 'efpga_carry' cells must be created.  This
+#is what keeps the techmap file itself free of any primitive definition (a
+#module living in a techmap file is a mapping rule and would be expanded back
+#into soft logic).
+
+read_verilog <<EOF
+module carrychain_undeclared_primitive
+  # (
+     parameter WIDTH = 8
+     )
+   (
+    input [(WIDTH-1):0] a,
+    input [(WIDTH-1):0] b,
+    output [WIDTH:0]    y
+    );
+
+   assign y = a + b;
+
+endmodule
+EOF
+
+synth_fpga -config ../data/carrychain/carrychain.json
+
+#The whole adder is in the carry chain : no '$alu' survived and no soft
+#logic was needed.
+select -assert-count 9 */t:efpga_carry
+select -assert-count 0 */t:$alu
+select -assert-count 0 */t:$lut
diff --git a/tests/unit/carrychain/carrychain-techmap-wide_add.ys b/tests/unit/carrychain/carrychain-techmap-wide_add.ys
new file mode 100644
index 0000000..d6186dc
--- /dev/null
+++ b/tests/unit/carrychain/carrychain-techmap-wide_add.ys
@@ -0,0 +1,30 @@
+# yosys -m wildebeest -s carrychain-techmap-wide_add.ys
+
+#A 32 bit adder exercises a long carry chain : 33 result bits, 33 hard carry
+#cells and no soft logic.
+
+read_verilog -lib ../data/carrychain/models/tech_carry.v
+
+read_verilog <<EOF
+module carrychain_wide_add
+  # (
+     parameter WIDTH = 32
+     )
+   (
+    input [(WIDTH-1):0] a,
+    input [(WIDTH-1):0] b,
+    output [WIDTH:0]    y
+    );
+
+   assign y = a + b;
+
+endmodule
+EOF
+
+synth_fpga -config ../data/carrychain/carrychain.json
+
+#The whole adder is in the carry chain : no '$alu' survived and no soft
+#logic was needed.
+select -assert-count 33 */t:efpga_carry
+select -assert-count 0 */t:$alu
+select -assert-count 0 */t:$lut
diff --git a/tests/unit/carrychain/carrychain-techmap-with_dsp.ys b/tests/unit/carrychain/carrychain-techmap-with_dsp.ys
new file mode 100644
index 0000000..bb2a8ff
--- /dev/null
+++ b/tests/unit/carrychain/carrychain-techmap-with_dsp.ys
@@ -0,0 +1,33 @@
+# yosys -m wildebeest -s carrychain-techmap-with_dsp.ys
+
+#Adder tech mapping is independent from DSP inference : with a config that
+#describes both, the multiply goes to the DSP and the unrelated adder to the
+#hard carry chain.
+
+read_verilog -lib ../data/carrychain/models/tech_carry.v
+
+read_verilog <<EOF
+module carrychain_with_dsp
+  # (
+     parameter WIDTH = 8
+     )
+   (
+    input [(WIDTH-1):0]    a,
+    input [(WIDTH-1):0]    b,
+    input [(WIDTH-1):0]    c,
+    input [(WIDTH-1):0]    d,
+    output [(2*WIDTH-1):0] p,
+    output [WIDTH:0]       s
+    );
+
+   assign p = a * b;
+   assign s = c + d;
+
+endmodule
+EOF
+
+synth_fpga -config ../data/carrychain/carrychain_dsp.json
+
+select -assert-count 1 */t:DSP48
+select -assert-count 9 */t:efpga_carry
+select -assert-count 0 */t:$alu
diff --git a/tests/unit/carrychain/carrychain-techmap-with_no_dsp.ys b/tests/unit/carrychain/carrychain-techmap-with_no_dsp.ys
new file mode 100644
index 0000000..b9b5c39
--- /dev/null
+++ b/tests/unit/carrychain/carrychain-techmap-with_no_dsp.ys
@@ -0,0 +1,35 @@
+# yosys -m wildebeest -s carrychain-techmap-with_no_dsp.ys
+
+#'-no_dsp' disables DSP inference only : the multiply falls back to soft
+#logic while the adder must still be mapped onto the hard carry chain.
+
+read_verilog -lib ../data/carrychain/models/tech_carry.v
+
+read_verilog <<EOF
+module carrychain_with_no_dsp
+  # (
+     parameter WIDTH = 8
+     )
+   (
+    input [(WIDTH-1):0]    a,
+    input [(WIDTH-1):0]    b,
+    input [(WIDTH-1):0]    c,
+    input [(WIDTH-1):0]    d,
+    output [(2*WIDTH-1):0] p,
+    output [WIDTH:0]       s
+    );
+
+   assign p = a * b;
+   assign s = c + d;
+
+endmodule
+EOF
+
+synth_fpga -config ../data/carrychain/carrychain_dsp.json -no_dsp
+
+select -assert-count 0 */t:DSP48
+select -assert-count 9 */t:efpga_carry
+select -assert-count 0 */t:$alu
+
+#The multiply is the only thing left in soft logic.
+select -assert-min 1 */t:$lut
diff --git a/tests/unit/data/carrychain/carrychain.json b/tests/unit/data/carrychain/carrychain.json
new file mode 100644
index 0000000..54d224e
--- /dev/null
+++ b/tests/unit/data/carrychain/carrychain.json
@@ -0,0 +1,23 @@
+{
+    "version": 1,
+    "partname": "z1010",
+    "lut_size": 4,
+    "flipflops": {
+        "features": [
+            "async_reset",
+            "async_set",
+            "flop_enable"
+        ],
+        "models": {},
+        "legalize_list": [
+            "$_DFF_PN0_",
+            "$_DFF_P_",
+            "$_DFFE_PP_",
+            "$_DFFE_PN0P_"
+        ],
+        "techmap": "../z1010/tech_flops.v"
+    },
+    "adders": {
+        "techmap": "tech_adder.v"
+    }
+}
diff --git a/tests/unit/data/carrychain/carrychain_abspath.json b/tests/unit/data/carrychain/carrychain_abspath.json
new file mode 100644
index 0000000..7582885
--- /dev/null
+++ b/tests/unit/data/carrychain/carrychain_abspath.json
@@ -0,0 +1,23 @@
+{
+    "version": 1,
+    "partname": "z1010",
+    "lut_size": 4,
+    "flipflops": {
+        "features": [
+            "async_reset",
+            "async_set",
+            "flop_enable"
+        ],
+        "models": {},
+        "legalize_list": [
+            "$_DFF_PN0_",
+            "$_DFF_P_",
+            "$_DFFE_PP_",
+            "$_DFFE_PN0P_"
+        ],
+        "techmap": "../z1010/tech_flops.v"
+    },
+    "adders": {
+        "techmap": "/tech_adder.v"
+    }
+}
diff --git a/tests/unit/data/carrychain/carrychain_dsp.json b/tests/unit/data/carrychain/carrychain_dsp.json
new file mode 100644
index 0000000..80ea2d6
--- /dev/null
+++ b/tests/unit/data/carrychain/carrychain_dsp.json
@@ -0,0 +1,44 @@
+{
+    "version": 1,
+    "partname": "z1010",
+    "lut_size": 4,
+    "flipflops": {
+        "features": [
+            "async_reset",
+            "async_set",
+            "flop_enable"
+        ],
+        "models": {},
+        "legalize_list": [
+            "$_DFF_PN0_",
+            "$_DFF_P_",
+            "$_DFFE_PP_",
+            "$_DFFE_PN0P_"
+        ],
+        "techmap": "../z1010/tech_flops.v"
+    },
+    "brams": {
+        "memory_libmap": [
+            "../z1010/bram_memory_map.txt"
+        ],
+        "techmap": [
+            "../z1010/tech_bram.v"
+        ]
+    },
+    "dsps": {
+        "family": "DSP48",
+        "techmap": "../z1010/mult18x18_DSP48.v",
+        "techmap_parameters": {
+            "DSP_A_MAXWIDTH": 18,
+            "DSP_B_MAXWIDTH": 18,
+            "DSP_A_MINWIDTH": 2,
+            "DSP_B_MINWIDTH": 2,
+            "DSP_Y_MINWIDTH": 9,
+            "DSP_SIGNEDONLY": 1,
+            "DSP_NAME": "$__MUL18X18"
+        }
+    },
+    "adders": {
+        "techmap": "tech_adder.v"
+    }
+}
diff --git a/tests/unit/data/carrychain/carrychain_min8.json b/tests/unit/data/carrychain/carrychain_min8.json
new file mode 100644
index 0000000..798b143
--- /dev/null
+++ b/tests/unit/data/carrychain/carrychain_min8.json
@@ -0,0 +1,23 @@
+{
+    "version": 1,
+    "partname": "z1010",
+    "lut_size": 4,
+    "flipflops": {
+        "features": [
+            "async_reset",
+            "async_set",
+            "flop_enable"
+        ],
+        "models": {},
+        "legalize_list": [
+            "$_DFF_PN0_",
+            "$_DFF_P_",
+            "$_DFFE_PP_",
+            "$_DFFE_PN0P_"
+        ],
+        "techmap": "../z1010/tech_flops.v"
+    },
+    "adders": {
+        "techmap": "tech_adder_min8.v"
+    }
+}
diff --git a/tests/unit/data/carrychain/carrychain_no_adders.json b/tests/unit/data/carrychain/carrychain_no_adders.json
new file mode 100644
index 0000000..a4cae04
--- /dev/null
+++ b/tests/unit/data/carrychain/carrychain_no_adders.json
@@ -0,0 +1,20 @@
+{
+    "version": 1,
+    "partname": "z1010",
+    "lut_size": 4,
+    "flipflops": {
+        "features": [
+            "async_reset",
+            "async_set",
+            "flop_enable"
+        ],
+        "models": {},
+        "legalize_list": [
+            "$_DFF_PN0_",
+            "$_DFF_P_",
+            "$_DFFE_PP_",
+            "$_DFFE_PN0P_"
+        ],
+        "techmap": "../z1010/tech_flops.v"
+    }
+}
diff --git a/tests/unit/data/carrychain/models/tech_carry.v b/tests/unit/data/carrychain/models/tech_carry.v
new file mode 100644
index 0000000..90e18fd
--- /dev/null
+++ b/tests/unit/data/carrychain/models/tech_carry.v
@@ -0,0 +1,21 @@
+//tech_carry.v
+//
+//Blackbox declaration of the hard carry-chain adder primitive targeted by
+//data/z1010/tech_adder.v.  Kept out of the techmap file on purpose : any
+//module in a techmap file is a mapping rule, so the primitive would be
+//expanded back into soft logic if it lived there.
+
+(* blackbox *)
+module efpga_carry
+  (
+   input  a,
+   input  b,
+   input  ci,
+   output s,
+   output co
+   );
+
+   assign s  = a ^ b ^ ci;
+   assign co = (a & b) | (a & ci) | (b & ci);
+
+endmodule
diff --git a/tests/unit/data/carrychain/tech_adder.v b/tests/unit/data/carrychain/tech_adder.v
new file mode 100644
index 0000000..97d40f8
--- /dev/null
+++ b/tests/unit/data/carrychain/tech_adder.v
@@ -0,0 +1,65 @@
+//tech_adder.v
+//
+//Hard carry-chain adder tech mapping used by the tests/unit/carrychain
+//unit tests.  It maps the $alu cells created by the 'alumacc' pass onto a
+//bit-sliced hard carry-chain primitive ('efpga_carry') so that the
+//arithmetic never reaches the generic '+/techmap.v' soft logic mapping.
+//
+//The primitive itself is deliberately NOT declared in this file : modules
+//that live in a techmap file are themselves treated as mapping rules and
+//would be expanded back into soft logic.  The blackbox declaration lives in
+//models/tech_carry.v instead.
+
+(* techmap_celltype = "$alu" *)
+module \$__CARRYCHAIN_ALU (A, B, CI, BI, X, Y, CO);
+
+   parameter A_SIGNED = 0;
+   parameter B_SIGNED = 0;
+   parameter A_WIDTH = 1;
+   parameter B_WIDTH = 1;
+   parameter Y_WIDTH = 1;
+
+   (* force_downto *)
+   input [(A_WIDTH-1):0] A;
+   (* force_downto *)
+   input [(B_WIDTH-1):0] B;
+
+   input 		 CI, BI;
+
+   (* force_downto *)
+   output [(Y_WIDTH-1):0] X, Y;
+   (* force_downto *)
+   output [(Y_WIDTH-1):0] CO;
+
+   //Sign/zero extend both operands up to the full result width.
+   (* force_downto *)
+   wire [(Y_WIDTH-1):0]   AA, BB;
+
+   \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(AA));
+   \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(BB));
+
+   //'BI' asks for the B operand to be inverted (subtraction).
+   (* force_downto *)
+   wire [(Y_WIDTH-1):0]   BBB = BI ? ~BB : BB;
+
+   //The 'X' output of $alu is the propagate signal.
+   assign X = AA ^ BBB;
+
+   //Carry chain : bit 'i' consumes the carry out of bit 'i-1'.
+   (* force_downto *)
+   wire [(Y_WIDTH-1):0]   C = {CO, CI};
+
+   genvar 		  i;
+   generate
+      for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
+	 efpga_carry carry (
+			    .a(AA[i]),
+			    .b(BBB[i]),
+			    .ci(C[i]),
+			    .s(Y[i]),
+			    .co(CO[i])
+			    );
+      end
+   endgenerate
+
+endmodule
diff --git a/tests/unit/data/carrychain/tech_adder_min8.v b/tests/unit/data/carrychain/tech_adder_min8.v
new file mode 100644
index 0000000..2788b20
--- /dev/null
+++ b/tests/unit/data/carrychain/tech_adder_min8.v
@@ -0,0 +1,69 @@
+//tech_adder_min8.v
+//
+//Same hard carry-chain adder tech mapping as tech_adder.v, except that it
+//rejects any adder narrower than 8 bits through '_TECHMAP_FAIL_' so that
+//small adders are left behind for the generic soft logic mapping.  Used by
+//the tests/unit/carrychain unit tests.
+//
+//The primitive itself is deliberately NOT declared in this file : modules
+//that live in a techmap file are themselves treated as mapping rules and
+//would be expanded back into soft logic.  The blackbox declaration lives in
+//models/tech_carry.v instead.
+
+(* techmap_celltype = "$alu" *)
+module \$__CARRYCHAIN_MIN8_ALU (A, B, CI, BI, X, Y, CO);
+
+   parameter A_SIGNED = 0;
+   parameter B_SIGNED = 0;
+   parameter A_WIDTH = 1;
+   parameter B_WIDTH = 1;
+   parameter Y_WIDTH = 1;
+
+   (* force_downto *)
+   input [(A_WIDTH-1):0] A;
+   (* force_downto *)
+   input [(B_WIDTH-1):0] B;
+
+   input 		 CI, BI;
+
+   (* force_downto *)
+   output [(Y_WIDTH-1):0] X, Y;
+   (* force_downto *)
+   output [(Y_WIDTH-1):0] CO;
+
+   //Narrow adders are not worth a hard carry chain : reject them and let the
+   //generic '+/techmap.v' mapping turn them into soft logic.
+   wire 		 _TECHMAP_FAIL_ = (Y_WIDTH < 8);
+
+   //Sign/zero extend both operands up to the full result width.
+   (* force_downto *)
+   wire [(Y_WIDTH-1):0]   AA, BB;
+
+   \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(AA));
+   \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(BB));
+
+   //'BI' asks for the B operand to be inverted (subtraction).
+   (* force_downto *)
+   wire [(Y_WIDTH-1):0]   BBB = BI ? ~BB : BB;
+
+   //The 'X' output of $alu is the propagate signal.
+   assign X = AA ^ BBB;
+
+   //Carry chain : bit 'i' consumes the carry out of bit 'i-1'.
+   (* force_downto *)
+   wire [(Y_WIDTH-1):0]   C = {CO, CI};
+
+   genvar 		  i;
+   generate
+      for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
+	 efpga_carry carry (
+			    .a(AA[i]),
+			    .b(BBB[i]),
+			    .ci(C[i]),
+			    .s(Y[i]),
+			    .co(CO[i])
+			    );
+      end
+   endgenerate
+
+endmodule