diff --git a/.github/actions/setup-python/action.yml b/.github/actions/setup-container/action.yml similarity index 63% rename from .github/actions/setup-python/action.yml rename to .github/actions/setup-container/action.yml index fc8aa83a3b..9bb56f985a 100644 --- a/.github/actions/setup-python/action.yml +++ b/.github/actions/setup-container/action.yml @@ -2,8 +2,8 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: setup-python -description: Install Python dependencies once per job, and cache across jobs +name: setup-container +description: Set up the container's Bender and Python dependencies runs: using: "composite" @@ -30,6 +30,21 @@ runs: path: ~/.cache/uv key: uvcache-${{ hashFiles('uv.lock', '.python-version') }} + # Cache the .bender directory (checked out Bender dependencies) + - name: Cache Bender dependencies + uses: actions/cache@v4 + with: + path: .bender + key: bender-${{ hashFiles('Bender.lock') }} + + # In container jobs the entrypoint's `bender checkout` runs before + # actions/checkout populates the workspace, so it has no effect here and + # we need to check out Bender dependencies again after checkout. + - name: Checkout Bender dependencies + shell: sh + run: | + bender checkout + - name: Sync Python environment shell: sh run: | diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index c344db38b9..d7c037b782 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -37,13 +37,19 @@ jobs: # commit on this branch: CI doesn't necessarily run on every push # (e.g. superseded runs get cancelled), so a plain previous-commit # diff could silently skip over a real prerequisite change. + # + # On forks, `origin` is the fork itself, whose `main` can lag behind + # the upstream repo it was forked from, so we always fetch + # `main` from the canonical upstream repo instead of `origin`. run: | if [ "${{ github.ref_name }}" = "main" ]; then - echo "sha=${{ github.event.before }}" >> "$GITHUB_OUTPUT" + sha="${{ github.event.before }}" else - git fetch origin main - echo "sha=$(git merge-base origin/main HEAD)" >> "$GITHUB_OUTPUT" + git fetch https://github.com/pulp-platform/snitch_cluster.git main + sha="$(git merge-base FETCH_HEAD HEAD)" fi + echo "sha=$sha" >> "$GITHUB_OUTPUT" + echo "Base SHA: $sha" ########################## # Build Docker Container # @@ -118,7 +124,7 @@ jobs: - uses: actions/checkout@v4 with: submodules: 'recursive' - - uses: ./.github/actions/setup-python + - uses: ./.github/actions/setup-container - name: Build docs run: make docs @@ -133,7 +139,13 @@ jobs: - uses: actions/checkout@v4 with: submodules: 'recursive' - - uses: ./.github/actions/setup-python + - uses: ./.github/actions/setup-container + # For some reason, the checkout is done by a different user + # than that deploying to Github (root, possibly due to Docker). + # So we need to set the repository as a safe directory. + - name: Git config safe.directory + run: | + git config --global --add safe.directory $GITHUB_WORKSPACE - name: Generate documentation sources run: | make doc-srcs @@ -155,7 +167,7 @@ jobs: - uses: actions/checkout@v4 with: submodules: 'recursive' - - uses: ./.github/actions/setup-python + - uses: ./.github/actions/setup-container - name: Run pytest run: pytest @@ -173,7 +185,7 @@ jobs: - uses: actions/checkout@v4 with: submodules: 'recursive' - - uses: ./.github/actions/setup-python + - uses: ./.github/actions/setup-container - name: Hash Verilator prerequisites id: list-make-prerequisites uses: colluca/list-make-prerequisites@v1.0.0 @@ -203,7 +215,7 @@ jobs: - uses: actions/checkout@v4 with: submodules: 'recursive' - - uses: ./.github/actions/setup-python + - uses: ./.github/actions/setup-container - name: Build Software run: | make sw -j @@ -238,7 +250,7 @@ jobs: - uses: actions/checkout@v4 with: submodules: 'recursive' - - uses: ./.github/actions/setup-python + - uses: ./.github/actions/setup-container - name: Hash Verilator prerequisites id: list-make-prerequisites uses: colluca/list-make-prerequisites@v1.0.0 @@ -260,7 +272,7 @@ jobs: make CFG_OVERRIDE=cfg/mempool.json verilator - name: Build Software for mempool tests run: | - make sw CFG_OVERRIDE=cfg/mempool.json SN_MCPU=snitch-mempool -j + make sw CFG_OVERRIDE=cfg/mempool.json -j - name: Run Tests run: | cd test @@ -270,7 +282,54 @@ jobs: # testbench does not wait until all the instructions are retired # (compiler introduces few instructions after exit routine). run: | - make SIM_DIR=./test/runs/simple SN_MCPU=snitch-mempool DEBUG=ON annotate -j + make SIM_DIR=./test/runs/simple DEBUG=ON annotate -j + + ###################################################### + # Simulate SW on Snitch Cluster (Spatz) w/ Verilator # + ###################################################### + + snitch-spatz-cluster-vlt: + name: Build and Simulate Spatz Snitch Cluster w/ Verilator + runs-on: ubuntu-22.04 + needs: [docker-meta, build-hw-image] + container: + image: ${{ needs.docker-meta.outputs.hw_image_name }} + volumes: + - ${{ github.workspace }}:/repo + defaults: + run: + working-directory: /repo + steps: + - uses: actions/checkout@v4 + with: + submodules: 'recursive' + - uses: ./.github/actions/setup-container + - name: Hash Verilator prerequisites + id: list-make-prerequisites + uses: colluca/list-make-prerequisites@v1.0.0 + with: + target: verilator + flags: --recursive + - name: Set up cache for Verilator build + id: verilator-cache + uses: actions/cache@v4 + with: + path: | + /repo/target/sim/build/bin + key: verilator-spatz-${{ steps.list-make-prerequisites.outputs.hash }} + restore-keys: | + verilator-spatz- + - name: Build Hardware + if: steps.verilator-cache.outputs.cache-hit != 'true' + run: | + make CFG_OVERRIDE=cfg/spatz.json verilator + - name: Build Software + run: | + make CFG_OVERRIDE=cfg/spatz.json sw -j + - name: Run Tests + run: | + cd test + ../util/experiments/run.py spatz.yaml --simulator verilator -j ############# # Synthesis # @@ -292,10 +351,10 @@ jobs: with: submodules: 'recursive' fetch-depth: 0 - - uses: ./.github/actions/setup-python + - uses: ./.github/actions/setup-container - name: Check if Yosys prerequisites changed id: make-prerequisites-changed - uses: colluca/make-prerequisites-changed@v1.1.1 + uses: colluca/make-prerequisites-changed@v1.2.0 with: target: yosys flags: --recursive @@ -304,6 +363,15 @@ jobs: if: steps.make-prerequisites-changed.outputs.changed == 'true' run: | make CFG_OVERRIDE=cfg/yosys-ci.json yosys + - name: Upload Yosys logs + if: failure() + uses: actions/upload-artifact@v4 + with: + name: yosys-synthesis-logs + path: | + target/asic/yosys/*.log + target/asic/yosys/reports/ + if-no-files-found: warn ###################### # Sources Up-to-Date # @@ -324,7 +392,7 @@ jobs: - uses: actions/checkout@v4 with: submodules: 'recursive' - - uses: ./.github/actions/setup-python + - uses: ./.github/actions/setup-container - name: Generate opcodes run: | ./util/clustergen/generate-opcodes.sh diff --git a/.gitignore b/.gitignore index 9b07c09fce..8875bca923 100644 --- a/.gitignore +++ b/.gitignore @@ -4,7 +4,8 @@ !/nonfree/util/.gitignore .cockpitgroup -# Dependency files +# Dependencies +/deps /.bender/ # Modelsim files diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 3b962c7ad1..5a17448e12 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -4,6 +4,7 @@ variables: GIT_STRATEGY: clone + GIT_DEPTH: 0 # Enable colors in CI terminal TERM: ansi FORCE_COLOR: 1 @@ -108,12 +109,9 @@ snitch-ip-tests: - snitch_cluster - tcdm_interface - snitch_ssr - - reqrsp_interface script: - make rtl -j - - cd hw/$IP - - ./util/compile.sh - - ./util/run_vsim.sh + - make test-$IP #################### # Simulation tests # @@ -123,7 +121,7 @@ snitch-ip-tests: snitch-cluster-vlt: needs: [snitch-cluster-sw] script: - - make verilator + - make verilator TRACE=OFF -j - cd test - ../util/experiments/run.py run.yaml --simulator verilator -j --run-dir runs/vlt @@ -131,7 +129,7 @@ snitch-cluster-vlt: snitch-cluster-vcs: needs: [snitch-cluster-sw] script: - - make vcs + - make vcs TRACE=OFF -j - cd test - ../util/experiments/run.py run.yaml --simulator vcs -j --run-dir runs/vcs @@ -164,7 +162,7 @@ snitch-cluster-vsim: snitch-cluster-omega-vsim: script: - make CFG_OVERRIDE=cfg/omega.json sw -j - - make vsim -j + - make vsim TRACE=OFF -j - cd test - ../util/experiments/run.py run.yaml --simulator vsim -j --run-dir runs/vsim @@ -172,34 +170,42 @@ snitch-cluster-omega-vsim: snitch-cluster-mchan-vsim: script: - make CFG_OVERRIDE=cfg/dma_mchan.json sw -j - - make vsim -j + - make vsim TRACE=OFF -j - cd test - ../util/experiments/run.py dma_mchan.yaml --simulator vsim -j --run-dir runs/vsim # Test Mempool configuration snitch-cluster-mempool-vsim: script: - - make CFG_OVERRIDE=cfg/mempool.json SN_MCPU=snitch-mempool sw -j + - make CFG_OVERRIDE=cfg/mempool.json sw -j - make vsim -j - cd test - ../util/experiments/run.py mempool.yaml --simulator vsim -j --run-dir runs/vsim - - make -C .. SIM_DIR=$PWD/runs/vsim/simple SN_MCPU=snitch-mempool annotate -j + - make -C .. SIM_DIR=$PWD/runs/vsim/simple annotate -j # Additional tests for different FREP configurations snitch-cluster-frep-vsim: script: # Large FREP configuration - make CFG_OVERRIDE=cfg/frep_xl.json sw -j - - make vsim -j + - make vsim TRACE=OFF -j - cd test - ../util/experiments/run.py frep_xl.yaml --simulator vsim -j --run-dir runs/vsim - cd - # Small FREP configuration - make CFG_OVERRIDE=cfg/frep_xs.json sw -j - - make vsim -j + - make vsim TRACE=OFF -j - cd test - ../util/experiments/run.py frep_xs.yaml --simulator vsim -j --run-dir runs/vsim +# Test Spatz configuration +snitch-cluster-spatz-vsim: + script: + - make CFG_OVERRIDE=cfg/spatz.json sw -j + - make vsim TRACE=OFF -j + - cd test + - ../util/experiments/run.py spatz.yaml --simulator vsim -j --run-dir runs/vsim + # COPIFT experiments snitch-cluster-copift-vsim: script: diff --git a/Bender.lock b/Bender.lock index ef8814e808..a85d6b855c 100644 --- a/Bender.lock +++ b/Bender.lock @@ -55,6 +55,22 @@ packages: source: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] + core_ips: + revision: 5d0eaf02297ef0818f83e178f2818435eaa8fc05 + version: 0.1.0 + source: + Git: https://github.com/pulp-platform/core_ips.git + dependencies: + - axi + - common_cells + - reqrsp_interface + core_v_xif: + revision: fad32c62f07ec7304a7169640eaf946da3727f77 + version: null + source: + Git: https://github.com/pulp-platform/core-v-xif.git + dependencies: + - common_cells fpnew: revision: 46cb33a4ce6b04b83ec38ebd288dd58a031a6390 version: null @@ -101,6 +117,15 @@ packages: - axi - common_cells - common_verification + reqrsp_interface: + revision: 390e41cd4885f09548dda6e1e989aee561e03986 + version: 0.1.0 + source: + Git: https://github.com/pulp-platform/reqrsp_interface.git + dependencies: + - axi + - common_cells + - tech_cells_generic riscv-dbg: revision: 358f90110220adf7a083f8b65d157e836d706236 version: 0.8.1 @@ -116,6 +141,17 @@ packages: Git: https://github.com/pulp-platform/scm.git dependencies: - tech_cells_generic + spatz_vpu: + revision: 0266c93f3e660db0d2eb756a00fa622b9076ddd9 + version: null + source: + Git: https://github.com/pulp-platform/spatz_vpu.git + dependencies: + - common_cells + - core_ips + - fpnew + - reqrsp_interface + - tech_cells_generic tech_cells_generic: revision: 3a3de73632a06826b1bd9c65a0a2e92b32016845 version: 0.2.14 diff --git a/Bender.yml b/Bender.yml index 56381ce282..3b38dc3897 100644 --- a/Bender.yml +++ b/Bender.yml @@ -23,7 +23,6 @@ remotes: dependencies: tech_cells_generic: 0.2.14 - riscv-dbg: 0.8.1 cluster_icache: git: https://github.com/pulp-platform/cluster_icache.git rev: common-cells-v2 @@ -41,12 +40,25 @@ dependencies: git: https://github.com/colluca/axi.git rev: multicast common_cells: 2.0.0-beta.2 + core_v_xif: + git: https://github.com/pulp-platform/core-v-xif.git + rev: colluca/cvxif-demux-bender-ready FPnew: git: https://github.com/pulp-platform/cvfpu.git rev: common-cells-v2 + reqrsp_interface: 0.1.0 + core_ips: 0.1.0 + riscv-dbg: 0.8.1 + spatz_vpu: + git: https://github.com/pulp-platform/spatz_vpu.git + rev: common_cell_v2 + +workspace: + package_links: + # Required for proper Python integration + deps/spatz_vpu: spatz_vpu export_include_dirs: - - hw/reqrsp_interface/include - hw/mem_interface/include - hw/tcdm_interface/include - hw/dca_interface/include @@ -59,12 +71,11 @@ sources: - files: # Level 0 - hw/snitch/src/snitch_pma_pkg.sv - - hw/snitch/src/riscv_instr.sv + - hw/snitch/src/snitch_riscv_instr.sv # Level 1 - hw/snitch/src/snitch_pkg.sv # Level 2 - hw/snitch/src/snitch_regfile_ff.sv - - hw/snitch/src/snitch_lsu.sv - hw/snitch/src/snitch_l0_tlb.sv - target: not(disable_pmcs) defines: @@ -79,33 +90,6 @@ sources: files: - hw/snitch/test/snitch_l0_tlb_tb.sv - # reqrsp_interface - - files: - # Level 0 - - hw/reqrsp_interface/src/generic_reqrsp_cut.sv - - hw/reqrsp_interface/src/generic_reqrsp_demux.sv - - hw/reqrsp_interface/src/generic_reqrsp_mux.sv - - hw/reqrsp_interface/src/reqrsp_pkg.sv - # Level 1 - - hw/reqrsp_interface/src/reqrsp_intf.sv - # Level 2 - - hw/reqrsp_interface/src/axi_to_reqrsp.sv - - hw/reqrsp_interface/src/reqrsp_cut.sv - - hw/reqrsp_interface/src/reqrsp_demux.sv - - hw/reqrsp_interface/src/reqrsp_iso.sv - - hw/reqrsp_interface/src/reqrsp_mux.sv - - hw/reqrsp_interface/src/reqrsp_to_axi.sv - - target: test - files: - - hw/reqrsp_interface/src/reqrsp_test.sv - - target: all(tb, not(verilator)) - files: - - hw/reqrsp_interface/test/axi_to_reqrsp_tb.sv - - hw/reqrsp_interface/test/reqrsp_demux_tb.sv - - hw/reqrsp_interface/test/reqrsp_idempotent_tb.sv - - hw/reqrsp_interface/test/reqrsp_mux_tb.sv - - hw/reqrsp_interface/test/reqrsp_to_axi_tb.sv - # mem_interface - files: - hw/mem_interface/src/mem_wide_narrow_mux.sv @@ -122,16 +106,18 @@ sources: # Level 0 - hw/tcdm_interface/src/tcdm_interface.sv # Level 1 + - hw/tcdm_interface/src/tcdm_width_converter.sv - hw/tcdm_interface/src/axi_to_tcdm.sv - - hw/tcdm_interface/src/reqrsp_to_tcdm.sv + - hw/tcdm_interface/src/lsu_to_tcdm.sv - hw/tcdm_interface/src/tcdm_mux.sv - target: test files: - hw/tcdm_interface/src/tcdm_test.sv - target: all(tb, not(verilator)) files: - - hw/tcdm_interface/test/reqrsp_to_tcdm_tb.sv + - hw/tcdm_interface/test/lsu_to_tcdm_intf.sv - hw/tcdm_interface/test/tcdm_mux_tb.sv + - hw/tcdm_interface/test/lsu_to_tcdm_tb.sv # dca_interface - files: @@ -181,6 +167,16 @@ sources: # Level 1 - hw/snitch_fp_ss/src/snitch_fp_ss.sv + # snitch_cc + - files: + # Level 0 + - hw/snitch_cc/src/snitch_cc_pkg.sv + # Level 1 + - hw/snitch_cc/src/snitch_tracer.sv + - hw/snitch_cc/src/snitch_ssr_subsystem.sv + # Level 2 + - hw/snitch_cc/src/snitch_cc.sv + # snitch_cluster - files: # Level 0 @@ -195,7 +191,6 @@ sources: - hw/snitch_cluster/src/snitch_barrier.sv - hw/snitch_cluster/src/snitch_tcdm_interconnect.sv # Level 2 - - hw/snitch_cluster/src/snitch_cc.sv - hw/snitch_cluster/src/snitch_clkdiv2.sv # Level 3 - hw/snitch_cluster/src/snitch_hive.sv diff --git a/Makefile b/Makefile index 83621b18a8..59ff6aa736 100644 --- a/Makefile +++ b/Makefile @@ -11,6 +11,7 @@ ####################### DEBUG ?= OFF # ON to turn on debugging symbols and wave logging +TRACE ?= ON # OFF to turn off trace logging CFG_OVERRIDE ?= # Override default configuration file TECH ?= # [gf12, ihp13] for physical simulation VCD_DUMP ?= 0 # 1 to dump VCD traces @@ -31,7 +32,7 @@ endif .PHONY: all clean all: rtl sw -clean: clean-rtl clean-sw clean-work clean-logs clean-bender clean-misc +clean: clean-rtl clean-sw clean-work clean-logs clean-bender clean-misc clean-toolchain ########## # Common # @@ -126,6 +127,17 @@ $(GENERATED_DOCS_DIR)/peripherals.md: hw/snitch_cluster/src/snitch_cluster_perip $(DOXYGEN_DOCS_DIR): $(DOXYFILE) $(DOXYGEN_INPUTS) doxygen $< +############# +# Toolchain # +############# + +# Toolchain used by both RTL and SW stages +include $(SN_ROOT)/make/toolchain.mk + +.PHONY: toolchain clean-toolchain +toolchain: sn-toolchain +clean-toolchain: sn-clean-toolchain + ####### # RTL # ####### @@ -259,6 +271,24 @@ clean-annotate: sn-clean-annotate clean-perf: sn-clean-perf clean-visual-trace: sn-clean-visual-trace +############ +# IP tests # +############ + +IP_LIST = mem_interface +IP_LIST += tcdm_interface +IP_LIST += snitch_ssr +IP_LIST += snitch_cluster + +IP_TARGETS = $(addprefix test-,$(IP_LIST)) + +.PHONY: test-ips + +test-ips: $(IP_TARGETS) + +$(IP_TARGETS): test-%: + cd hw/$* && ./util/compile.sh && ./util/run_vsim.sh + ############################ # Additional PHONY targets # ############################ diff --git a/cfg/default.json b/cfg/default.json index 9f97c2ff98..265875a970 100644 --- a/cfg/default.json +++ b/cfg/default.json @@ -99,7 +99,7 @@ xfrep: true, xcopift: true, xdma: false, - xf16: true, + zfh: true, xf16alt: true, xf8: true, xf8alt: true, @@ -129,7 +129,7 @@ xssr: false, xfrep: false, xcopift: false, - xf16: false, + zfh: false, xf16alt: false, xf8: false, xf8alt: false, diff --git a/cfg/dma_mchan.json b/cfg/dma_mchan.json index e16197562d..61c892e989 100644 --- a/cfg/dma_mchan.json +++ b/cfg/dma_mchan.json @@ -99,7 +99,7 @@ xfrep: true, xcopift: true, xdma: false, - xf16: true, + zfh: true, xf16alt: true, xf8: true, xf8alt: true, @@ -129,7 +129,7 @@ xssr: false, xfrep: false, xcopift: false, - xf16: false, + zfh: false, xf16alt: false, xf8: false, xf8alt: false, diff --git a/cfg/frep_xl.json b/cfg/frep_xl.json index 5a0a3f446d..28f75e00ef 100644 --- a/cfg/frep_xl.json +++ b/cfg/frep_xl.json @@ -98,7 +98,7 @@ xfrep: true, xcopift: true, xdma: false, - xf16: true, + zfh: true, xf16alt: true, xf8: true, xf8alt: true, @@ -128,7 +128,7 @@ xssr: false, xfrep: false, xcopift: false, - xf16: false, + zfh: false, xf16alt: false, xf8: false, xf8alt: false, diff --git a/cfg/frep_xs.json b/cfg/frep_xs.json index dc53f50a15..ae2b1c18db 100644 --- a/cfg/frep_xs.json +++ b/cfg/frep_xs.json @@ -99,7 +99,7 @@ xfrep: true, xcopift: true, xdma: false, - xf16: true, + zfh: true, xf16alt: true, xf8: true, xf8alt: true, @@ -129,7 +129,7 @@ xssr: false, xfrep: false, xcopift: false, - xf16: false, + zfh: false, xf16alt: false, xf8: false, xf8alt: false, diff --git a/cfg/github-ci.json b/cfg/github-ci.json index 852fe4165a..4881b86a1a 100644 --- a/cfg/github-ci.json +++ b/cfg/github-ci.json @@ -95,7 +95,7 @@ xfrep: true, xcopift: true, xdma: false, - xf16: true, + zfh: true, xf16alt: true, xf8: true, xf8alt: true, @@ -125,7 +125,7 @@ xssr: false, xfrep: false, xcopift: false, - xf16: false, + zfh: false, xf16alt: false, xf8: false, xf8alt: false, diff --git a/cfg/mempool.json b/cfg/mempool.json index b41a4c260a..ca4cee97e7 100644 --- a/cfg/mempool.json +++ b/cfg/mempool.json @@ -100,7 +100,7 @@ xfrep: false, xcopift: false, xdma: false, - xf16: false, + zfh: false, xf16alt: false, xf8: false, xf8alt: false, diff --git a/cfg/omega.json b/cfg/omega.json index e6a49426f8..e94b481dba 100644 --- a/cfg/omega.json +++ b/cfg/omega.json @@ -100,7 +100,7 @@ xfrep: true, xcopift: true, xdma: false, - xf16: true, + zfh: true, xf16alt: true, xf8: true, xf8alt: true, @@ -130,7 +130,7 @@ xssr: false, xfrep: false, xcopift: false, - xf16: false, + zfh: false, xf16alt: false, xf8: false, xf8alt: false, diff --git a/cfg/spatz.json b/cfg/spatz.json new file mode 100644 index 0000000000..d616ee574a --- /dev/null +++ b/cfg/spatz.json @@ -0,0 +1,142 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +{ + cluster: { + cluster_base_addr: 0x10000000, + cluster_base_offset: 0, + cluster_base_hartid: 0, + addr_width: 48, + data_width: 64, + atomic_id_width: 5, + tcdm: { + size: 128, + banks: 32, + }, + cluster_periph_size: 60, // kB + zero_mem_size: 64, // kB + alias_region_enable: true, + dma_data_width: 512, + dma_axi_req_fifo_depth: 24, + dma_req_fifo_depth: 8, + narrow_trans: 4, + wide_trans: 32, + // We don't need Snitch debugging in Occamy + enable_debug: false, + enable_xif: false, + // DCA adaption for Spatz is not yet implemented + enable_dca: false, + // We don't need Snitch (core-internal) virtual memory support + vm_support: false, + // Memory configuration inputs + sram_cfg_expose: true, + sram_cfg_fields: { + ema: 3, + emaw: 2, + emas: 1 + }, + // Timing parameters + timing: { + lat_comp_fp32: 2, + lat_comp_fp64: 3, + lat_comp_fp16: 1, + lat_comp_fp16_alt: 1, + lat_comp_fp8: 1, + lat_comp_fp8_alt: 1, + lat_noncomp: 1, + lat_conv: 2, + lat_sdotp: 3, + fpu_pipe_config: "BEFORE", + narrow_xbar_latency: "CUT_ALL_PORTS", + wide_xbar_latency: "CUT_ALL_PORTS", + // Isolate the core. + register_core_req: true, + register_core_rsp: true, + register_offload_req: true, + register_offload_rsp: true, + register_fpu_req: true, + register_ext_narrow: false, + register_ext_wide: false + }, + hives: [ + // Hive 0 + { + icache: { + size: 16, // total instruction cache size in kByte + ways: 2, // number of ways + cacheline: 512 // word size in bits + }, + cores: [ + { $ref: "#/compute_core_template" }, + { $ref: "#/dma_core_template" }, + ] + } + ] + }, + external_addr_regions: [ + { + name: "dram", + address: 0x80000000, + length: 0x80000000, + cacheable: true + }, + { + name: "clint", + address: 0xFFFF0000, + length: 0x1000 + }, + ], + // Templates. + compute_core_template: { + isa: "rv32imafdv", + xssr: false, + xfrep: false, + xcopift: false, + xdma: false, + zfh: true, + xf16alt: true, + xf8: true, + xf8alt: true, + xfdotp: true, + xfvec: true, + num_int_outstanding_loads: 4, + num_int_outstanding_mem: 4, + num_fp_outstanding_loads: 4, + num_fp_outstanding_mem: 4, + num_dtlb_entries: 1, + num_itlb_entries: 1, + spatz: { + num_outstanding_loads: 4, + n_ipu: 1, + n_fpu: 8, + vlen: 512, + spatz_nports: 8, + double_bw: false, + spatz_fpu: true, + mempool: false, + buf_fpu: 1, + rvf: true, + rvd: true + } + }, + dma_core_template: { + isa: "rv32imafd", + xdma: true, + xssr: false, + xfrep: false, + xcopift: false, + zfh: true, + xf16alt: false, + xf8: false, + xf8alt: false, + xfdotp: false, + xfvec: false, + num_int_outstanding_loads: 4, + num_int_outstanding_mem: 4, + num_fp_outstanding_loads: 4, + num_fp_outstanding_mem: 4, + num_dtlb_entries: 1, + num_itlb_entries: 1, + } +} diff --git a/cfg/yosys-ci.json b/cfg/yosys-ci.json index 8b38172bfd..b514effe49 100644 --- a/cfg/yosys-ci.json +++ b/cfg/yosys-ci.json @@ -93,7 +93,7 @@ xfrep: true, xcopift: true, xdma: false, - xf16: true, + zfh: true, xf16alt: true, xf8: true, xf8alt: true, @@ -123,7 +123,7 @@ xssr: false, xfrep: false, xcopift: false, - xf16: false, + zfh: false, xf16alt: false, xf8: false, xf8alt: false, diff --git a/docs/rm/hw/reqrsp_interface.md b/docs/rm/hw/reqrsp_interface.md deleted file mode 100644 index 76b8191dd1..0000000000 --- a/docs/rm/hw/reqrsp_interface.md +++ /dev/null @@ -1,88 +0,0 @@ -!!! warning - This page is no longer maintained, and may contain outdated information. - -# Reqrsp Interface - -The `reqrsp_interface` (request and response) is a custom interface based on -common principles found in other interconnects such as AXI or TileLink. It has -only two channels (request and response) which are handshaked according to the -AMBA standard: - -- The initiator asserts `valid`. The assertion of `valid` must not depend on - `ready`. -- Once `valid` has been asserted all data must remain stable. -- The receiver asserts `ready` whenever it is ready to receive the transaction. -- When both `valid` and `ready` are high the transaction is successful. - -The bus is little endian. - -## Channels - -The two channels are: - -- Request (`q`): The initiator requests a memory transaction. Supported are - read, write, atomic memory operations, load-linked and store-conditional - pairs. -- Response (`p`): _Every_ transaction which was requested ultimately returns a - response. For reads the response channel returns the read response, for writes - the response acknowledges that the data is committed and subsequent reads will - return the last written value, for atomic operations the data _before_ the - memory operations has happened is being returned. For load-linked the the read - response is returned, for store-conditionals the the success code is returned. - Additionally, the response channel carries error information. - -## Sizes - -Data bus size of 32, 64, 128, 256, 512, 1024-bit are supported. Atomic memory -operations are 32 bit or 64 bit for bus sizes greater than 32. - -## Data Alignment - -The data is always bus-aligned. similar to AXI. For reads the address and size -fields indicate which data is valid. Similarly for writes the address and size -fields in addition to the write strobe field indicate valid bytes (8 bit of -data). Atomics and LR/SCs addresses are always naturally aligned to their size. - -## Ordering - -Transactions on the request channel are always strongly ordered (as if they -would all use the same ID in AXI terms). Reads and writes are ordered with -respect to each other (that needs to be maintained when translating to AXI). - -## Atomic Memory Operations - -Atomic memory operations supported are: - -| Operation | Description | -| ------------------ | ------------------------------------------------------------------------- | -| `Swap` | Swaps the values. | -| `Add` | Signed addition. | -| `And`, `Or`, `Xor` | Bitwise `and`, `or`, and `xor` operation. | -| `Max`, `Maxu` | Signed and unsigned maximum operation. | -| `Min`, `Minu` | Signed and unsigned minimum operation. | -| `Lr` | Places a reservation on the given memory address | -| `Sc` | Conditional store, returns `0` on `q.data` if successful, `1` otherwise. | - - -The operation reads the value at the given address and returns the read value on -the `p` channel. The same memory location is updated with the data and operation -supplied on the `q.amo` and `q.data` signals. The `q.write` signal must be set to `1'b0`. - -## Load-Reserved/Store-conditional - -The `q.amo` field carries the information on whether the transaction encodes an -LR/SC. - -| Operation | Description | -| ------------ | ------------------------------------------------------------------------- | -| Lr | Places a reservation on the given memory address | -| Sc | Conditional store, returns `0` on `q.data` if successful, `1` otherwise. | - -For `Sc` and `LR` the `q.write` signal must be set to `0`. - -## Error - -The `p` channel carries additional error information: - -- `0`: The access is ok. -- `1`: The access has encountered an error. diff --git a/docs/ug/system_integration.md b/docs/ug/system_integration.md index 5d24fb9229..bbea039752 100644 --- a/docs/ug/system_integration.md +++ b/docs/ug/system_integration.md @@ -14,7 +14,7 @@ As you may note, we do not instantiate the `snitch_cluster` directly but a so-ca This file can be programmatically generated from a single source of truth, namely a JSON5 configuration file, from which the software hardware abstraction layer (HAL), and all other sources dependent on the configuration within the repository, are also generated. -This way, if you want to modify the cluster configuration, you don't have to go and manually change it in multiple places (the RTL, the HAL, etc.), but only in the single-source-of-truth cluster configuration file. More information on the configuration file can be found in the [tutorial](tutorial.md#configuring-the-hardware). +This way, if you want to modify the cluster configuration, you don't have to go and manually change it in multiple places (the RTL, the HAL, the toolchain flags, etc.), but only in the single-source-of-truth cluster configuration file. More information on the configuration file can be found in the [tutorial](tutorial.md#configuring-the-hardware). We suggest that the same approach is used when integrating the Snitch cluster in an SoC. This further allows you to easily test different configurations of the cluster inside your SoC. @@ -27,6 +27,7 @@ SN_ROOT = $(shell $(BENDER) path snitch_cluster) # Customization options should precede the following lines include $(SN_ROOT)/make/common.mk +include $(SN_ROOT)/make/toolchain.mk include $(SN_ROOT)/make/rtl.mk ``` @@ -38,6 +39,9 @@ You can then use the `sn-rtl` and `sn-clean-rtl` targets to respectively build a !!! note The `common.mk` fragment is required by all of the make fragments presented in the subsequent sections, so it must included before the others. +!!! note + The `toolchain.mk` fragment is required to build the bootrom, one of the RTL sources generated by `rtl.mk`. Like `common.mk`, it is needed also by several other Make fragments. + The included Makefiles can be customized to some extent by overriding some variables before the Makefile inclusion lines. By default, the build directories of all auto-generated sources live in the Snitch cluster repo. If you are simultaneously working on the Snitch cluster and your derived system repos, it may be beneficial to have separate build directories for your artifacts, to avoid having to regenerate the sources for the right target every time you switch between the two. @@ -60,6 +64,8 @@ sources: - /snitch_cluster_wrapper_pkg.sv ``` +The `override_files` entry is required to ensure that Bender resolves the correct compilation order: the system-specific `snitch_cluster_wrapper_pkg.sv` file has to be compiled before Snitch's `snitch_cluster_wrapper.sv` file. + ## Integrating the software The Snitch cluster repo comes with a collection of software tests and kernels. diff --git a/hw/dca_interface/include/dca_interface/assign.svh b/hw/dca_interface/include/dca_interface/assign.svh deleted file mode 100644 index d89398b384..0000000000 --- a/hw/dca_interface/include/dca_interface/assign.svh +++ /dev/null @@ -1,27 +0,0 @@ -// Copyright 2025 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Author: Luca Colagrande - -`ifndef DCA_INTERFACE_ASSIGN_SVH_ -`define DCA_INTERFACE_ASSIGN_SVH_ - -`define DCA_REQRSP_ASSIGN_REQ(__opt_as, dst, src) \ - __opt_as dst.q_valid = src.q_valid; \ - __opt_as dst.p_ready = src.p_ready; \ - __opt_as dst.q.operands = src.q.operands; \ - __opt_as dst.q.rnd_mode = src.q.rnd_mode; \ - __opt_as dst.q.op = src.q.op; \ - __opt_as dst.q.op_mod = src.q.op_mod; \ - __opt_as dst.q.src_fmt = src.q.src_fmt; \ - __opt_as dst.q.dst_fmt = src.q.dst_fmt; \ - __opt_as dst.q.int_fmt = src.q.int_fmt; \ - __opt_as dst.q.vectorial_op = src.q.vectorial_op; -`define DCA_REQRSP_ASSIGN_RSP(__opt_as, dst, src) \ - __opt_as dst.p_valid = src.p_valid; \ - __opt_as dst.q_ready = src.q_ready; \ - __opt_as dst.p.status = src.p.status; \ - __opt_as dst.p.result = src.p.result; - -`endif // DCA_INTERFACE_ASSIGN_SVH_ diff --git a/hw/dca_interface/include/dca_interface/typedef.svh b/hw/dca_interface/include/dca_interface/typedef.svh index 4f4617e00e..8ed7f62af9 100644 --- a/hw/dca_interface/include/dca_interface/typedef.svh +++ b/hw/dca_interface/include/dca_interface/typedef.svh @@ -28,10 +28,10 @@ } `define DCA_REQ_STRUCT(__data_width) \ - `GENERIC_REQRSP_REQ_STRUCT(`DCA_REQ_CHAN_STRUCT(__data_width)) + `REQRSP_REQ_STRUCT(`DCA_REQ_CHAN_STRUCT(__data_width)) `define DCA_RSP_STRUCT(__data_width) \ - `GENERIC_REQRSP_RSP_STRUCT(`DCA_RSP_CHAN_STRUCT(__data_width)) + `REQRSP_RSP_STRUCT(`DCA_RSP_CHAN_STRUCT(__data_width)) `define DCA_TYPEDEF_REQ_CHAN_T(__name, __data_width) \ typedef `DCA_REQ_CHAN_STRUCT(__data_width) __name``_req_chan_t; @@ -45,6 +45,6 @@ `define DCA_TYPEDEF_ALL(__name, __data_width) \ `DCA_TYPEDEF_REQRSP_CHAN_ALL(__name, __data_width) \ - `GENERIC_REQRSP_TYPEDEF_ALL(__name, __name``_req_chan_t, __name``_rsp_chan_t) + `REQRSP_TYPEDEF_ALL(__name, __name``_req_chan_t, __name``_rsp_chan_t) `endif // DCA_INTERFACE_TYPEDEF_SVH_ diff --git a/hw/generated/snitch_cluster_wrapper_pkg.sv b/hw/generated/snitch_cluster_wrapper_pkg.sv index fcd9be8508..3f2846cb73 100644 --- a/hw/generated/snitch_cluster_wrapper_pkg.sv +++ b/hw/generated/snitch_cluster_wrapper_pkg.sv @@ -15,6 +15,7 @@ + `include "axi/typedef.svh" `include "tcdm_interface/typedef.svh" `include "dca_interface/typedef.svh" @@ -1022,11 +1023,12 @@ package snitch_cluster_wrapper_pkg; RVE: 0, RVF: 1, RVD: 1, + RVV: 0, Xdma: 0, Xssr: 1, Xfrep: 1, Xcopift: 1, - XF16: 1, + Zfh: 1, XF16ALT: 1, XF8: 1, XF8ALT: 1, @@ -1050,11 +1052,12 @@ package snitch_cluster_wrapper_pkg; RVE: 0, RVF: 1, RVD: 1, + RVV: 0, Xdma: 0, Xssr: 1, Xfrep: 1, Xcopift: 1, - XF16: 1, + Zfh: 1, XF16ALT: 1, XF8: 1, XF8ALT: 1, @@ -1078,11 +1081,12 @@ package snitch_cluster_wrapper_pkg; RVE: 0, RVF: 1, RVD: 1, + RVV: 0, Xdma: 0, Xssr: 1, Xfrep: 1, Xcopift: 1, - XF16: 1, + Zfh: 1, XF16ALT: 1, XF8: 1, XF8ALT: 1, @@ -1106,11 +1110,12 @@ package snitch_cluster_wrapper_pkg; RVE: 0, RVF: 1, RVD: 1, + RVV: 0, Xdma: 0, Xssr: 1, Xfrep: 1, Xcopift: 1, - XF16: 1, + Zfh: 1, XF16ALT: 1, XF8: 1, XF8ALT: 1, @@ -1134,11 +1139,12 @@ package snitch_cluster_wrapper_pkg; RVE: 0, RVF: 1, RVD: 1, + RVV: 0, Xdma: 0, Xssr: 1, Xfrep: 1, Xcopift: 1, - XF16: 1, + Zfh: 1, XF16ALT: 1, XF8: 1, XF8ALT: 1, @@ -1162,11 +1168,12 @@ package snitch_cluster_wrapper_pkg; RVE: 0, RVF: 1, RVD: 1, + RVV: 0, Xdma: 0, Xssr: 1, Xfrep: 1, Xcopift: 1, - XF16: 1, + Zfh: 1, XF16ALT: 1, XF8: 1, XF8ALT: 1, @@ -1190,11 +1197,12 @@ package snitch_cluster_wrapper_pkg; RVE: 0, RVF: 1, RVD: 1, + RVV: 0, Xdma: 0, Xssr: 1, Xfrep: 1, Xcopift: 1, - XF16: 1, + Zfh: 1, XF16ALT: 1, XF8: 1, XF8ALT: 1, @@ -1218,11 +1226,12 @@ package snitch_cluster_wrapper_pkg; RVE: 0, RVF: 1, RVD: 1, + RVV: 0, Xdma: 0, Xssr: 1, Xfrep: 1, Xcopift: 1, - XF16: 1, + Zfh: 1, XF16ALT: 1, XF8: 1, XF8ALT: 1, @@ -1246,11 +1255,12 @@ package snitch_cluster_wrapper_pkg; RVE: 0, RVF: 1, RVD: 1, + RVV: 0, Xdma: 1, Xssr: 0, Xfrep: 0, Xcopift: 0, - XF16: 0, + Zfh: 0, XF16ALT: 0, XF8: 0, XF8ALT: 0, @@ -1315,7 +1325,7 @@ package snitch_cluster_wrapper_pkg; }; // Forward potentially optional configuration parameters - localparam snitch_cluster_pkg::hart_id_t CfgBaseHartId = (32'h0); + localparam snitch_pkg::hart_id_t CfgBaseHartId = (32'h0); localparam addr_t CfgClusterBaseAddr = (48'h10000000); localparam addr_t CfgClusterBaseOffset = (48'h0); @@ -1374,16 +1384,18 @@ package snitch_cluster_wrapper_pkg; localparam bit NarrowAxiPortExpose = 0; // Per-core localparam arrays - localparam int unsigned NumIntOutstandingLoads [NrCores] = '{4, 4, 4, 4, 4, 4, 4, 4, 4}; - localparam int unsigned NumIntOutstandingMem [NrCores] = '{4, 4, 4, 4, 4, 4, 4, 4, 4}; - localparam int unsigned NumFPOutstandingLoads [NrCores] = '{4, 4, 4, 4, 4, 4, 4, 4, 4}; - localparam int unsigned NumFPOutstandingMem [NrCores] = '{4, 4, 4, 4, 4, 4, 4, 4, 4}; - localparam int unsigned NumDTLBEntries [NrCores] = '{1, 1, 1, 1, 1, 1, 1, 1, 1}; - localparam int unsigned NumITLBEntries [NrCores] = '{1, 1, 1, 1, 1, 1, 1, 1, 1}; - localparam int unsigned NumSequencerInstr [NrCores] = '{32, 32, 32, 32, 32, 32, 32, 32, 16}; - localparam int unsigned NumSequencerLoops [NrCores] = '{2, 2, 2, 2, 2, 2, 2, 2, 1}; - localparam int unsigned NumSsrs [NrCores] = '{3, 3, 3, 3, 3, 3, 3, 3, 1}; - localparam int unsigned SsrMuxRespDepth [NrCores] = '{4, 4, 4, 4, 4, 4, 4, 4, 4}; + localparam int unsigned NumIntOutstandingLoads [NrCores] = '{4, 4, 4, 4, 4, 4, 4, 4, 4}; + localparam int unsigned NumIntOutstandingMem [NrCores] = '{4, 4, 4, 4, 4, 4, 4, 4, 4}; + localparam int unsigned NumFPOutstandingLoads [NrCores] = '{4, 4, 4, 4, 4, 4, 4, 4, 4}; + localparam int unsigned NumFPOutstandingMem [NrCores] = '{4, 4, 4, 4, 4, 4, 4, 4, 4}; + localparam int unsigned NumDTLBEntries [NrCores] = '{1, 1, 1, 1, 1, 1, 1, 1, 1}; + localparam int unsigned NumITLBEntries [NrCores] = '{1, 1, 1, 1, 1, 1, 1, 1, 1}; + localparam int unsigned NumSequencerInstr [NrCores] = '{32, 32, 32, 32, 32, 32, 32, 32, 16}; + localparam int unsigned NumSequencerLoops [NrCores] = '{2, 2, 2, 2, 2, 2, 2, 2, 1}; + localparam int unsigned NumSsrs [NrCores] = '{3, 3, 3, 3, 3, 3, 3, 3, 1}; + localparam int unsigned SsrMuxRspDepth [NrCores] = '{4, 4, 4, 4, 4, 4, 4, 4, 4}; + localparam bit SpatzDoubleBw [NrCores] = '{0, 0, 0, 0, 0, 0, 0, 0, 0}; + localparam int unsigned NumSpatzOutstandingLoads [NrCores] = '{1, 1, 1, 1, 1, 1, 1, 1, 1}; endpackage // verilog_lint: waive-stop package-filename diff --git a/hw/mem_interface/include/mem_interface/assign.svh b/hw/mem_interface/include/mem_interface/assign.svh index 45122712e3..7cab40f383 100644 --- a/hw/mem_interface/include/mem_interface/assign.svh +++ b/hw/mem_interface/include/mem_interface/assign.svh @@ -54,9 +54,9 @@ // The request macro `MEM_ASSIGN_FROM_REQ(MEM_if, req_struct)` assigns the // request channel and the request-side handshake signals of the `MEM_if` // interface from the signals in `req_struct`. The response macro -// `MEM_ASSIGN_FROM_RESP(MEM_if, resp_struct)` assigns the response +// `MEM_ASSIGN_FROM_RSP(MEM_if, rsp_struct)` assigns the response // channel and the response-side handshake signals of the `MEM_if` interface -// from the signals in `resp_struct`. +// from the signals in `rsp_struct`. // // Usage Example: // `MEM_ASSIGN_FROM_REQ(my_if, my_req_struct) @@ -64,9 +64,9 @@ `MEM_ASSIGN_VALID(assign, MEM_if, req_struct, q) \ `MEM_ASSIGN_Q_CHAN(assign, MEM_if, req_struct, _, .) -`define MEM_ASSIGN_FROM_RESP(MEM_if, resp_struct) \ - `MEM_ASSIGN_READY(assign, MEM_if, resp_struct, q) \ - `MEM_ASSIGN_P_CHAN(assign, MEM_if, resp_struct, _, .) +`define MEM_ASSIGN_FROM_RSP(MEM_if, rsp_struct) \ + `MEM_ASSIGN_READY(assign, MEM_if, rsp_struct, q) \ + `MEM_ASSIGN_P_CHAN(assign, MEM_if, rsp_struct, _, .) //////////////////////////////////////////////////////////////////////////////////////////////////// @@ -74,11 +74,11 @@ // Assigning channel or request/response structs from an interface outside a // process. // -// The request macro `MEM_ASSIGN_TO_REQ(MEM_if, req_struct)` assigns all +// The request macro `MEM_ASSIGN_TO_REQ(req_struct, MEM_if)` assigns all // signals of `req_struct` payload and request-side handshake signals to the // signals in the `MEM_if` interface. The response macro -// `MEM_ASSIGN_TO_RESP(MEM_if, resp_struct)` assigns all signals of -// `resp_struct` payload and response-side handshake signals to the signals in +// `MEM_ASSIGN_TO_RSP(rsp_struct, MEM_if)` assigns all signals of +// `rsp_struct` payload and response-side handshake signals to the signals in // the `MEM_if` interface. // // Usage Example: @@ -87,9 +87,9 @@ `MEM_ASSIGN_VALID(assign, req_struct, MEM_if, q) \ `MEM_ASSIGN_Q_CHAN(assign, req_struct, MEM_if, ., _) -`define MEM_ASSIGN_TO_RESP(resp_struct, MEM_if) \ - `MEM_ASSIGN_READY(assign, resp_struct, MEM_if, q) \ - `MEM_ASSIGN_P_CHAN(assign, resp_struct, MEM_if, ., _) +`define MEM_ASSIGN_TO_RSP(rsp_struct, MEM_if) \ + `MEM_ASSIGN_READY(assign, rsp_struct, MEM_if, q) \ + `MEM_ASSIGN_P_CHAN(assign, rsp_struct, MEM_if, ., _) //////////////////////////////////////////////////////////////////////////////////////////////////// `endif diff --git a/hw/mem_interface/include/mem_interface/typedef.svh b/hw/mem_interface/include/mem_interface/typedef.svh index 71f39cc39f..4f90d3ae17 100644 --- a/hw/mem_interface/include/mem_interface/typedef.svh +++ b/hw/mem_interface/include/mem_interface/typedef.svh @@ -12,7 +12,7 @@ typedef struct packed { \ __addr_t addr; \ logic write; \ - snitch_pkg::amo_op_e amo; \ + lsu_pkg::amo_op_e amo; \ __data_t data; \ __strb_t strb; \ __user_t user; \ diff --git a/hw/mem_interface/src/mem_interface.sv b/hw/mem_interface/src/mem_interface.sv index 8fd93ac33a..43e34a7a22 100644 --- a/hw/mem_interface/src/mem_interface.sv +++ b/hw/mem_interface/src/mem_interface.sv @@ -15,7 +15,7 @@ interface MEM_BUS #( parameter type user_t = logic ); - import snitch_pkg::*; + import lsu_pkg::*; localparam int unsigned StrbWidth = DATA_WIDTH / 8; @@ -65,7 +65,7 @@ interface MEM_BUS_DV #( input logic clk_i ); - import snitch_pkg::*; + import lsu_pkg::*; localparam int unsigned StrbWidth = DATA_WIDTH / 8; diff --git a/hw/mem_interface/src/mem_test.sv b/hw/mem_interface/src/mem_test.sv index 4d897bf795..7ce4490430 100644 --- a/hw/mem_interface/src/mem_test.sv +++ b/hw/mem_interface/src/mem_test.sv @@ -12,7 +12,7 @@ package mem_test; ); rand logic [AW-1:0] addr; rand logic write; - rand snitch_pkg::amo_op_e amo; + rand lsu_pkg::amo_op_e amo; rand logic [DW-1:0] data; rand logic [DW/8-1:0] strb; rand user_t user; @@ -21,31 +21,31 @@ package mem_test; constraint legal_amo_op_c { amo inside { - snitch_pkg::AMOSwap, - snitch_pkg::AMOAdd, - snitch_pkg::AMOAnd, - snitch_pkg::AMOOr, - snitch_pkg::AMOXor, - snitch_pkg::AMOMax, - snitch_pkg::AMOMaxu, - snitch_pkg::AMOMin, - snitch_pkg::AMOMinu, - snitch_pkg::AMOSC} -> write == 1; + lsu_pkg::AMOSwap, + lsu_pkg::AMOAdd, + lsu_pkg::AMOAnd, + lsu_pkg::AMOOr, + lsu_pkg::AMOXor, + lsu_pkg::AMOMax, + lsu_pkg::AMOMaxu, + lsu_pkg::AMOMin, + lsu_pkg::AMOMinu, + lsu_pkg::AMOSC} -> write == 1; } // Reduce the amount of atomics. constraint amo_reduce_c { is_amo dist { 1:= 1, 0:= 10}; is_amo -> amo inside { - snitch_pkg::AMOSwap, - snitch_pkg::AMOAdd, - snitch_pkg::AMOAnd, - snitch_pkg::AMOOr, - snitch_pkg::AMOXor, - snitch_pkg::AMOMax, - snitch_pkg::AMOMaxu, - snitch_pkg::AMOMin, - snitch_pkg::AMOMinu + lsu_pkg::AMOSwap, + lsu_pkg::AMOAdd, + lsu_pkg::AMOAnd, + lsu_pkg::AMOOr, + lsu_pkg::AMOXor, + lsu_pkg::AMOMax, + lsu_pkg::AMOMaxu, + lsu_pkg::AMOMin, + lsu_pkg::AMOMinu }; } @@ -104,7 +104,7 @@ package mem_test; task reset_master; bus.q_addr <= '0; bus.q_write <= '0; - bus.q_amo <= snitch_pkg::AMONone; + bus.q_amo <= lsu_pkg::AMONone; bus.q_data <= '0; bus.q_strb <= '0; bus.q_user <= '0; diff --git a/hw/mem_interface/src/mem_wide_narrow_mux.sv b/hw/mem_interface/src/mem_wide_narrow_mux.sv index ef26f69518..c5f8444542 100644 --- a/hw/mem_interface/src/mem_wide_narrow_mux.sv +++ b/hw/mem_interface/src/mem_wide_narrow_mux.sv @@ -94,7 +94,7 @@ module mem_wide_narrow_mux #( out_req_o[i].q = '{ addr: in_wide_req_i.q.addr, write: in_wide_req_i.q.write, - amo: snitch_pkg::AMONone, + amo: lsu_pkg::AMONone, data: in_wide_req_i.q.data[i*NarrowDataWidth+:NarrowDataWidth], strb: in_wide_req_i.q.strb[i*NarrowStrbWidth+:NarrowStrbWidth], user: in_wide_req_i.q.user @@ -111,7 +111,7 @@ module mem_wide_narrow_mux #( out_req_o[i].q = '{ addr: in_ext_req_i.q.addr, write: in_ext_req_i.q.write, - amo: snitch_pkg::AMONone, + amo: lsu_pkg::AMONone, data: in_ext_req_i.q.data[i*NarrowDataWidth+:NarrowDataWidth], strb: in_ext_req_i.q.strb[i*NarrowStrbWidth+:NarrowStrbWidth], user: in_ext_req_i.q.user @@ -225,15 +225,15 @@ module mem_wide_narrow_mux_intf #( for (genvar i = 0; i < NrPorts; i++) begin : gen_interface_assign `MEM_ASSIGN_TO_REQ(in_narrow_req[i], in_narrow[i]) - `MEM_ASSIGN_FROM_RESP(in_narrow[i], in_narrow_rsp[i]) + `MEM_ASSIGN_FROM_RSP(in_narrow[i], in_narrow_rsp[i]) `MEM_ASSIGN_FROM_REQ(out[i], out_req[i]) - `MEM_ASSIGN_TO_RESP(out_rsp[i], out[i]) + `MEM_ASSIGN_TO_RSP(out_rsp[i], out[i]) end `MEM_ASSIGN_TO_REQ(in_wide_req, in_wide) - `MEM_ASSIGN_FROM_RESP(in_wide, in_wide_rsp) + `MEM_ASSIGN_FROM_RSP(in_wide, in_wide_rsp) `MEM_ASSIGN_TO_REQ(in_ext_req, in_ext) - `MEM_ASSIGN_FROM_RESP(in_ext, in_ext_rsp) + `MEM_ASSIGN_FROM_RSP(in_ext, in_ext_rsp) endmodule diff --git a/hw/reqrsp_interface/README.md b/hw/reqrsp_interface/README.md deleted file mode 100644 index 1086fc5cb1..0000000000 --- a/hw/reqrsp_interface/README.md +++ /dev/null @@ -1,21 +0,0 @@ -# Reqrsp Interface - -A simple interface with a single request channel and a single response channel, -for both read and write data. A more thorough documentation can be found in the -[docs](doc/index.md) folder. - -## List of Modules - -| Name | Description | Status | -| ---------------- | ---------------------------------------------------------------------------- | ---------- | -| `axi_to_reqrsp` | Protocol translator between `reqrsp` and AXI4+ATOP | active | -| `reqrsp_cut` | Insert registers (i.e., a pipeline stage) into request and/or response path. | active | -| `reqrsp_demux` | Demultiplex, based on a select signal. | active | -| `reqrsp_intf` | Systemverilog interface definition of `reqrsp` interface. | active | -| `reqrsp_iso` | Isochronous clockdomain crossing. | active | -| `reqrsp_mux` | Arbitrate multiple ports based on round-robin arbitration. | active | -| `reqrsp_test` | Common test infrastructure for the `reqrsp` protocol. | active | -| `reqrsp_to_axi` | Protocol translator between AXI4+ATOP and `reqrsp`. | active | -| `reqrsp_to_tcdm` | Protocol translator between `reqrsp` and `tcdm` protocol. | _untested_ | - - diff --git a/hw/reqrsp_interface/include/reqrsp_interface/assign.svh b/hw/reqrsp_interface/include/reqrsp_interface/assign.svh deleted file mode 100644 index b363c26aaa..0000000000 --- a/hw/reqrsp_interface/include/reqrsp_interface/assign.svh +++ /dev/null @@ -1,112 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Author: Florian Zaruba -// Author: Fabian Schuiki -// Author: Luca Colagrande - -// Macros to assign reqrsp Interfaces and Structs - -`ifndef REQRSP_ASSIGN_SVH_ -`define REQRSP_ASSIGN_SVH_ - -// Tie off a generic reqrsp-like interface -`define REQRSP_TIE_OFF_REQ(__if) \ - assign ``__if``.q = '0; \ - assign ``__if``.q_valid = 1'b0; \ - assign ``__if``.p_ready = 1'b0; -`define REQRSP_TIE_OFF_RSP(__if) \ - assign ``__if``.p = '0; \ - assign ``__if``.p_valid = 1'b0; \ - assign ``__if``.q_ready = 1'b0; - -// Assign an reqrsp handshake. -`define REQRSP_ASSIGN_VALID(__opt_as, __dst, __src, __chan) \ - __opt_as ``__dst``.``__chan``_valid = ``__src``.``__chan``_valid; -`define REQRSP_ASSIGN_READY(__opt_as, __dst, __src, __chan) \ - __opt_as ``__dst``.``__chan``_ready = ``__src``.``__chan``_ready; - -`define REQRSP_ASSIGN_HANDSHAKE(__opt_as, __dst, __src, __chan) \ - `REQRSP_ASSIGN_VALID(__opt_as, __dst, __src, __chan) \ - `REQRSP_ASSIGN_READY(__opt_as, __src, __dst, __chan) - -//////////////////////////////////////////////////////////////////////////////////////////////////// -// Assigning one REQRSP interface to another, as if you would do `assign slv = -// mst;` -// -// The channel assignments `REQRSP_ASSIGN_XX(dst, src)` assign all payload and -// the valid signal of the `XX` channel from the `src` to the `dst` interface -// and they assign the ready signal from the `src` to the `dst` interface. The -// interface assignment `REQRSP_ASSIGN(dst, src)` assigns all channels including -// handshakes as if `src` was the master of `dst`. -// -// Usage Example: `REQRSP_ASSIGN(slv, mst) `REQRSP_ASSIGN_Q(dst, src, aw) -// `REQRSP_ASSIGN_P(dst, src) -`define REQRSP_ASSIGN_Q_CHAN(__opt_as, dst, src, __sep_dst, __sep_src) \ - __opt_as dst.q``__sep_dst``addr = src.q``__sep_src``addr; \ - __opt_as dst.q``__sep_dst``write = src.q``__sep_src``write; \ - __opt_as dst.q``__sep_dst``amo = src.q``__sep_src``amo; \ - __opt_as dst.q``__sep_dst``data = src.q``__sep_src``data; \ - __opt_as dst.q``__sep_dst``strb = src.q``__sep_src``strb; \ - __opt_as dst.q``__sep_dst``size = src.q``__sep_src``size; -`define REQRSP_ASSIGN_P_CHAN(__opt_as, dst, src, __sep_dst, __sep_src) \ - __opt_as dst.p``__sep_dst``data = src.p``__sep_src``data; \ - __opt_as dst.p``__sep_dst``error = src.p``__sep_src``error; -`define REQRSP_ASSIGN(slv, mst) \ - `REQRSP_ASSIGN_Q_CHAN(assign, slv, mst, _, _) \ - `REQRSP_ASSIGN_HANDSHAKE(assign, slv, mst, q) \ - `REQRSP_ASSIGN_P_CHAN(assign, mst, slv, _, _) \ - `REQRSP_ASSIGN_HANDSHAKE(assign, mst, slv, p) -//////////////////////////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////////////////////////// -// Assigning an interface from channel or request/response structs outside a -// process. -// -// The request macro `REQRSP_ASSIGN_FROM_REQ(reqrsp_if, req_struct)` assigns the -// request channel and the request-side handshake signals of the `reqrsp_if` -// interface from the signals in `req_struct`. The response macro -// `REQRSP_ASSIGN_FROM_RESP(reqrsp_if, resp_struct)` assigns the response -// channel and the response-side handshake signals of the `reqrsp_if` interface -// from the signals in `resp_struct`. -// -// Usage Example: -// `REQRSP_ASSIGN_FROM_REQ(my_if, my_req_struct) -`define REQRSP_ASSIGN_FROM_REQ(reqrsp_if, req_struct) \ - `REQRSP_ASSIGN_VALID(assign, reqrsp_if, req_struct, q) \ - `REQRSP_ASSIGN_Q_CHAN(assign, reqrsp_if, req_struct, _, .) \ - `REQRSP_ASSIGN_READY(assign, reqrsp_if, req_struct, p) - -`define REQRSP_ASSIGN_FROM_RESP(reqrsp_if, resp_struct) \ - `REQRSP_ASSIGN_READY(assign, reqrsp_if, resp_struct, q) \ - `REQRSP_ASSIGN_P_CHAN(assign, reqrsp_if, resp_struct, _, .) \ - `REQRSP_ASSIGN_VALID(assign, reqrsp_if, resp_struct, p) - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////////////////////////// -// Assigning channel or request/response structs from an interface outside a -// process. -// -// The request macro `REQRSP_ASSIGN_TO_REQ(reqrsp_if, req_struct)` assigns all -// signals of `req_struct` payload and request-side handshake signals to the -// signals in the `reqrsp_if` interface. The response macro -// `REQRSP_ASSIGN_TO_RESP(reqrsp_if, resp_struct)` assigns all signals of -// `resp_struct` payload and response-side handshake signals to the signals in -// the `reqrsp_if` interface. -// -// Usage Example: -// `REQRSP_ASSIGN_TO_REQ(my_req_struct, my_if) -`define REQRSP_ASSIGN_TO_REQ(req_struct, reqrsp_if) \ - `REQRSP_ASSIGN_VALID(assign, req_struct, reqrsp_if, q) \ - `REQRSP_ASSIGN_Q_CHAN(assign, req_struct, reqrsp_if, ., _) \ - `REQRSP_ASSIGN_READY(assign, req_struct, reqrsp_if, p) - -`define REQRSP_ASSIGN_TO_RESP(resp_struct, reqrsp_if) \ - `REQRSP_ASSIGN_READY(assign, resp_struct, reqrsp_if, q) \ - `REQRSP_ASSIGN_P_CHAN(assign, resp_struct, reqrsp_if, ., _) \ - `REQRSP_ASSIGN_VALID(assign, resp_struct, reqrsp_if, p) -//////////////////////////////////////////////////////////////////////////////////////////////////// - -`endif diff --git a/hw/reqrsp_interface/include/reqrsp_interface/typedef.svh b/hw/reqrsp_interface/include/reqrsp_interface/typedef.svh deleted file mode 100644 index 1b9b2e0293..0000000000 --- a/hw/reqrsp_interface/include/reqrsp_interface/typedef.svh +++ /dev/null @@ -1,58 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Author: Florian Zaruba -// Author: Fabian Schuiki - -`ifndef REQRSP_INTERFACE_TYPEDEF_SVH_ -`define REQRSP_INTERFACE_TYPEDEF_SVH_ - -`define REQRSP_TYPEDEF_REQ_CHAN_T(__req_chan_t, __addr_t, __data_t, __strb_t, __user_t) \ - typedef struct packed { \ - __addr_t addr; \ - logic write; \ - snitch_pkg::amo_op_e amo; \ - __data_t data; \ - __strb_t strb; \ - __user_t user; \ - snitch_pkg::size_t size; \ - } __req_chan_t; - -`define REQRSP_TYPEDEF_RSP_CHAN_T(__rsp_chan_t, __data_t) \ - typedef struct packed { \ - __data_t data; \ - logic error; \ - } __rsp_chan_t; - -`define GENERIC_REQRSP_REQ_STRUCT(__req_chan_t) \ - struct packed { \ - __req_chan_t q; \ - logic q_valid; \ - logic p_ready; \ - } - -`define GENERIC_REQRSP_RSP_STRUCT(__rsp_chan_t) \ - struct packed { \ - __rsp_chan_t p; \ - logic p_valid; \ - logic q_ready; \ - } - -`define REQRSP_TYPEDEF_REQ_T(__req_t, __req_chan_t) \ - typedef `GENERIC_REQRSP_REQ_STRUCT(__req_chan_t) __req_t; - -`define REQRSP_TYPEDEF_RSP_T(__rsp_t, __rsp_chan_t) \ - typedef `GENERIC_REQRSP_RSP_STRUCT(__rsp_chan_t) __rsp_t; - -`define REQRSP_TYPEDEF_ALL(__name, __addr_t, __data_t, __strb_t, __user_t) \ - `REQRSP_TYPEDEF_REQ_CHAN_T(__name``_req_chan_t, __addr_t, __data_t, __strb_t, __user_t) \ - `REQRSP_TYPEDEF_RSP_CHAN_T(__name``_rsp_chan_t, __data_t) \ - `REQRSP_TYPEDEF_REQ_T(__name``_req_t, __name``_req_chan_t) \ - `REQRSP_TYPEDEF_RSP_T(__name``_rsp_t, __name``_rsp_chan_t) - -`define GENERIC_REQRSP_TYPEDEF_ALL(__name, __req_chan_t, __rsp_chan_t) \ - `REQRSP_TYPEDEF_REQ_T(__name``_req_t, __req_chan_t) \ - `REQRSP_TYPEDEF_RSP_T(__name``_rsp_t, __rsp_chan_t) - -`endif diff --git a/hw/reqrsp_interface/src/axi_to_reqrsp.sv b/hw/reqrsp_interface/src/axi_to_reqrsp.sv deleted file mode 100644 index 9734d6d18e..0000000000 --- a/hw/reqrsp_interface/src/axi_to_reqrsp.sv +++ /dev/null @@ -1,495 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Authors: -// - Florian Zaruba -// - Andreas Kurth -// - Wolfgang Roenninger - -`include "common_cells/registers.svh" -`include "common_cells/assertions.svh" - -/// AXI4+ATOP slave module which translates AXI bursts to reqrsp. This module -/// fully supports the Atomic + LR/SC semantic of the reqrsp interface. -/// -/// ## Complexity -/// -/// The complexity of the module increases lineraly with `BufDepth` as all -/// requests need to be saved for proper response routing and error condition -/// generation. -/// -/// ## Note -/// -/// > This work is largely (99.5%) based on `axi_to_mem` found in the AXI -/// > repository. Eventually these two modules can be merged (translating from AXI -/// > to reqrsp to mem). -module axi_to_reqrsp #( - /// AXI4+ATOP request type. See `include/axi/typedef.svh`. - parameter type axi_req_t = logic, - /// AXI4+ATOP response type. See `include/axi/typedef.svh`. - parameter type axi_rsp_t = logic, - /// Address width, has to be less or equal than the width off the AXI address - /// field. Determines the width of `mem_addr_o`. Has to be wide enough to emit - /// the memory region which should be accessible. - parameter int unsigned AddrWidth = 0, - parameter int unsigned DataWidth = 0, - /// AXI4+ATOP ID width. - parameter int unsigned IdWidth = 0, - /// Depth of memory response buffer. This should be equal to the downstream - /// response latency. - parameter int unsigned BufDepth = 1, - /// Reqrsp request channel type. - parameter type reqrsp_req_t = logic, - /// Reqrsp response channel type. - parameter type reqrsp_rsp_t = logic -) ( - /// Clock input. - input logic clk_i, - /// Asynchronous reset, active low. - input logic rst_ni, - /// The unit is busy handling an AXI4+ATOP request. - output logic busy_o, - /// AXI4+ATOP slave port, request input. - input axi_req_t axi_req_i, - /// AXI4+ATOP slave port, response output. - output axi_rsp_t axi_rsp_o, - /// Reqrsp request channel. - output reqrsp_req_t reqrsp_req_o, - /// Reqrsp respone channel. - input reqrsp_rsp_t reqrsp_rsp_i -); - - localparam int unsigned StrbWidth = DataWidth/8; - - typedef logic [AddrWidth-1:0] addr_t; - typedef logic [DataWidth-1:0] data_t; - typedef logic [IdWidth-1:0] axi_id_t; - - typedef struct packed { - addr_t addr; - axi_pkg::atop_t atop; - axi_id_t id; - logic last; - axi_pkg::qos_t qos; - axi_pkg::size_t size; - logic write; - logic lock; - } meta_t; - - snitch_pkg::amo_op_e amo; - data_t data; - axi_pkg::resp_t resp; - axi_pkg::len_t r_cnt_d, r_cnt_q, - w_cnt_d, w_cnt_q; - logic arb_valid, arb_ready, - rd_valid, rd_ready, - wr_valid, wr_ready, - sel_b, sel_buf_b, - sel_r, sel_buf_r, - sel_valid, sel_ready, - sel_buf_valid, sel_buf_ready, - sel_lock_d, sel_lock_q, - meta_valid, meta_ready, - meta_buf_valid, meta_buf_ready, - meta_sel_d, meta_sel_q; - meta_t rd_meta, - rd_meta_d, rd_meta_q, - wr_meta, - wr_meta_d, wr_meta_q, - meta, meta_buf; - - assign busy_o = axi_req_i.aw_valid | axi_req_i.ar_valid | axi_req_i.w_valid | - axi_rsp_o.b_valid | axi_rsp_o.r_valid | - (r_cnt_q > 0) | (w_cnt_q > 0); - - // Handle reads. - always_comb begin - // Default assignments - axi_rsp_o.ar_ready = 1'b0; - rd_meta_d = rd_meta_q; - rd_meta = '{default: '0}; - rd_valid = 1'b0; - r_cnt_d = r_cnt_q; - // Handle R burst in progress. - if (r_cnt_q > '0) begin - rd_meta_d.last = (r_cnt_q == 8'd1); - rd_meta = rd_meta_d; - rd_meta.addr = rd_meta_q.addr + axi_pkg::num_bytes(rd_meta_q.size); - rd_valid = 1'b1; - if (rd_ready) begin - r_cnt_d--; - rd_meta_d.addr = rd_meta.addr; - end - // Handle new AR if there is one. - end else if (axi_req_i.ar_valid) begin - rd_meta_d = '{ - addr: addr_t'(axi_pkg::aligned_addr(axi_pkg::largest_addr_t'(axi_req_i.ar.addr), axi_req_i.ar.size)), - atop: '0, - id: axi_req_i.ar.id, - last: (axi_req_i.ar.len == '0), - qos: axi_req_i.ar.qos, - size: axi_req_i.ar.size, - write: 1'b0, - lock: axi_req_i.ar.lock - }; - rd_meta = rd_meta_d; - rd_meta.addr = addr_t'(axi_req_i.ar.addr); - rd_valid = 1'b1; - if (rd_ready) begin - r_cnt_d = axi_req_i.ar.len; - axi_rsp_o.ar_ready = 1'b1; - end - end - end - - // Handle writes. - always_comb begin - // Default assignments - axi_rsp_o.aw_ready = 1'b0; - axi_rsp_o.w_ready = 1'b0; - wr_meta_d = wr_meta_q; - wr_meta = '{default: '0}; - wr_valid = 1'b0; - w_cnt_d = w_cnt_q; - // Handle W bursts in progress. - if (w_cnt_q > '0) begin - wr_meta_d.last = (w_cnt_q == 8'd1); - wr_meta = wr_meta_d; - wr_meta.addr = wr_meta_q.addr + axi_pkg::num_bytes(wr_meta_q.size); - if (axi_req_i.w_valid) begin - wr_valid = 1'b1; - if (wr_ready) begin - axi_rsp_o.w_ready = 1'b1; - w_cnt_d--; - wr_meta_d.addr = wr_meta.addr; - end - end - // Handle new AW if there is one. - end else if (axi_req_i.aw_valid && axi_req_i.w_valid) begin - wr_meta_d = '{ - addr: addr_t'(axi_pkg::aligned_addr(axi_pkg::largest_addr_t'(axi_req_i.aw.addr), axi_req_i.aw.size)), - atop: axi_req_i.aw.atop, - id: axi_req_i.aw.id, - last: (axi_req_i.aw.len == '0), - qos: axi_req_i.aw.qos, - size: axi_req_i.aw.size, - write: 1'b1, - lock: axi_req_i.aw.lock - }; - wr_meta = wr_meta_d; - wr_meta.addr = addr_t'(axi_req_i.aw.addr); - wr_valid = 1'b1; - if (wr_ready) begin - w_cnt_d = axi_req_i.aw.len; - axi_rsp_o.aw_ready = 1'b1; - axi_rsp_o.w_ready = 1'b1; - end - end - end - - // Arbitrate between reads and writes. - cc_stream_mux #( - .data_t ( meta_t ), - .NumInp ( 32'd2 ) - ) i_ax_mux ( - .inp_data_i ({wr_meta, rd_meta }), - .inp_valid_i ({wr_valid, rd_valid}), - .inp_ready_o ({wr_ready, rd_ready}), - .inp_sel_i ( meta_sel_d ), - .oup_data_o ( meta ), - .oup_valid_o ( arb_valid ), - .oup_ready_i ( arb_ready ) - ); - always_comb begin - meta_sel_d = meta_sel_q; - sel_lock_d = sel_lock_q; - if (sel_lock_q) begin - meta_sel_d = meta_sel_q; - if (arb_valid && arb_ready) begin - sel_lock_d = 1'b0; - end - end else begin - if (wr_valid ^ rd_valid) begin - // If either write or read is valid but not both, select the valid one. - meta_sel_d = wr_valid; - end else if (wr_valid && rd_valid) begin - // If both write and read are valid, decide according to QoS then burst properties. - // Prioritize higher QoS. - if (wr_meta.qos > rd_meta.qos) begin - meta_sel_d = 1'b1; - end else if (rd_meta.qos > wr_meta.qos) begin - meta_sel_d = 1'b0; - // Decide requests with identical QoS. - end else if (wr_meta.qos == rd_meta.qos) begin - // 1. Prioritize individual writes over read bursts. - // Rationale: Read bursts can be interleaved on AXI but write bursts cannot. - if (wr_meta.last && !rd_meta.last) begin - meta_sel_d = 1'b1; - // 2. Prioritize ongoing burst. - // Rationale: Stalled bursts create back-pressure or require costly buffers. - end else if (w_cnt_q > '0) begin - meta_sel_d = 1'b1; - end else if (r_cnt_q > '0) begin - meta_sel_d = 1'b0; - // 3. Otherwise arbitrate round robin to prevent starvation. - end else begin - meta_sel_d = ~meta_sel_q; - end - end - end - // Lock arbitration if valid but not yet ready. - if (arb_valid && !arb_ready) begin - sel_lock_d = 1'b1; - end - end - end - - // Fork arbitrated stream to meta data, memory requests, and R/B channel selection. - cc_stream_fork #( - .NumOup ( 32'd3 ) - ) i_fork ( - .clk_i, - .rst_ni, - .clr_i ( 1'b0 ), - .valid_i ( arb_valid ), - .ready_o ( arb_ready ), - .valid_o ({sel_valid, meta_valid, reqrsp_req_o.q_valid}), - .ready_i ({sel_ready, meta_ready, reqrsp_rsp_i.q_ready}) - ); - - assign sel_b = meta.write & meta.last; - assign sel_r = ~meta.write | meta.atop[5]; - - cc_stream_fifo #( - .FallThrough ( 1'b1 ), - .Depth ( 32'd1 + BufDepth ), - .data_t ( logic[1:0] ) - ) i_sel_buf ( - .clk_i, - .rst_ni, - .clr_i ( 1'b0 ), - .flush_i ( 1'b0 ), - .data_i ({sel_b, sel_r }), - .valid_i ( sel_valid ), - .ready_o ( sel_ready ), - .data_o ({sel_buf_b, sel_buf_r}), - .valid_o ( sel_buf_valid ), - .ready_i ( sel_buf_ready ), - .usage_o ( /* unused */ ) - ); - - cc_stream_fifo #( - .FallThrough ( 1'b1 ), - .Depth ( 32'd1 + BufDepth ), - .data_t ( meta_t ) - ) i_meta_buf ( - .clk_i, - .rst_ni, - .clr_i ( 1'b0 ), - .flush_i ( 1'b0 ), - .data_i ( meta ), - .valid_i ( meta_valid ), - .ready_o ( meta_ready ), - .data_o ( meta_buf ), - .valid_o ( meta_buf_valid ), - .ready_i ( meta_buf_ready ), - .usage_o ( /* unused */ ) - ); - - assign reqrsp_req_o.q = '{ - addr: meta.addr, - write: meta.write & (amo == snitch_pkg::AMONone), - amo: amo, - // Silence those channels in case of a read. - data: data & {DataWidth{meta.write}}, - strb: axi_req_i.w.strb & {StrbWidth{meta.write}}, - size: meta.size, - default: '0 - }; - - always_comb begin - amo = reqrsp_pkg::from_axi_amo(meta.atop); - data = axi_req_i.w.data; - // The `AMOAnd` has a slightly different semantic to the AXI `Set`. - if (amo == snitch_pkg::AMOAnd) data = ~axi_req_i.w.data; - // Check wether this meant to be an exclusive access. - if (meta.lock) begin - if (meta.write) amo = snitch_pkg::AMOSC; - else amo = snitch_pkg::AMOLR; - end - end - - // Join memory read data and meta data stream. - logic mem_join_valid, mem_join_ready; - cc_stream_join #( - .NumInp ( 32'd2 ) - ) i_join ( - .inp_valid_i ({reqrsp_rsp_i.p_valid, meta_buf_valid}), - .inp_ready_o ({reqrsp_req_o.p_ready, meta_buf_ready}), - .oup_valid_o ( mem_join_valid ), - .oup_ready_i ( mem_join_ready ) - ); - - // Dynamically fork the joined stream to B and R channels. - cc_stream_fork_dynamic #( - .NumOup ( 32'd2 ) - ) i_fork_dynamic ( - .clk_i, - .rst_ni, - .clr_i ( 1'b0 ), - .valid_i ( mem_join_valid ), - .ready_o ( mem_join_ready ), - .sel_i ({sel_buf_b, sel_buf_r }), - .sel_valid_i ( sel_buf_valid ), - .sel_ready_o ( sel_buf_ready ), - .valid_o ({axi_rsp_o.b_valid, axi_rsp_o.r_valid}), - .ready_i ({axi_req_i.b_ready, axi_req_i.r_ready }) - ); - - // Compose error flag. - always_comb begin - resp = axi_pkg::RESP_OKAY; - resp[1] = reqrsp_rsp_i.p.error; - // The success is encoded in the LSB. - if (meta_buf.lock) begin - resp[0] = reqrsp_rsp_i.p.data[0]; - end - end - - // Compose B responses. - assign axi_rsp_o.b = '{ - id: meta_buf.id, - resp: resp, - user: '0 - }; - - // Compose R responses. - assign axi_rsp_o.r = '{ - data: reqrsp_rsp_i.p.data, - id: meta_buf.id, - last: meta_buf.last, - resp: resp, - user: '0 - }; - - // Registers - `FF(meta_sel_q, meta_sel_d, 1'b0, clk_i, rst_ni) - `FF(sel_lock_q, sel_lock_d, 1'b0, clk_i, rst_ni) - `FF(rd_meta_q, rd_meta_d, meta_t'{default: '0}, clk_i, rst_ni) - `FF(wr_meta_q, wr_meta_d, meta_t'{default: '0}, clk_i, rst_ni) - `FF(r_cnt_q, r_cnt_d, '0, clk_i, rst_ni) - `FF(w_cnt_q, w_cnt_d, '0, clk_i, rst_ni) - - // Assertions - // Make sure that write is never set for AMOs. - `ASSERT(AMOWriteEnable, reqrsp_req_o.q_valid && - (reqrsp_req_o.q.amo != snitch_pkg::AMONone) |-> !reqrsp_req_o.q.write) - // pragma translate_off - `ifndef VERILATOR - default disable iff (!rst_ni); - assume property (@(posedge clk_i) - axi_req_i.ar_valid && !axi_rsp_o.ar_ready |=> $stable(axi_req_i.ar)) - else $error("AR must remain stable until handshake has happened!"); - assert property (@(posedge clk_i) - axi_rsp_o.r_valid && !axi_req_i.r_ready |=> $stable(axi_rsp_o.r)) - else $error("R must remain stable until handshake has happened!"); - assume property (@(posedge clk_i) - axi_req_i.aw_valid && !axi_rsp_o.aw_ready |=> $stable(axi_req_i.aw)) - else $error("AW must remain stable until handshake has happened!"); - assume property (@(posedge clk_i) - axi_req_i.w_valid && !axi_rsp_o.w_ready |=> $stable(axi_req_i.w)) - else $error("W must remain stable until handshake has happened!"); - assert property (@(posedge clk_i) - axi_rsp_o.b_valid && !axi_req_i.b_ready |=> $stable(axi_rsp_o.b)) - else $error("B must remain stable until handshake has happened!"); - assert property (@(posedge clk_i) axi_req_i.ar_valid && axi_req_i.ar.len > 0 |-> - axi_req_i.ar.burst == axi_pkg::BURST_INCR) - else $error("Non-incrementing bursts are not supported!"); - assert property (@(posedge clk_i) axi_req_i.aw_valid && axi_req_i.aw.len > 0 |-> - axi_req_i.aw.burst == axi_pkg::BURST_INCR) - else $error("Non-incrementing bursts are not supported!"); - assert property (@(posedge clk_i) meta_valid && meta.atop != '0 |-> meta.write) - else $warning("Unexpected atomic operation on read."); - `endif - // pragma translate_on -endmodule - -`include "reqrsp_interface/typedef.svh" -`include "reqrsp_interface/assign.svh" -`include "axi/typedef.svh" -`include "axi/assign.svh" - -/// Interface Wrapper -module axi_to_reqrsp_intf #( - /// AXI addr width. - parameter int unsigned AddrWidth = 0, - /// AXI data width. - parameter int unsigned DataWidth = 0, - /// AXI id width. - parameter int unsigned IdWidth = 0, - /// AXI user wdith. - parameter int unsigned UserWidth = 0, - /// Depth of memory response buffer. This should be equal to the downstream - /// response latency. - parameter int unsigned BufDepth = 1 -) ( - /// Clock input. - input logic clk_i, - /// Asynchronous reset, active low. - input logic rst_ni, - /// The unit is busy handling an AXI4+ATOP request. - output logic busy_o, - REQRSP_BUS reqrsp, - AXI_BUS axi -); - - typedef logic [AddrWidth-1:0] addr_t; - typedef logic [DataWidth-1:0] data_t; - typedef logic [DataWidth/8-1:0] strb_t; - typedef logic [IdWidth-1:0] id_t; - typedef logic [UserWidth-1:0] user_t; - - `REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t) - - `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) - - `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(axi_rsp_t, b_chan_t, r_chan_t) - - reqrsp_req_t reqrsp_req; - reqrsp_rsp_t reqrsp_rsp; - - axi_req_t axi_req; - axi_rsp_t axi_rsp; - - axi_to_reqrsp #( - .axi_req_t (axi_req_t), - .axi_rsp_t (axi_rsp_t), - .AddrWidth (AddrWidth), - .DataWidth (DataWidth), - .IdWidth (IdWidth), - .BufDepth (BufDepth), - .reqrsp_req_t (reqrsp_req_t), - .reqrsp_rsp_t (reqrsp_rsp_t ) - ) i_dut ( - .clk_i, - .rst_ni, - .busy_o, - .axi_req_i (axi_req), - .axi_rsp_o (axi_rsp), - .reqrsp_req_o (reqrsp_req), - .reqrsp_rsp_i (reqrsp_rsp) - ); - - `REQRSP_ASSIGN_FROM_REQ(reqrsp, reqrsp_req) - `REQRSP_ASSIGN_TO_RESP(reqrsp_rsp, reqrsp) - - `AXI_ASSIGN_TO_REQ(axi_req, axi) - `AXI_ASSIGN_FROM_RESP(axi, axi_rsp) - -endmodule diff --git a/hw/reqrsp_interface/src/generic_reqrsp_cut.sv b/hw/reqrsp_interface/src/generic_reqrsp_cut.sv deleted file mode 100644 index cfe5593780..0000000000 --- a/hw/reqrsp_interface/src/generic_reqrsp_cut.sv +++ /dev/null @@ -1,61 +0,0 @@ -// Copyright 2025 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Author: Luca Colagrande - -`include "reqrsp_interface/typedef.svh" - -/// Cut all combinatorial paths through a generic `reqrsp`-like interface. -module generic_reqrsp_cut #( - /// Request type. - parameter type req_chan_t = logic, - /// Response type. - parameter type rsp_chan_t = logic, - /// Bypass request channel. - parameter bit BypassReq = 0, - /// Bypass Response channel. - parameter bit BypassRsp = 0, - /// Derived parameters *do not override* - localparam type req_t = `GENERIC_REQRSP_REQ_STRUCT(req_chan_t), - localparam type rsp_t = `GENERIC_REQRSP_RSP_STRUCT(rsp_chan_t) -) ( - input logic clk_i, - input logic rst_ni, - input req_t slv_req_i, - output rsp_t slv_rsp_o, - output req_t mst_req_o, - input rsp_t mst_rsp_i -); - - cc_spill_register #( - .data_t(req_chan_t), - .Bypass(BypassReq) - ) i_spill_register_q ( - .clk_i, - .rst_ni, - .clr_i (1'b0), - .valid_i(slv_req_i.q_valid), - .ready_o(slv_rsp_o.q_ready), - .data_i (slv_req_i.q), - .valid_o(mst_req_o.q_valid), - .ready_i(mst_rsp_i.q_ready), - .data_o (mst_req_o.q) - ); - - cc_spill_register #( - .data_t(rsp_chan_t), - .Bypass(BypassRsp) - ) i_spill_register_p ( - .clk_i, - .rst_ni, - .clr_i (1'b0), - .valid_i(mst_rsp_i.p_valid), - .ready_o(mst_req_o.p_ready), - .data_i (mst_rsp_i.p), - .valid_o(slv_rsp_o.p_valid), - .ready_i(slv_req_i.p_ready), - .data_o (slv_rsp_o.p) - ); - -endmodule diff --git a/hw/reqrsp_interface/src/generic_reqrsp_demux.sv b/hw/reqrsp_interface/src/generic_reqrsp_demux.sv deleted file mode 100644 index d634babaf1..0000000000 --- a/hw/reqrsp_interface/src/generic_reqrsp_demux.sv +++ /dev/null @@ -1,86 +0,0 @@ -// Copyright 2025 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Author: Luca Colagrande - -`include "reqrsp_interface/typedef.svh" - -/* -Module: generic_reqrsp_demux -Demultiplex one generic `reqrsp`-like port onto multiple, based on an external index. -Ordering of responses is not guaranteed to match request ordering. - -Parameters: - NrPorts - Number of output ports. - req_chan_t - Request channel type. - rsp_chan_t - Response channel type. - -Ports: - clk_i - Clock. - rst_ni - Active-low reset. - slv_req_i - Slave port, request from single master. - slv_rsp_o - Slave port, response to single master. - mst_req_o - Master ports, requests to all slaves. - mst_rsp_i - Master ports, responses from all slaves. - idx_i - Index selecting which master port to route the incoming request to. -*/ -module generic_reqrsp_demux #( - parameter int unsigned NrPorts = 2, - parameter type req_chan_t = logic, - parameter type rsp_chan_t = logic, - // Dependent parameters - localparam int unsigned IdxWidth = cc_pkg::idx_width(NrPorts), - localparam type req_t = `GENERIC_REQRSP_REQ_STRUCT(req_chan_t), - localparam type rsp_t = `GENERIC_REQRSP_RSP_STRUCT(rsp_chan_t) -) ( - input logic clk_i, - input logic rst_ni, - input req_t slv_req_i, - output rsp_t slv_rsp_o, - output req_t [NrPorts-1:0] mst_req_o, - input rsp_t [NrPorts-1:0] mst_rsp_i, - input logic [IdxWidth-1:0] idx_i -); - - logic [NrPorts-1:0] mst_q_valid, mst_q_ready; - logic [NrPorts-1:0] mst_p_valid, mst_p_ready; - rsp_chan_t [NrPorts-1:0] mst_p_data; - - // Demux the request valid/ready handshake to the selected master port. - cc_stream_demux #( - .NumOup(NrPorts) - ) i_stream_demux ( - .inp_valid_i(slv_req_i.q_valid), - .inp_ready_o(slv_rsp_o.q_ready), - .oup_sel_i (idx_i), - .oup_valid_o(mst_q_valid), - .oup_ready_i(mst_q_ready) - ); - - // Arbitrate responses from all master ports back to the slave. - cc_stream_arbiter #( - .data_t(rsp_chan_t), - .NumInp(NrPorts) - ) i_stream_arbiter ( - .clk_i, - .rst_ni, - .clr_i (1'b0), - .inp_data_i (mst_p_data), - .inp_valid_i(mst_p_valid), - .inp_ready_o(mst_p_ready), - .oup_data_o (slv_rsp_o.p), - .oup_valid_o(slv_rsp_o.p_valid), - .oup_ready_i(slv_req_i.p_ready) - ); - - for (genvar i = 0; i < NrPorts; i++) begin : gen_port_connections - assign mst_req_o[i].q_valid = mst_q_valid[i]; - assign mst_req_o[i].q = slv_req_i.q; - assign mst_q_ready[i] = mst_rsp_i[i].q_ready; - assign mst_req_o[i].p_ready = mst_p_ready[i]; - assign mst_p_valid[i] = mst_rsp_i[i].p_valid; - assign mst_p_data[i] = mst_rsp_i[i].p; - end - -endmodule diff --git a/hw/reqrsp_interface/src/generic_reqrsp_mux.sv b/hw/reqrsp_interface/src/generic_reqrsp_mux.sv deleted file mode 100644 index 76061b7462..0000000000 --- a/hw/reqrsp_interface/src/generic_reqrsp_mux.sv +++ /dev/null @@ -1,153 +0,0 @@ -// Copyright 2025 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Author: Luca Colagrande - -`include "reqrsp_interface/typedef.svh" - -/// Multiplex multiple generic `reqrsp`-like ports onto one, based on arbitration. -module generic_reqrsp_mux #( - /// Number of input ports. - parameter int unsigned NrPorts = 2, - /// Request channel type. - parameter type req_chan_t = logic, - /// Response channel type. - parameter type rsp_chan_t = logic, - /// Amount of outstanding responses. Determines the FIFO size. - parameter int unsigned RspDepth = 8, - /// Cut timing paths on the request path. Incurs a cycle additional latency. - /// Registers are inserted at the slave side. - parameter bit [NrPorts-1:0] RegisterReq = '0, - /// Externally provide routing information for responses. Can be used when - /// storing response routes externally, e.g. as a source tag passed along a - /// pipeline, i.e. when RspDepth == 0. - parameter bit ExtRspRoute = 1'b0, - /// Dependent parameters *do not override* - /// Width of the arbitrated index. - localparam int unsigned IdxWidth = cc_pkg::idx_width(NrPorts), - localparam type req_t = `GENERIC_REQRSP_REQ_STRUCT(req_chan_t), - localparam type rsp_t = `GENERIC_REQRSP_RSP_STRUCT(rsp_chan_t) -) ( - input logic clk_i, - input logic rst_ni, - input req_t [NrPorts-1:0] slv_req_i, - output rsp_t [NrPorts-1:0] slv_rsp_o, - output req_t mst_req_o, - input rsp_t mst_rsp_i, - // Route responses should follow when using external routing. - input logic [IdxWidth-1:0] rsp_route_i, - // Request port select by the arbitration logic. - output logic [IdxWidth-1:0] idx_o -); - - logic [NrPorts-1:0] req_valid_masked, req_ready_masked; - logic [IdxWidth-1:0] idx, idx_rsp; - logic full; - - req_chan_t [NrPorts-1:0] req_payload_q; - logic [NrPorts-1:0] req_valid_q, req_ready_q; - - // Unforunately we need this signal otherwise the simulator complains about - // multiple driven signals, because some other signals are driven from an - // `always_comb` block. - logic [NrPorts-1:0] slv_rsp_q_ready; - - // Optionally cut the incoming paths - for (genvar i = 0; i < NrPorts; i++) begin : gen_cuts - cc_spill_register #( - .data_t (req_chan_t), - .Bypass (!RegisterReq[i]) - ) i_spill_register_req ( - .clk_i, - .rst_ni, - .clr_i (1'b0), - .valid_i (slv_req_i[i].q_valid), - .ready_o (slv_rsp_q_ready[i]), - .data_i (slv_req_i[i].q), - .valid_o (req_valid_q[i]), - .ready_i (req_ready_masked[i]), - .data_o (req_payload_q[i]) - ); - end - - // We need to silence the handshake in case the fifo is full and we can't - // accept more transactions. - for (genvar i = 0; i < NrPorts; i++) begin : gen_req_valid_masked - assign req_valid_masked[i] = req_valid_q[i] & ~full; - assign req_ready_masked[i] = req_ready_q[i] & ~full; - end - - /// Arbitrate requests - cc_rr_arb_tree #( - .NumIn (NrPorts), - .data_t (req_chan_t), - .AxiVldRdy (1'b1), - .LockIn (1'b1) - ) i_q_mux ( - .clk_i, - .rst_ni, - .clr_i (1'b0), - .rr_i ('0), - .req_i (req_valid_masked), - .gnt_o (req_ready_q), - .data_i (req_payload_q), - .gnt_i (mst_rsp_i.q_ready), - .req_o (mst_req_o.q_valid), - .data_o (mst_req_o.q), - .idx_o (idx_o) - ); - - // De-generate version does not need a fifo. We always know where to route - // back the responses. - if (NrPorts == 1) begin : gen_single_port - assign idx_rsp = 0; - assign full = 1'b0; - end else begin : gen_multi_port - if (ExtRspRoute) begin : gen_no_rsp_fifo - // Alternatively select route based on externally provided information. - assign idx_rsp = rsp_route_i; - assign full = 1'b0; - end else begin : gen_rsp_fifo - // For the "normal" case we need to save the arbitration decision. We do so - // by converting the handshake into a binary signal which we save for - // response routing. - cc_onehot_to_bin #( - .OnehotWidth (NrPorts) - ) i_onehot_to_bin ( - .onehot_i (req_valid_q & req_ready_q), - .bin_o (idx) - ); - // Save the arbitration decision. - cc_fifo #( - .DataWidth (IdxWidth), - .Depth (RspDepth) - ) i_rsp_fifo ( - .clk_i, - .rst_ni, - .clr_i (1'b0), - .flush_i (1'b0), - .full_o (full), - .empty_o (), - .usage_o (), - .data_i (idx), - .push_i (mst_req_o.q_valid & mst_rsp_i.q_ready), - .data_o (idx_rsp), - .pop_i (mst_req_o.p_ready & mst_rsp_i.p_valid) - ); - end - end - - // Output Mux - always_comb begin - for (int i = 0; i < NrPorts; i++) begin - slv_rsp_o[i].p_valid = '0; - slv_rsp_o[i].q_ready = slv_rsp_q_ready[i]; - slv_rsp_o[i].p = mst_rsp_i.p; - end - slv_rsp_o[idx_rsp].p_valid = mst_rsp_i.p_valid; - end - - assign mst_req_o.p_ready = slv_req_i[idx_rsp].p_ready; - -endmodule diff --git a/hw/reqrsp_interface/src/reqrsp_cut.sv b/hw/reqrsp_interface/src/reqrsp_cut.sv deleted file mode 100644 index 24408d562a..0000000000 --- a/hw/reqrsp_interface/src/reqrsp_cut.sv +++ /dev/null @@ -1,112 +0,0 @@ -// Copyright 2021 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -`include "reqrsp_interface/typedef.svh" - -// Author: Florian Zaruba - -/// Cut all combinatorial paths through the `reqrsp` interface. -module reqrsp_cut #( - /// Address width of the interface. - parameter int unsigned AddrWidth = 0, - /// Data width of the interface. - parameter int unsigned DataWidth = 0, - /// User width of the interface. - parameter int unsigned UserWidth = 0, - /// Request type. - parameter type req_t = logic, - /// Response type. - parameter type rsp_t = logic, - /// Bypass request channel. - parameter bit BypassReq = 0, - /// Bypass Response channel. - parameter bit BypassRsp = 0 -) ( - input logic clk_i, - input logic rst_ni, - input req_t slv_req_i, - output rsp_t slv_rsp_o, - output req_t mst_req_o, - input rsp_t mst_rsp_i -); - - typedef logic [AddrWidth-1:0] addr_t; - typedef logic [DataWidth-1:0] data_t; - typedef logic [DataWidth/8-1:0] strb_t; - typedef logic [UserWidth-1:0] user_t; - - `REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t) - - generic_reqrsp_cut #( - .req_chan_t(reqrsp_req_chan_t), - .rsp_chan_t(reqrsp_rsp_chan_t), - .BypassReq (BypassReq), - .BypassRsp (BypassRsp) - ) i_generic_reqrsp_cut ( - .clk_i, - .rst_ni, - .slv_req_i (slv_req_i), - .slv_rsp_o (slv_rsp_o), - .mst_req_o (mst_req_o), - .mst_rsp_i (mst_rsp_i) - ); - -endmodule - - -`include "reqrsp_interface/typedef.svh" -`include "reqrsp_interface/assign.svh" - -module reqrsp_cut_intf #( - /// Address width of the interface. - parameter int unsigned AddrWidth = 0, - /// Data width of the interface. - parameter int unsigned DataWidth = 0, - /// User width of the interface. - parameter int unsigned UserWidth = 0, - /// Bypass request channel. - parameter bit BypassReq = 0, - /// Bypass Response channel. - parameter bit BypassRsp = 0 -) ( - input logic clk_i, - input logic rst_ni, - REQRSP_BUS slv, - REQRSP_BUS mst -); - - typedef logic [AddrWidth-1:0] addr_t; - typedef logic [DataWidth-1:0] data_t; - typedef logic [DataWidth/8-1:0] strb_t; - typedef logic [UserWidth-1:0] user_t; - - `REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t) - - reqrsp_req_t reqrsp_slv_req, reqrsp_mst_req; - reqrsp_rsp_t reqrsp_slv_rsp, reqrsp_mst_rsp; - - reqrsp_cut #( - .AddrWidth (AddrWidth), - .DataWidth (DataWidth), - .UserWidth (UserWidth), - .req_t (reqrsp_req_t), - .rsp_t (reqrsp_rsp_t), - .BypassReq (BypassReq), - .BypassRsp (BypassRsp) - ) i_reqrsp_cut ( - .clk_i, - .rst_ni, - .slv_req_i (reqrsp_slv_req), - .slv_rsp_o (reqrsp_slv_rsp), - .mst_req_o (reqrsp_mst_req), - .mst_rsp_i (reqrsp_mst_rsp) - ); - - `REQRSP_ASSIGN_TO_REQ(reqrsp_slv_req, slv) - `REQRSP_ASSIGN_FROM_RESP(slv, reqrsp_slv_rsp) - - `REQRSP_ASSIGN_FROM_REQ(mst, reqrsp_mst_req) - `REQRSP_ASSIGN_TO_RESP(reqrsp_mst_rsp, mst) - -endmodule diff --git a/hw/reqrsp_interface/src/reqrsp_demux.sv b/hw/reqrsp_interface/src/reqrsp_demux.sv deleted file mode 100644 index 4b7e6e18c3..0000000000 --- a/hw/reqrsp_interface/src/reqrsp_demux.sv +++ /dev/null @@ -1,158 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Author: Florian Zaruba - -`include "reqrsp_interface/typedef.svh" -`include "common_cells/assertions.svh" - -module reqrsp_demux #( - /// Number of input ports. - parameter int unsigned NrPorts = 2, - /// Request type. - parameter type req_t = logic, - /// Response type. - parameter type rsp_t = logic, - /// Amount of outstanding responses. Determines the FIFO size. - parameter int unsigned RespDepth = 8, - // Dependent parameters, DO NOT OVERRIDE! - parameter int unsigned SelectWidth = cc_pkg::idx_width(NrPorts), - parameter type select_t = logic [SelectWidth-1:0] -) ( - input logic clk_i, - input logic rst_ni, - input select_t slv_select_i, - input req_t slv_req_i, - output rsp_t slv_rsp_o, - output req_t [NrPorts-1:0] mst_req_o, - input rsp_t [NrPorts-1:0] mst_rsp_i -); - - logic [NrPorts-1:0] fwd; - logic req_ready, req_valid; - logic fifo_full, fifo_empty; - logic [NrPorts-1:0] fifo_data; - logic push_id_fifo, pop_id_fifo; - - // we need space in the return id fifo, silence if no space is available - assign req_valid = ~fifo_full & slv_req_i.q_valid; - assign slv_rsp_o.q_ready = ~fifo_full & req_ready; - - // Stream demux (unwrapped because of struct issues) - always_comb begin - for (int i = 0; i < NrPorts; i++) begin - mst_req_o[i].q_valid = '0; - mst_req_o[i].q = slv_req_i.q; - mst_req_o[i].p_ready = fwd[i] ? slv_req_i.p_ready : 1'b0; - end - mst_req_o[slv_select_i].q_valid = req_valid; - end - assign req_ready = mst_rsp_i[slv_select_i].q_ready; - - assign push_id_fifo = req_valid & slv_rsp_o.q_ready; - assign pop_id_fifo = slv_rsp_o.p_valid & slv_req_i.p_ready; - - for (genvar i = 0; i < NrPorts; i++) begin : gen_fifo_data - assign fifo_data[i] = mst_rsp_i[i].q_ready & mst_req_o[i].q_valid; - end - - // Remember selected master for correct forwarding of read data/acknowledge. - cc_fifo #( - .DataWidth ( NrPorts ), - .Depth ( RespDepth ) - ) i_id_fifo ( - .clk_i, - .rst_ni, - .clr_i (1'b0), - .flush_i (1'b0), - .full_o (fifo_full), - .empty_o (fifo_empty), - .usage_o ( ), - // Onehot mask. - .data_i (fifo_data), - .push_i (push_id_fifo), - .data_o (fwd), - .pop_i (pop_id_fifo) - ); - - // Response data routing. - always_comb begin - slv_rsp_o.p = '0; - slv_rsp_o.p_valid = '0; - for (int i = 0; i < NrPorts; i++) begin - if (fwd[i]) begin - slv_rsp_o.p = mst_rsp_i[i].p; - slv_rsp_o.p_valid = mst_rsp_i[i].p_valid; - end - end - end - - `ASSERT(SelectStable, slv_req_i.q_valid && !slv_rsp_o.q_ready |=> $stable(slv_select_i)) - `ASSERT(SelectInBounds, slv_req_i.q_valid |-> (slv_select_i <= NrPorts)) - -endmodule - -`include "reqrsp_interface/typedef.svh" -`include "reqrsp_interface/assign.svh" - -/// Reqrsp demux interface version. -module reqrsp_demux_intf #( - /// Number of input ports. - parameter int unsigned NrPorts = 2, - /// Address width of the interface. - parameter int unsigned AddrWidth = 0, - /// Data width of the interface. - parameter int unsigned DataWidth = 0, - /// User width of the interface. - parameter int unsigned UserWidth = 0, - /// Amount of outstanding responses. Determines the FIFO size. - parameter int unsigned RespDepth = 8, - // Dependent parameters, DO NOT OVERRIDE! - parameter int unsigned SelectWidth = cc_pkg::idx_width(NrPorts), - parameter type select_t = logic [SelectWidth-1:0] -) ( - input logic clk_i, - input logic rst_ni, - input select_t slv_select_i, - REQRSP_BUS slv, - REQRSP_BUS mst [NrPorts] -); - - typedef logic [AddrWidth-1:0] addr_t; - typedef logic [DataWidth-1:0] data_t; - typedef logic [DataWidth/8-1:0] strb_t; - typedef logic [UserWidth-1:0] user_t; - - `REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t) - - reqrsp_req_t reqrsp_slv_req; - reqrsp_rsp_t reqrsp_slv_rsp; - - reqrsp_req_t [NrPorts-1:0] reqrsp_mst_req; - reqrsp_rsp_t [NrPorts-1:0] reqrsp_mst_rsp; - - reqrsp_demux #( - .NrPorts (NrPorts), - .req_t (reqrsp_req_t), - .rsp_t (reqrsp_rsp_t), - .RespDepth (RespDepth) - ) i_reqrsp_demux ( - .clk_i, - .rst_ni, - .slv_select_i (slv_select_i), - .slv_req_i (reqrsp_slv_req), - .slv_rsp_o (reqrsp_slv_rsp), - .mst_req_o (reqrsp_mst_req), - .mst_rsp_i (reqrsp_mst_rsp) - ); - - `REQRSP_ASSIGN_TO_REQ(reqrsp_slv_req, slv) - `REQRSP_ASSIGN_FROM_RESP(slv, reqrsp_slv_rsp) - - for (genvar i = 0; i < NrPorts; i++) begin : gen_interface_assignment - `REQRSP_ASSIGN_FROM_REQ(mst[i], reqrsp_mst_req[i]) - `REQRSP_ASSIGN_TO_RESP(reqrsp_mst_rsp[i], mst[i]) - end - -endmodule diff --git a/hw/reqrsp_interface/src/reqrsp_intf.sv b/hw/reqrsp_interface/src/reqrsp_intf.sv deleted file mode 100644 index 43570bb14f..0000000000 --- a/hw/reqrsp_interface/src/reqrsp_intf.sv +++ /dev/null @@ -1,133 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Fabian Schuiki - -/// A simple two channel interface. -/// -/// This interface provides two channels, one for requests and one for -/// responses. Both channels have a valid/ready handshake. The sender sets the -/// channel signals and pulls valid high. Once pulled high, valid must remain -/// high and none of the signals may change. The transaction completes when both -/// valid and ready are high. Valid must not depend on ready. The master can -/// request a read or write on the `q` channel. The slave responds on the `p` -/// channel once the action has been completed. Every transaction returns a -/// response. For write transaction the datum on the response channel is -/// invalid. For read and atomic transaction the value corresponds to the -/// un-modified value (the value read before an operation was performed).For -/// further details see docs/index.md - -// verilog_lint: waive interface-name-style -interface REQRSP_BUS #( - /// The width of the address. - parameter int ADDR_WIDTH = -1, - /// The width of the data. - parameter int DATA_WIDTH = -1 -); - - import snitch_pkg::*; - - localparam int unsigned StrbWidth = DATA_WIDTH / 8; - - typedef logic [ADDR_WIDTH-1:0] addr_t; - typedef logic [DATA_WIDTH-1:0] data_t; - typedef logic [StrbWidth-1:0] strb_t; - /// The request channel (Q). - addr_t q_addr; - /// 0 = read, 1 = write, 1 = amo fetch-and-op - logic q_write; - amo_op_e q_amo; - data_t q_data; - /// Byte-wise strobe - strb_t q_strb; - size_t q_size; - logic q_valid; - logic q_ready; - - /// The response channel (P). - data_t p_data; - /// 0 = ok, 1 = error - logic p_error; - logic p_valid; - logic p_ready; - - - modport in ( - input q_addr, q_write, q_amo, q_size, q_data, q_strb, q_valid, p_ready, - output q_ready, p_data, p_error, p_valid - ); - modport out ( - output q_addr, q_write, q_amo, q_size, q_data, q_strb, q_valid, p_ready, - input q_ready, p_data, p_error, p_valid - ); - -endinterface - -// The DV interface additionally caries a clock signal. -// verilog_lint: waive interface-name-style -interface REQRSP_BUS_DV #( - /// The width of the address. - parameter int ADDR_WIDTH = -1, - /// The width of the data. - parameter int DATA_WIDTH = -1 -) ( - input logic clk_i -); - - import snitch_pkg::*; - - localparam int unsigned StrbWidth = DATA_WIDTH / 8; - - typedef logic [ADDR_WIDTH-1:0] addr_t; - typedef logic [DATA_WIDTH-1:0] data_t; - typedef logic [StrbWidth-1:0] strb_t; - /// The request channel (Q). - addr_t q_addr; - /// 0 = read, 1 = write, 1 = amo fetch-and-op - logic q_write; - amo_op_e q_amo; - data_t q_data; - /// Byte-wise strobe - strb_t q_strb; - size_t q_size; - logic q_valid; - logic q_ready; - - /// The response channel (P). - data_t p_data; - /// 0 = ok, 1 = error - logic p_error; - logic p_valid; - logic p_ready; - - modport in ( - input q_addr, q_write, q_amo, q_size, q_data, q_strb, q_valid, p_ready, - output q_ready, p_data, p_error, p_valid - ); - modport out ( - output q_addr, q_write, q_amo, q_size, q_data, q_strb, q_valid, p_ready, - input q_ready, p_data, p_error, p_valid - ); - modport monitor ( - input q_addr, q_write, q_amo, q_size, q_data, q_strb, q_valid, p_ready, - q_ready, p_data, p_error, p_valid - ); - - // pragma translate_off - `ifndef VERILATOR - assert property (@(posedge clk_i) (q_valid && !q_ready |=> $stable(q_addr))); - assert property (@(posedge clk_i) (q_valid && !q_ready |=> $stable(q_write))); - assert property (@(posedge clk_i) (q_valid && !q_ready |=> $stable(q_amo))); - assert property (@(posedge clk_i) (q_valid && !q_ready |=> $stable(q_size))); - assert property (@(posedge clk_i) (q_valid && !q_ready |=> $stable(q_data))); - assert property (@(posedge clk_i) (q_valid && !q_ready |=> $stable(q_strb))); - assert property (@(posedge clk_i) (q_valid && !q_ready |=> q_valid)); - - assert property (@(posedge clk_i) (p_valid && !p_ready |=> $stable(p_data))); - assert property (@(posedge clk_i) (p_valid && !p_ready |=> $stable(p_error))); - assert property (@(posedge clk_i) (p_valid && !p_ready |=> p_valid)); - `endif - // pragma translate_on - -endinterface diff --git a/hw/reqrsp_interface/src/reqrsp_iso.sv b/hw/reqrsp_interface/src/reqrsp_iso.sv deleted file mode 100644 index bb2ecfe87c..0000000000 --- a/hw/reqrsp_interface/src/reqrsp_iso.sv +++ /dev/null @@ -1,150 +0,0 @@ -// Copyright 2021 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -`include "reqrsp_interface/typedef.svh" - -// Author: Florian Zaruba - -/// Decouple `src` and `dst` side using an isochronous clock-domain crossing. -/// See `common_cells/isochronous_spill_register` for further detail on the -/// clock requirements. -module reqrsp_iso #( - /// Address width of the interface. - parameter int unsigned AddrWidth = 0, - /// Data width of the interface. - parameter int unsigned DataWidth = 0, - /// User width of the interface. - parameter int unsigned UserWidth = 0, - /// Request type. - parameter type req_t = logic, - /// Response type. - parameter type rsp_t = logic, - /// Bypass. - parameter bit BypassReq = 0, - parameter bit BypassRsp = 0 -) ( - /// Clock of source clock domain. - input logic src_clk_i, - /// Active low async reset in source domain. - input logic src_rst_ni, - /// Source request data. - input req_t src_req_i, - /// Source response data. - output rsp_t src_rsp_o, - /// Clock of destination clock domain. - input logic dst_clk_i, - /// Active low async reset in destination domain. - input logic dst_rst_ni, - /// Destination request data. - output req_t dst_req_o, - /// Destination response data. - input rsp_t dst_rsp_i -); - - typedef logic [AddrWidth-1:0] addr_t; - typedef logic [DataWidth-1:0] data_t; - typedef logic [DataWidth/8-1:0] strb_t; - typedef logic [cc_pkg::iomsb(UserWidth):0] user_t; - - `REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t) - - cc_isochronous_spill_register #( - .data_t (reqrsp_req_chan_t), - .Bypass (BypassReq) - ) i_isochronous_spill_register_q ( - .src_clk_i (src_clk_i), - .src_rst_ni (src_rst_ni), - .src_valid_i (src_req_i.q_valid) , - .src_ready_o (src_rsp_o.q_ready) , - .src_data_i (src_req_i.q), - .dst_clk_i (dst_clk_i), - .dst_rst_ni (dst_rst_ni), - .dst_valid_o (dst_req_o.q_valid), - .dst_ready_i (dst_rsp_i.q_ready), - .dst_data_o (dst_req_o.q) - ); - - cc_isochronous_spill_register #( - .data_t (reqrsp_rsp_chan_t), - .Bypass (BypassRsp) - ) i_isochronous_spill_register_p ( - .src_clk_i (dst_clk_i), - .src_rst_ni (dst_rst_ni), - .src_valid_i (dst_rsp_i.p_valid) , - .src_ready_o (dst_req_o.p_ready) , - .src_data_i (dst_rsp_i.p), - .dst_clk_i (src_clk_i), - .dst_rst_ni (src_rst_ni), - .dst_valid_o (src_rsp_o.p_valid), - .dst_ready_i (src_req_i.p_ready), - .dst_data_o (src_rsp_o.p) - ); - -endmodule - -`include "reqrsp_interface/typedef.svh" -`include "reqrsp_interface/assign.svh" - -/// Interface wrapper for `reqrsp_iso`. -module reqrsp_iso_intf #( - /// Address width of the interface. - parameter int unsigned AddrWidth = 0, - /// Data width of the interface. - parameter int unsigned DataWidth = 0, - /// User width of the interface. - parameter int unsigned UserWidth = 0, - /// Bypass. - parameter bit BypassReq = 0, - parameter bit BypassRsp = 0 -) ( - /// Clock of source clock domain. - input logic src_clk_i, - /// Active low async reset in source domain. - input logic src_rst_ni, - /// Source interface. - REQRSP_BUS src, - /// Clock of destination clock domain. - input logic dst_clk_i, - /// Active low async reset in destination domain. - input logic dst_rst_ni, - /// Destination interface. - REQRSP_BUS dst -); - - typedef logic [AddrWidth-1:0] addr_t; - typedef logic [DataWidth-1:0] data_t; - typedef logic [DataWidth/8-1:0] strb_t; - typedef logic [cc_pkg::iomsb(UserWidth):0] user_t; - - `REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t) - - reqrsp_req_t reqrsp_src_req, reqrsp_dst_req; - reqrsp_rsp_t reqrsp_src_rsp, reqrsp_dst_rsp; - - reqrsp_iso #( - .AddrWidth (AddrWidth), - .DataWidth (DataWidth), - .UserWidth (UserWidth), - .req_t (reqrsp_req_t), - .rsp_t (reqrsp_rsp_t), - .BypassReq (BypassReq), - .BypassRsp (BypassRsp) - ) i_reqrsp_iso ( - .src_clk_i, - .src_rst_ni, - .src_req_i (reqrsp_src_req), - .src_rsp_o (reqrsp_src_rsp), - .dst_clk_i, - .dst_rst_ni, - .dst_req_o (reqrsp_dst_req), - .dst_rsp_i (reqrsp_dst_rsp) - ); - - `REQRSP_ASSIGN_TO_REQ(reqrsp_src_req, src) - `REQRSP_ASSIGN_FROM_RESP(src, reqrsp_src_rsp) - - `REQRSP_ASSIGN_FROM_REQ(dst, reqrsp_dst_req) - `REQRSP_ASSIGN_TO_RESP(reqrsp_dst_rsp, dst) - -endmodule diff --git a/hw/reqrsp_interface/src/reqrsp_mux.sv b/hw/reqrsp_interface/src/reqrsp_mux.sv deleted file mode 100644 index 42e0bd7698..0000000000 --- a/hw/reqrsp_interface/src/reqrsp_mux.sv +++ /dev/null @@ -1,134 +0,0 @@ -// Copyright 2021 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Author: Florian Zaruba - -`include "reqrsp_interface/typedef.svh" - -/// Multiplex multiple `reqrsp` ports onto one, based on arbitration. -module reqrsp_mux #( - /// Number of input ports. - parameter int unsigned NrPorts = 2, - /// Address width of the interface. - parameter int unsigned AddrWidth = 0, - /// Data width of the interface. - parameter int unsigned DataWidth = 0, - /// User width of the interface. - parameter int unsigned UserWidth = 0, - /// Request type. - parameter type req_t = logic, - /// Response type. - parameter type rsp_t = logic, - /// Amount of outstanding responses. Determines the FIFO size. - parameter int unsigned RespDepth = 8, - /// Cut timing paths on the request path. Incurs a cycle additional latency. - /// Registers are inserted at the slave side. - parameter bit [NrPorts-1:0] RegisterReq = '0, - /// Dependent parameter, do **not** overwrite. - /// Width of the arbitrated index. - parameter int unsigned IdxWidth = (NrPorts > 32'd1) ? unsigned'($clog2(NrPorts)) : 32'd1 -) ( - input logic clk_i, - input logic rst_ni, - input req_t [NrPorts-1:0] slv_req_i, - output rsp_t [NrPorts-1:0] slv_rsp_o, - output req_t mst_req_o, - input rsp_t mst_rsp_i, - output logic [IdxWidth-1:0] idx_o -); - - typedef logic [AddrWidth-1:0] addr_t; - typedef logic [DataWidth-1:0] data_t; - typedef logic [DataWidth/8-1:0] strb_t; - typedef logic [UserWidth-1:0] user_t; - - `REQRSP_TYPEDEF_REQ_CHAN_T(req_chan_t, addr_t, data_t, strb_t, user_t) - `REQRSP_TYPEDEF_RSP_CHAN_T(rsp_chan_t, data_t) - - generic_reqrsp_mux #( - .NrPorts(NrPorts), - .req_chan_t(req_chan_t), - .rsp_chan_t(rsp_chan_t), - .RspDepth(RespDepth), - .RegisterReq(RegisterReq) - ) i_generic_reqrsp_mux ( - .clk_i, - .rst_ni, - .slv_req_i, - .slv_rsp_o, - .mst_req_o, - .mst_rsp_i, - .rsp_route_i('0), - .idx_o - ); - -endmodule - -`include "reqrsp_interface/typedef.svh" -`include "reqrsp_interface/assign.svh" - -/// Interface wrapper. -module reqrsp_mux_intf #( - /// Number of input ports. - parameter int unsigned NrPorts = 2, - /// Address width of the interface. - parameter int unsigned AddrWidth = 0, - /// Data width of the interface. - parameter int unsigned DataWidth = 0, - /// User width of the interface. - parameter int unsigned UserWidth = 0, - /// Amount of outstanding responses. Determines the FIFO size. - parameter int unsigned RespDepth = 8, - /// Cut timing paths on the request path. Incurs a cycle additional latency. - /// Registers are inserted at the slave side. - parameter bit [NrPorts-1:0] RegisterReq = '0 -) ( - input logic clk_i, - input logic rst_ni, - REQRSP_BUS slv [NrPorts], - REQRSP_BUS mst, - output logic [$clog2(NrPorts)-1:0] idx_o -); - - typedef logic [AddrWidth-1:0] addr_t; - typedef logic [DataWidth-1:0] data_t; - typedef logic [DataWidth/8-1:0] strb_t; - typedef logic [UserWidth-1:0] user_t; - - `REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t) - - reqrsp_req_t [NrPorts-1:0] reqrsp_slv_req; - reqrsp_rsp_t [NrPorts-1:0] reqrsp_slv_rsp; - - reqrsp_req_t reqrsp_mst_req; - reqrsp_rsp_t reqrsp_mst_rsp; - - reqrsp_mux #( - .NrPorts (NrPorts), - .AddrWidth (AddrWidth), - .DataWidth (DataWidth), - .UserWidth (UserWidth), - .req_t (reqrsp_req_t), - .rsp_t (reqrsp_rsp_t), - .RespDepth (RespDepth), - .RegisterReq (RegisterReq) - ) i_reqrsp_mux ( - .clk_i, - .rst_ni, - .slv_req_i (reqrsp_slv_req), - .slv_rsp_o (reqrsp_slv_rsp), - .mst_req_o (reqrsp_mst_req), - .mst_rsp_i (reqrsp_mst_rsp), - .idx_o (idx_o) - ); - - for (genvar i = 0; i < NrPorts; i++) begin : gen_interface_assignment - `REQRSP_ASSIGN_TO_REQ(reqrsp_slv_req[i], slv[i]) - `REQRSP_ASSIGN_FROM_RESP(slv[i], reqrsp_slv_rsp[i]) - end - - `REQRSP_ASSIGN_FROM_REQ(mst, reqrsp_mst_req) - `REQRSP_ASSIGN_TO_RESP(reqrsp_mst_rsp, mst) - -endmodule diff --git a/hw/reqrsp_interface/src/reqrsp_pkg.sv b/hw/reqrsp_interface/src/reqrsp_pkg.sv deleted file mode 100644 index a143e6bfdb..0000000000 --- a/hw/reqrsp_interface/src/reqrsp_pkg.sv +++ /dev/null @@ -1,56 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -/// Package containing common req resp definitions. -package reqrsp_pkg; - - import snitch_pkg::*; - - /// The given operation falls into the atomic fetch-and-op memory operations. - function automatic logic is_amo(amo_op_e amo); - if (amo inside {AMOSwap, AMOAdd, AMOAnd, AMOOr, AMOXor, AMOMax, AMOMaxu, AMOMin, AMOMinu}) begin - return 1; - end else begin - return 0; - end - endfunction - - /// Translate to AXI5+ATOP AMOs - function automatic logic [5:0] to_axi_amo(amo_op_e amo); - logic [5:0] result; - unique case (amo) - AMOSwap: result = axi_pkg::ATOP_ATOMICSWAP; - AMOAdd: result = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_ADD}; - // Careful, this case needs to invert the bits on the write data bus. - AMOAnd: result = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_CLR}; - AMOOr: result = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SET}; - AMOXor: result = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_EOR}; - AMOMax: result = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SMAX}; - AMOMaxu: result = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMAX}; - AMOMin: result = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SMIN}; - AMOMinu: result = {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMIN}; - default: result = '0; - endcase - return result; - endfunction - - /// Translate from AXI5+ATOP AMOs - function automatic amo_op_e from_axi_amo(axi_pkg::atop_t amo); - amo_op_e result; - unique case (amo) - axi_pkg::ATOP_ATOMICSWAP: result = AMOSwap; - {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_ADD}: result = AMOAdd; - // Careful, this case needs to invert the bits on the write data bus. - {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_CLR}: result = AMOAnd; - {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SET}: result = AMOOr; - {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_EOR}: result = AMOXor; - {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SMAX}: result = AMOMax; - {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMAX}: result = AMOMaxu; - {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_SMIN}: result = AMOMin; - {axi_pkg::ATOP_ATOMICLOAD, axi_pkg::ATOP_LITTLE_END, axi_pkg::ATOP_UMIN}: result = AMOMinu; - default: result = AMONone; - endcase - return result; - endfunction -endpackage diff --git a/hw/reqrsp_interface/src/reqrsp_test.sv b/hw/reqrsp_interface/src/reqrsp_test.sv deleted file mode 100644 index a0d30371dc..0000000000 --- a/hw/reqrsp_interface/src/reqrsp_test.sv +++ /dev/null @@ -1,387 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Fabian Schuiki -// Florian Zaruba - -/// A set of testbench utilities for REQRSP interfaces. -package reqrsp_test; - - import snitch_pkg::*; - - class req_t #( - parameter int AW = 32, - parameter int DW = 32 - ); - rand logic [AW-1:0] addr; - rand logic write; - rand amo_op_e amo; - rand logic [DW-1:0] data; - rand logic [DW/8-1:0] strb; - rand size_t size; - - rand bit is_amo; - - constraint legal_amo_op_c { - amo inside { - AMOSwap, AMOAdd, AMOAnd, - AMOOr, AMOXor, AMOMax, - AMOMaxu, AMOMin, AMOMinu, AMOLR, AMOSC} -> write == 0; - } - - // Reduce the amount of atomics. - constraint amo_reduce_c { - is_amo dist { 1:= 1, 0:= 10}; - is_amo -> amo inside { - AMOSwap, AMOAdd, AMOAnd, - AMOOr, AMOXor, AMOMax, - AMOMaxu, AMOMin, AMOMinu, AMOLR, AMOSC - }; - } - - /// Compare objects of same type. - function do_compare(req_t rhs); - return addr == rhs.addr & - write == rhs.write & - amo == rhs.amo & - data == rhs.data & - strb == rhs.strb & - size == rhs.size; - endfunction - - endclass - - class rsp_t #( - parameter int DW = 32 - ); - rand logic [DW-1:0] data; - rand logic error; - - /// Compare objects of same type. - function do_compare(rsp_t rhs); - return data == rhs.data & - error == rhs.error; - endfunction - - endclass - - /// A driver for the REQRSP interface. - class reqrsp_driver #( - parameter int AW = -1, - parameter int DW = -1, - parameter time TA = 0 , // stimuli application time - parameter time TT = 0 // stimuli test time - ); - virtual REQRSP_BUS_DV #( - .ADDR_WIDTH(AW), - .DATA_WIDTH(DW) - ) bus; - - function new( - virtual REQRSP_BUS_DV #( - .ADDR_WIDTH(AW), - .DATA_WIDTH(DW) - ) bus - ); - this.bus = bus; - endfunction - - task reset_master; - bus.q_addr <= '0; - bus.q_write <= '0; - bus.q_amo <= AMONone; - bus.q_data <= '0; - bus.q_strb <= '0; - bus.q_size <= '0; - bus.q_valid <= '0; - bus.p_ready <= '0; - endtask - - task reset_slave; - bus.q_ready <= '0; - bus.p_data <= '0; - bus.p_error <= '0; - bus.p_valid <= '0; - endtask - - task cycle_start; - #TT; - endtask - - task cycle_end; - @(posedge bus.clk_i); - endtask - - /// Send a request. - task send_req (input req_t req); - bus.q_addr <= #TA req.addr; - bus.q_write <= #TA req.write; - bus.q_amo <= #TA req.amo; - bus.q_data <= #TA req.data; - bus.q_strb <= #TA req.strb; - bus.q_size <= #TA req.size; - bus.q_valid <= #TA 1; - cycle_start(); - while (bus.q_ready != 1) begin cycle_end(); cycle_start(); end - cycle_end(); - bus.q_addr <= #TA '0; - bus.q_write <= #TA '0; - bus.q_data <= #TA '0; - bus.q_strb <= #TA '0; - bus.q_valid <= #TA 0; - endtask - - /// Send a response. - task send_rsp (input rsp_t rsp); - bus.p_data <= #TA rsp.data; - bus.p_error <= #TA rsp.error; - bus.p_valid <= #TA 1; - cycle_start(); - while (bus.p_ready != 1) begin cycle_end(); cycle_start(); end - cycle_end(); - bus.p_data <= #TA '0; - bus.p_error <= #TA '0; - bus.p_valid <= #TA 0; - endtask - - /// Receive a request. - task recv_req (output req_t req); - bus.q_ready <= #TA 1; - cycle_start(); - while (bus.q_valid != 1) begin cycle_end(); cycle_start(); end - req = new; - req.addr = bus.q_addr; - req.write = bus.q_write; - req.amo = bus.q_amo; - req.data = bus.q_data; - req.strb = bus.q_strb; - req.size = bus.q_size; - cycle_end(); - bus.q_ready <= #TA 0; - endtask - - /// Receive a response. - task recv_rsp (output rsp_t rsp); - bus.p_ready <= #TA 1; - cycle_start(); - while (bus.p_valid != 1) begin cycle_end(); cycle_start(); end - rsp = new; - rsp.data = bus.p_data; - rsp.error = bus.p_error; - cycle_end(); - bus.p_ready <= #TA 0; - endtask - - /// Monitor request. - task mon_req (output req_t req); - cycle_start(); - while (!(bus.q_valid && bus.q_ready)) begin cycle_end(); cycle_start(); end - req = new; - req.addr = bus.q_addr; - req.write = bus.q_write; - req.amo = bus.q_amo; - req.data = bus.q_data; - req.strb = bus.q_strb; - req.size = bus.q_size; - cycle_end(); - endtask - - /// Monitor response. - task mon_rsp (output rsp_t rsp); - cycle_start(); - while (!(bus.p_valid && bus.p_ready)) begin cycle_end(); cycle_start(); end - rsp = new; - rsp.data = bus.p_data; - rsp.error = bus.p_error; - cycle_end(); - endtask - - endclass - - // Super classs for random reqrsp drivers. - virtual class rand_reqrsp #( - // Reqrsp interface parameters - parameter int AW = 32, - parameter int DW = 32, - // Stimuli application and test time - parameter time TA = 0ps, - parameter time TT = 0ps - ); - - typedef reqrsp_test::reqrsp_driver #( - // Reqrsp bus interface paramaters; - .AW ( AW ), - .DW ( DW ), - // Stimuli application and test time - .TA ( TA ), - .TT ( TT ) - ) reqrsp_driver_t; - - reqrsp_driver_t drv; - - function new(virtual REQRSP_BUS_DV #( .ADDR_WIDTH (AW), .DATA_WIDTH (DW)) bus); - this.drv = new (bus); - endfunction - - task automatic rand_wait(input int unsigned min, input int unsigned max); - int unsigned rand_success, cycles; - rand_success = std::randomize(cycles) with { - cycles >= min; - cycles <= max; - // Weigh the distribution so that the minimum cycle time is the common - // case. - cycles dist {min := 10, [min+1:max] := 1}; - }; - assert (rand_success) else $error("Failed to randomize wait cycles!"); - repeat (cycles) @(posedge this.drv.bus.clk_i); - endtask - - endclass - - /// Generate random requests as a master device. - class rand_reqrsp_master #( - // Reqrsp interface parameters - parameter int AW = 32, - parameter int DW = 32, - // Stimuli application and test time - parameter time TA = 0ps, - parameter time TT = 0ps, - parameter int unsigned REQ_MIN_WAIT_CYCLES = 1, - parameter int unsigned REQ_MAX_WAIT_CYCLES = 20, - parameter int unsigned RSP_MIN_WAIT_CYCLES = 1, - parameter int unsigned RSP_MAX_WAIT_CYCLES = 20 - ) extends rand_reqrsp #(.AW(AW), .DW(DW), .TA(TA), .TT(TT)); - - int unsigned cnt = 0; - bit req_done = 0; - - /// Reset the driver. - task reset(); - drv.reset_master(); - endtask - - /// Constructor. - function new(virtual REQRSP_BUS_DV #( .ADDR_WIDTH (AW), .DATA_WIDTH (DW)) bus); - super.new(bus); - endfunction - - task run(input int n); - fork - send_requests(n); - recv_response(); - join - endtask - - /// Send random requests. - task send_requests (input int n); - automatic req_t r = new; - - repeat (n) begin - this.cnt++; - assert(r.randomize()); - rand_wait(REQ_MIN_WAIT_CYCLES, REQ_MAX_WAIT_CYCLES); - this.drv.send_req(r); - end - this.req_done = 1; - endtask - - /// Receive random responses. - task recv_response; - while (!this.req_done || this.cnt > 0) begin - automatic rsp_t rsp; - this.cnt--; - rand_wait(RSP_MIN_WAIT_CYCLES, RSP_MAX_WAIT_CYCLES); - this.drv.recv_rsp(rsp); - end - endtask - endclass - - class rand_reqrsp_slave #( - // Reqrsp interface parameters - parameter int AW = 32, - parameter int DW = 32, - // Stimuli application and test time - parameter time TA = 0ps, - parameter time TT = 0ps, - parameter int unsigned REQ_MIN_WAIT_CYCLES = 0, - parameter int unsigned REQ_MAX_WAIT_CYCLES = 10, - parameter int unsigned RSP_MIN_WAIT_CYCLES = 0, - parameter int unsigned RSP_MAX_WAIT_CYCLES = 10 - ) extends rand_reqrsp #(.AW(AW), .DW(DW), .TA(TA), .TT(TT)); - - mailbox req_mbx = new(); - - /// Reset the driver. - task reset(); - drv.reset_slave(); - endtask - - task run(); - fork - recv_requests(); - send_responses(); - join - endtask - - /// Constructor. - function new(virtual REQRSP_BUS_DV #( .ADDR_WIDTH (AW), .DATA_WIDTH (DW)) bus); - super.new(bus); - endfunction - - task recv_requests(); - forever begin - automatic req_t req; - rand_wait(REQ_MIN_WAIT_CYCLES, REQ_MAX_WAIT_CYCLES); - this.drv.recv_req(req); - req_mbx.put(req); - end - endtask - - task send_responses(); - automatic rsp_t rsp = new; - automatic req_t req; - forever begin - req_mbx.get(req); - assert(rsp.randomize()); - @(posedge this.drv.bus.clk_i); - rand_wait(RSP_MIN_WAIT_CYCLES, RSP_MAX_WAIT_CYCLES); - this.drv.send_rsp(rsp); - end - endtask - endclass - - class reqrsp_monitor #( - // Reqrsp interface parameters - parameter int AW = 32, - parameter int DW = 32, - // Stimuli application and test time - parameter time TA = 0ps, - parameter time TT = 0ps - ) extends rand_reqrsp #(.AW(AW), .DW(DW), .TA(TA), .TT(TT)); - - mailbox req_mbx = new, rsp_mbx = new; - - /// Constructor. - function new(virtual REQRSP_BUS_DV #( .ADDR_WIDTH (AW), .DATA_WIDTH (DW)) bus); - super.new(bus); - endfunction - - // Reqrsp Monitor. - task monitor; - fork - forever begin - automatic reqrsp_test::req_t req; - this.drv.mon_req(req); - req_mbx.put(req); - end - forever begin - automatic reqrsp_test::rsp_t rsp; - this.drv.mon_rsp(rsp); - rsp_mbx.put(rsp); - end - join - endtask - endclass - -endpackage diff --git a/hw/reqrsp_interface/src/reqrsp_to_axi.sv b/hw/reqrsp_interface/src/reqrsp_to_axi.sv deleted file mode 100644 index c0d119347c..0000000000 --- a/hw/reqrsp_interface/src/reqrsp_to_axi.sv +++ /dev/null @@ -1,360 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// AUthor: Florian Zaruba - -`include "common_cells/registers.svh" -`include "common_cells/assertions.svh" - -/// Convert reqrsp to AXI. -/// -/// Two things make this module a bit more special: -/// 1. We need to be careful with the memory model: AXI does not imply any -/// ordering between the read and the write channel. On the other hand the -/// reqrsp protocol does (implicitly because everything is in issue order). -/// 2. Atomic memory operations are supported and they are a bit quirky in the -/// AXI5 standard. In particular the kind of break the assumption that every -/// `AW` implies exactly one `B` because the read data is also returned on -/// the `R` channel. -/// -/// ## Memory Ordering -/// -/// 1. Atomics need to block and wait until the ID becomes available again. -/// 2. Reads can go after reads, AXI will maintain the ordering. -/// 3. Similarly, writes can go after writes, AXI will also maintain the -/// ordering there. -/// -/// This has the drawback that we are overly conservative when only -/// point-to-point ordering is needed. In the future one can implement two -/// regions: (i) one where the ordering between reads and writs is point to -/// point (ii) one where the ordering is strong as it is currently the case. -/// That would also mean that we would need to keep a FIFO width the arbitration -/// decisions so that we can route the response from the correct channel. -/// -/// ## Complexity -/// -/// The module just needs to save the amount of transactions which are currently -/// in-flight. This parameter is bound by `MaxTrans` and O(log2(MaxTrans))) -/// storage complexity is needed. -/// -/// This module does not emit any bursts, but AXI5 capability is needed because -/// of the atomic memory operations. -module reqrsp_to_axi import reqrsp_pkg::*; import snitch_pkg::*; #( - /// Number of same transactions which can be in-flight - /// simulatnously. Must be greater than 1. - parameter int unsigned MaxTrans = 4, - /// ID with which to send the transactions. - parameter int unsigned ID = 0, - /// Data width of bus, must be 32 or 64. - parameter int unsigned DataWidth = 32'b0, - parameter type reqrsp_req_t = logic, - parameter type reqrsp_rsp_t = logic, - parameter type axi_req_t = logic, - parameter type axi_rsp_t = logic -) ( - input logic clk_i, - input logic rst_ni, - input reqrsp_req_t reqrsp_req_i, - output reqrsp_rsp_t reqrsp_rsp_o, - output axi_req_t axi_req_o, - input axi_rsp_t axi_rsp_i -); - - localparam int unsigned CounterWidth = cc_pkg::idx_width(MaxTrans); - typedef logic [CounterWidth-1:0] cnt_t; - logic req_is_amo; - logic is_write; - - logic atomic_in_flight_d, atomic_in_flight_q; - cnt_t read_cnt_d, read_cnt_q; - cnt_t write_cnt_d, write_cnt_q; - logic [DataWidth-1:0] write_data; - - logic q_valid, q_ready; - logic q_valid_read, q_ready_read; - logic q_valid_write, q_ready_write; - - logic delay_r_for_atomic, delay_r_for_atomic_q; - logic r_valid, r_ready; - - // Globally no new transactions can be accepted if there is an unresolved - // atomic transactions and per channel we can not accept a new transaction iff: - // - The other channel has in-flight transactions (we can't guarantee the ordering). - // - The counter would overflow. - logic stall_read, dec_read_cnt, read_cnt_not_zero; - logic stall_write, dec_write_cnt, write_cnt_not_zero; - // AMos need to make sure that they don't re-use an in-flight ID. - logic stall_amo; - - assign req_is_amo = is_amo(reqrsp_req_i.q.amo); - assign is_write = reqrsp_req_i.q.write | req_is_amo | (reqrsp_req_i.q.amo == AMOSC); - - assign dec_read_cnt = r_valid & r_ready; - assign dec_write_cnt = axi_rsp_i.b_valid & axi_req_o.b_ready; - - // Read count isn't zero in this cycle. - assign read_cnt_not_zero = read_cnt_q > 1 | (read_cnt_q == 1 & ~dec_read_cnt); - // Write count isn't zero in this cycle. - assign write_cnt_not_zero = write_cnt_q > 1 | (write_cnt_q == 1 & ~dec_write_cnt); - // Reads and writes stall iff there are transactions of the othter type in place. - // See ordering rules above. - assign stall_write = is_write & (write_cnt_q == MaxTrans-1 | read_cnt_not_zero); - assign stall_read = !is_write & (read_cnt_q == MaxTrans-1 | write_cnt_not_zero); - // For atomics we additionally need to check whether there are any in-flight - // writes, as atomci are already write transactions this wouldn't be captured - // by the regular case. This makes sure that neither read nor writes are - // in-flight. - assign stall_amo = req_is_amo & write_cnt_not_zero; - - // Incoming handshake. Make sure we can accept the new transactions according - // to our rules. - always_comb begin - q_valid = reqrsp_req_i.q_valid; - reqrsp_rsp_o.q_ready = q_ready; - // Stall new transaction. - if (atomic_in_flight_q || stall_write || stall_read || stall_amo) begin - q_valid = 1'b0; - reqrsp_rsp_o.q_ready = 1'b0; - end - end - - assign q_valid_read = q_valid & ~is_write; - assign q_valid_write = q_valid & is_write; - assign q_ready = (q_valid_read & q_ready_read) | (q_valid_write & q_ready_write); - - // ------------------ - // Counter Management - // ------------------ - // Count the number of in-fligh reads. - `FF(read_cnt_q, read_cnt_d, '0) - // Count the number of in-fligh writes. - `FF(write_cnt_q, write_cnt_d, '0) - `FF(atomic_in_flight_q, atomic_in_flight_d, '0) - - always_comb begin - atomic_in_flight_d = atomic_in_flight_q; - read_cnt_d = read_cnt_q; - write_cnt_d = write_cnt_q; - - if (reqrsp_req_i.q_valid && reqrsp_rsp_o.q_ready) begin - // Set atomic in-flight flag if we sent an atomic. - if (req_is_amo) begin - atomic_in_flight_d = 1'b1; - read_cnt_d++; - end - - if (!is_write) read_cnt_d++; - else write_cnt_d++; - end - - // Reset atomic in-flight flag. - if (read_cnt_d == 0 && write_cnt_d == 0) begin - atomic_in_flight_d = 1'b0; - end - // Decrement the write counter again when the signals arrived. - if (dec_read_cnt) read_cnt_d--; - if (dec_write_cnt) write_cnt_d--; - end - - `ASSERT(WriteCntOverflow, (write_cnt_q == MaxTrans - 1) |=> !(write_cnt_q == 0)) - `ASSERT(ReadCntOverflow, (read_cnt_q == MaxTrans - 1) |=> !(read_cnt_q == 0)) - `ASSERT(WriteCntUnderflow, (write_cnt_q == 0) |=> !(write_cnt_q == MaxTrans - 1)) - `ASSERT(ReadCntUnderflow, (read_cnt_q == 0) |=> !(read_cnt_q == MaxTrans - 1)) - - // ------------- - // Read Channel - // ------------- - - // AXI read bus assignment. - assign axi_req_o.ar.addr = reqrsp_req_i.q.addr; - assign axi_req_o.ar.size = {1'b0, reqrsp_req_i.q.size}; - assign axi_req_o.ar.burst = axi_pkg::BURST_INCR; - assign axi_req_o.ar.lock = (reqrsp_req_i.q.amo == AMOLR); - assign axi_req_o.ar.cache = axi_pkg::CACHE_MODIFIABLE; - assign axi_req_o.ar.id = ID; - assign axi_req_o.ar.user = reqrsp_req_i.q.user; - assign axi_req_o.ar_valid = q_valid_read; - assign q_ready_read = axi_rsp_i.ar_ready; - - // ------------- - // Write Channel - // ------------- - - // AXI write bus assignment. - assign axi_req_o.aw.addr = reqrsp_req_i.q.addr; - assign axi_req_o.aw.size = {1'b0, reqrsp_req_i.q.size}; - assign axi_req_o.aw.burst = axi_pkg::BURST_INCR; - assign axi_req_o.aw.lock = (reqrsp_req_i.q.amo == AMOSC); - assign axi_req_o.aw.cache = axi_pkg::CACHE_MODIFIABLE; - assign axi_req_o.aw.id = ID; - assign axi_req_o.aw.user = reqrsp_req_i.q.user; - assign axi_req_o.w.data = write_data; - assign axi_req_o.w.strb = reqrsp_req_i.q.strb; - assign axi_req_o.w.last = 1'b1; - assign axi_req_o.w.user = reqrsp_req_i.q.user; - - // Both channels need to handshake (independently). - cc_stream_fork #( - .NumOup (2) - ) i_stream_fork ( - .clk_i, - .rst_ni, - .clr_i (1'b0), - .valid_i (q_valid_write), - .ready_o (q_ready_write), - .valid_o ({axi_req_o.aw_valid, axi_req_o.w_valid}), - .ready_i ({axi_rsp_i.aw_ready, axi_rsp_i.w_ready}) - ); - - `ASSERT(AssertStability, q_valid_write && !q_ready_write |=> q_valid_write) - - // Atomic signalling. - assign axi_req_o.aw.atop = to_axi_amo(reqrsp_req_i.q.amo); - always_comb begin - write_data = reqrsp_req_i.q.data; - if (reqrsp_req_i.q.amo == AMOAnd) begin - // in this case we need to invert the data to get a "CLR" - write_data = ~reqrsp_req_i.q.data; - end - end - - // ----------- - // Return Path - // ----------- - // There is an atomic instruction present which didn't receive a full - // handshake on either the AW or W channel. We silence the R channel. - assign delay_r_for_atomic = q_valid_write & ~q_ready_write & req_is_amo; - - assign r_valid = axi_rsp_i.r_valid & ~delay_r_for_atomic_q; - assign axi_req_o.r_ready = r_ready & ~delay_r_for_atomic_q; - - // Delay the signal for one cycle. We will never get the R response in the - // same cycle as the request. (Except for when the W is after the AW and the R - // comes in the same cycle, we will loose a cycle latency) - `FF(delay_r_for_atomic_q, delay_r_for_atomic, '0) - - // As we can never have two read and write transactions in-flight (except for - // atomics) simultaneously return path arbitration becomes quite an simply an - // `or` between `r` and `b` channel. - assign reqrsp_rsp_o.p.error = (r_valid & axi_rsp_i.r.resp[1]) - | (axi_rsp_i.b_valid & axi_rsp_i.b.resp[1]); - - // In case we have an atomic instruction in-flight we don't pass on the - // b channel as we are just interested in the read data. The logic in this - // module will make sure that we only issue new instructions if the atomic has - // been fully resolved. - assign reqrsp_rsp_o.p_valid = r_valid | (~atomic_in_flight_q & axi_rsp_i.b_valid); - // In case we have an atomic in flight we need to delay the r response. In AXI - // they can come before the interface accepted the W beat, this would mess - // with the counters (underflow). - assign r_ready = reqrsp_req_i.p_ready & r_valid; - assign axi_req_o.b_ready = (reqrsp_req_i.p_ready | atomic_in_flight_q) & axi_rsp_i.b_valid; - - always_comb begin - reqrsp_rsp_o.p.data = '0; - // Normal case. - if (r_valid) reqrsp_rsp_o.p.data = axi_rsp_i.r.data; - // In case we got a B response and this wasn't an atomic, let's check - // if we need to signal an `exclusive error` i.e., check if the we got `RESP_EXOKAY`. - // In case we didn't, we set the response to `1` which signals a failed - // store conditional for the reqrsp interface. - if ((axi_rsp_i.b_valid && ~atomic_in_flight_q - && axi_rsp_i.b.resp != axi_pkg::RESP_EXOKAY)) begin - // Set all 32-bit words to 1 since we don't know the alignment - // and which bits are cut off by the core. - reqrsp_rsp_o.p.data = {DataWidth/32{32'h1}}; - end - end - - // AXI auxiliary signal - assign axi_req_o.aw.len = '0; - assign axi_req_o.aw.qos = 4'b0; - assign axi_req_o.aw.prot = 3'b0; - assign axi_req_o.aw.region = 4'b0; - assign axi_req_o.ar.len = '0; - assign axi_req_o.ar.qos = 4'b0; - assign axi_req_o.ar.prot = 3'b0; - assign axi_req_o.ar.region = 4'b0; - - // Assertions: - // Make sure that write is never set for AMOs. - `ASSERT(AMOWriteEnable, reqrsp_req_i.q_valid && - (reqrsp_req_i.q.amo != snitch_pkg::AMONone) |-> !reqrsp_req_i.q.write) - // Check that the data width is in the range of 32 or 64 bit. We didn't define - // any other bus widths so far. - `ASSERT_INIT(check_DataWidth, DataWidth inside {32, 64}) - `ASSERT_INIT(MaxTrans_greater_than_one, MaxTrans > 1) - // 1. Assert that the in-flight counters are never both 2+ == 2+, that would - // imply an illegal state. - -endmodule - -`include "reqrsp_interface/typedef.svh" -`include "reqrsp_interface/assign.svh" -`include "axi/typedef.svh" -`include "axi/assign.svh" - -module reqrsp_to_axi_intf #( - /// ID width which to send the transactions. - parameter int unsigned ID = 0, - /// AXI ID width. - parameter int unsigned AxiIdWidth = 32'd0, - /// AXI and REQRSP address width. - parameter int unsigned AddrWidth = 32'd0, - /// AXI and REQRSP data width. - parameter int unsigned DataWidth = 32'd0, - /// AXI and REQRSP user width. - parameter int unsigned UserWidth = 32'd0 -) ( - input logic clk_i, - input logic rst_ni, - REQRSP_BUS reqrsp, - AXI_BUS axi -); - - typedef logic [AddrWidth-1:0] addr_t; - typedef logic [DataWidth-1:0] data_t; - typedef logic [DataWidth/8-1:0] strb_t; - typedef logic [AxiIdWidth-1:0] id_t; - typedef logic [UserWidth-1:0] user_t; - - `REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t) - - `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t) - - `AXI_TYPEDEF_REQ_T(axi_req_t, aw_chan_t, w_chan_t, ar_chan_t) - `AXI_TYPEDEF_RESP_T(axi_rsp_t, b_chan_t, r_chan_t) - - reqrsp_req_t reqrsp_req; - reqrsp_rsp_t reqrsp_rsp; - - axi_req_t axi_req; - axi_rsp_t axi_rsp; - - reqrsp_to_axi #( - .DataWidth ( DataWidth ), - .reqrsp_req_t (reqrsp_req_t), - .reqrsp_rsp_t (reqrsp_rsp_t), - .axi_req_t (axi_req_t), - .axi_rsp_t (axi_rsp_t) - ) i_reqrsp_to_axi ( - .clk_i, - .rst_ni, - .reqrsp_req_i (reqrsp_req), - .reqrsp_rsp_o (reqrsp_rsp), - .axi_req_o (axi_req), - .axi_rsp_i (axi_rsp) - ); - - `REQRSP_ASSIGN_TO_REQ(reqrsp_req, reqrsp) - `REQRSP_ASSIGN_FROM_RESP(reqrsp, reqrsp_rsp) - - `AXI_ASSIGN_FROM_REQ(axi, axi_req) - `AXI_ASSIGN_TO_RESP(axi_rsp, axi) - -endmodule diff --git a/hw/reqrsp_interface/test/axi_to_reqrsp_tb.sv b/hw/reqrsp_interface/test/axi_to_reqrsp_tb.sv deleted file mode 100644 index 8b24968f95..0000000000 --- a/hw/reqrsp_interface/test/axi_to_reqrsp_tb.sv +++ /dev/null @@ -1,263 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Author: Florian Zaruba - -`include "reqrsp_interface/typedef.svh" -`include "reqrsp_interface/assign.svh" -`include "axi/typedef.svh" -`include "axi/assign.svh" - -module axi_to_reqrsp_tb import reqrsp_pkg::*; import snitch_pkg::*; #( - parameter int unsigned AW = 32, - parameter int unsigned DW = 32, - parameter int unsigned IW = 2, - parameter int unsigned UW = 2, - parameter int unsigned NrReads = 1000, - parameter int unsigned NrWrites = 1000 -); - - localparam time ClkPeriod = 10ns; - localparam time ApplTime = 2ns; - localparam time TestTime = 8ns; - - logic clk, rst_n; - - // interfaces - REQRSP_BUS #( - .ADDR_WIDTH ( AW ), - .DATA_WIDTH ( DW ) - ) slave (); - - REQRSP_BUS_DV #( - .ADDR_WIDTH ( AW ), - .DATA_WIDTH ( DW ) - ) slave_dv (clk); - - AXI_BUS #( - .AXI_ADDR_WIDTH ( AW ), - .AXI_DATA_WIDTH ( DW ), - .AXI_ID_WIDTH ( IW ), - .AXI_USER_WIDTH ( UW ) - ) master (); - - AXI_BUS_DV #( - .AXI_ADDR_WIDTH ( AW ), - .AXI_DATA_WIDTH ( DW ), - .AXI_ID_WIDTH ( IW ), - .AXI_USER_WIDTH ( UW ) - ) master_dv (clk); - - axi_to_reqrsp_intf #( - .AddrWidth (AW), - .DataWidth (DW), - .IdWidth (IW), - .UserWidth (UW), - .BufDepth (4) - ) dut ( - .clk_i (clk), - .rst_ni (rst_n), - .busy_o (), - .axi (master), - .reqrsp (slave) - ); - - `AXI_ASSIGN(master, master_dv) - `REQRSP_ASSIGN(slave_dv, slave) - - // ---------------- - // Clock generation - // ---------------- - initial begin - rst_n = 0; - repeat (3) begin - #(ClkPeriod/2) clk = 0; - #(ClkPeriod/2) clk = 1; - end - rst_n = 1; - forever begin - #(ClkPeriod/2) clk = 0; - #(ClkPeriod/2) clk = 1; - end - end - - // ------- - // Monitor - // ------- - typedef reqrsp_test::reqrsp_monitor #( - // Reqrsp bus interface paramaters; - .AW ( AW ), - .DW ( DW ), - // Stimuli application and test time - .TA ( ApplTime ), - .TT ( TestTime ) - ) reqrsp_monitor_t; - - reqrsp_monitor_t reqrsp_monitor = new (slave_dv); - // Reqrsp Monitor. - initial begin - @(posedge rst_n) - reqrsp_monitor.monitor(); - end - - // AXI Monitor - typedef axi_test::axi_monitor #( - // AXI interface parameters - .AW ( AW ), - .DW ( DW ), - .IW ( IW ), - .UW ( UW ), - // Stimuli application and test time - .TT ( TestTime ) - ) axi_monitor_t; - - axi_monitor_t axi_monitor = new (master_dv); - initial begin - @(posedge rst_n); - axi_monitor.monitor(); - end - - // ---------- - // Scoreboard - // ---------- - initial begin - automatic int unsigned id_cnt_read; - automatic int unsigned id_cnt_write; - forever begin - automatic reqrsp_test::req_t req; - automatic reqrsp_test::rsp_t rsp; - automatic axi_monitor_t::ax_beat_t ax; - automatic axi_monitor_t::b_beat_t b; - automatic axi_monitor_t::r_beat_t r; - automatic axi_monitor_t::w_beat_t w; - - reqrsp_monitor.req_mbx.get(req); - reqrsp_monitor.rsp_mbx.get(rsp); - - // Check that we have seen the appropriate transactions on the inputs. - if (req.write | is_amo(req.amo) | (req.amo == AMOSC)) begin - axi_monitor.aw_mbx.peek(ax); - axi_monitor.w_mbx.get(w); - // Invert bits as this is signalled as a clear condition on AXI. - if (req.amo == AMOAnd) begin - req.data = ~req.data; - end - assert(req.size == ax.ax_size) - else $error("[Write Size] Expected `%h` got `%h`", ax.ax_size, req.size); - assert(req.strb == w.w_strb) - else $error("[Write Strb] Expected `%h` got `%h`", w.w_strb, req.strb); - assert(req.data == w.w_data) - else $error("[Write Data] Expected `%h` got `%h`", w.w_data, req.data); - assert(req.write == (req.amo == AMONone)); - assert ( - req.addr == - axi_pkg::beat_addr(ax.ax_addr, ax.ax_size, ax.ax_len, ax.ax_burst, id_cnt_write) - ) else $error("[Write Addr] Expected `%h` got `%h`.", ax.ax_addr, req.addr); - - id_cnt_write++; - // Check SCs - assert(ax.ax_lock == (req.amo == AMOSC)) - else $error("[Write Amo] Expected `%h` got `%h`", ax.ax_lock, (req.amo == AMOSC)); - // Consume Rs for atomic instructions. - if (ax.ax_atop[5:4] == axi_pkg::ATOP_ATOMICLOAD || - ax.ax_atop inside {axi_pkg::ATOP_ATOMICSWAP, axi_pkg::ATOP_ATOMICCMP}) begin - axi_monitor.r_mbx.get(r); - assert(req.amo == from_axi_amo(ax.ax_atop)); - end - if (w.w_last) begin - axi_monitor.aw_mbx.get(ax); - axi_monitor.b_mbx.get(b); - id_cnt_write = 0; - assert(ax.ax_id == b.b_id); - end - end else begin - axi_monitor.ar_mbx.peek(ax); - axi_monitor.r_mbx.get(r); - assert(req.size == ax.ax_size) - else $error("[Read Size] Expected `%h` got `%h`", ax.ax_size, req.size); - assert(rsp.data == r.r_data) - else $error("[Read Data] Expected `%h` got `%h`", r.r_data, rsp.data); - assert(ax.ax_id == r.r_id); - assert(req.write == 0); - assert(ax.ax_lock == (req.amo == AMOLR)) - else $error("[Read Amo] Expected `%h` got `%h`", ax.ax_lock, (req.amo == AMOLR)); - assert( - req.addr == - axi_pkg::beat_addr(ax.ax_addr, ax.ax_size, ax.ax_len, ax.ax_burst, id_cnt_read) - ) else $error("[Read Addr] Expected `%h` got `%h`.", ax.ax_addr, req.addr); - id_cnt_read++; - if (r.r_last) begin - id_cnt_read = 0; - axi_monitor.ar_mbx.get(ax); - end - end - end - end - - // Check that all transcations ceased. - final begin - assert(axi_monitor.aw_mbx.num() == 0); - assert(axi_monitor.w_mbx.num() == 0); - assert(axi_monitor.b_mbx.num() == 0); - assert(axi_monitor.ar_mbx.num() == 0); - assert(axi_monitor.r_mbx.num() == 0); - end - - // ------ - // Driver - // ------ - // AXI Master - typedef axi_test::axi_rand_master #( - // AXI interface parameters - .AW ( AW ), - .DW ( DW ), - .IW ( IW ), - .UW ( UW ), - // Stimuli application and test time - .TA ( ApplTime ), - .TT ( TestTime ), - .MAX_READ_TXNS (10), - .MAX_WRITE_TXNS (10), - .AX_MIN_WAIT_CYCLES (0), - .AX_MAX_WAIT_CYCLES (20), - // Only incremental bursts are supported. - .AXI_BURST_FIXED (0), - // Limit the burst length, to reduce simulation time. - .AXI_MAX_BURST_LEN (10), - // Check for exclusive accesses and atops. - .AXI_EXCLS (1), - .AXI_ATOPS (1) - ) rand_axi_master_t; - - rand_axi_master_t axi_rand_master = new (master_dv); - - // AXI Random master. - initial begin - axi_rand_master.reset(); - @(posedge rst_n); - axi_rand_master.run(NrReads, NrWrites); - // Wait until all transactions have ceased. - repeat(1000) @(posedge clk); - $finish; - end - - typedef reqrsp_test::rand_reqrsp_slave #( - // Reqrsp bus interface paramaters; - .AW ( AW ), - .DW ( DW ), - // Stimuli application and test time - .TA ( ApplTime ), - .TT ( TestTime ) - ) reqrsp_rand_slave_t; - - reqrsp_rand_slave_t rand_reqrsp_slave = new (slave_dv); - - // Reqrsp Slave. - initial begin - rand_reqrsp_slave.reset(); - @(posedge rst_n); - rand_reqrsp_slave.run(); - end - -endmodule diff --git a/hw/reqrsp_interface/test/reqrsp_demux_tb.sv b/hw/reqrsp_interface/test/reqrsp_demux_tb.sv deleted file mode 100644 index 1639caba9e..0000000000 --- a/hw/reqrsp_interface/test/reqrsp_demux_tb.sv +++ /dev/null @@ -1,192 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Author: Florian Zaruba - -`include "reqrsp_interface/assign.svh" - -/// Testbench for `reqrsp_demux`. Random drivers on the slave and master ports -/// drive a random pattern. The monitors track all packets and the scoreboard -/// checks the integrity of the schedule and data. We test the demux on a fixed, -/// address-based routing scheme. That makes it deterministic which port should -/// have received the corresponding datum and we can use the scoreboard to track -/// this. -module reqrsp_demux_tb import reqrsp_pkg::*; #( - parameter int unsigned AW = 32, - parameter int unsigned DW = 32, - parameter int unsigned NrPorts = 4, - parameter int unsigned RespDepth = 2, - parameter int unsigned NrRandomTransactions = 1000 -); - localparam time ClkPeriod = 10ns; - localparam time ApplTime = 2ns; - localparam time TestTime = 8ns; - localparam int unsigned SelectWidth = cc_pkg::idx_width(NrPorts); - typedef logic [SelectWidth-1:0] select_t; - logic clk, rst_n; - select_t slv_select; - - REQRSP_BUS #( - .ADDR_WIDTH ( AW ), - .DATA_WIDTH ( DW ) - ) master (); - - REQRSP_BUS_DV #( - .ADDR_WIDTH ( AW ), - .DATA_WIDTH ( DW ) - ) master_dv (clk); - - REQRSP_BUS #( - .ADDR_WIDTH ( AW ), - .DATA_WIDTH ( DW ) - ) slave [NrPorts](); - - REQRSP_BUS_DV #( - .ADDR_WIDTH ( AW ), - .DATA_WIDTH ( DW ) - ) slave_dv [NrPorts] (clk); - - reqrsp_demux_intf #( - .NrPorts (NrPorts), - .AddrWidth (AW), - .DataWidth (DW), - .RespDepth (RespDepth) - ) dut ( - .clk_i (clk), - .rst_ni (rst_n), - .slv_select_i (slv_select), - .slv (master), - .mst (slave) - ); - - assign slv_select = master.q_addr % NrPorts; - - `REQRSP_ASSIGN(master, master_dv) - for (genvar i = 0; i < NrPorts; i++) begin : gen_if_assignment - `REQRSP_ASSIGN(slave_dv[i], slave[i]) - end - - // ---------------- - // Clock generation - // ---------------- - initial begin - rst_n = 0; - repeat (3) begin - #(ClkPeriod/2) clk = 0; - #(ClkPeriod/2) clk = 1; - end - rst_n = 1; - forever begin - #(ClkPeriod/2) clk = 0; - #(ClkPeriod/2) clk = 1; - end - end - - // ------- - // Monitor - // ------- - typedef reqrsp_test::reqrsp_monitor #( - // Reqrsp bus interface paramaters; - .AW ( AW ), - .DW ( DW ), - // Stimuli application and test time - .TA ( ApplTime ), - .TT ( TestTime ) - ) reqrsp_monitor_t; - - reqrsp_monitor_t reqrsp_mst_monitor = new (master_dv); - // Reqrsp Monitor. - initial begin - @(posedge rst_n); - reqrsp_mst_monitor.monitor(); - end - - reqrsp_monitor_t reqrsp_slv_monitor [NrPorts]; - for (genvar i = 0; i < NrPorts; i++) begin : gen_mst_mon - initial begin - reqrsp_slv_monitor[i] = new (slave_dv[i]); - @(posedge rst_n); - reqrsp_slv_monitor[i].monitor(); - end - end - - // ------ - // Driver - // ------ - typedef reqrsp_test::rand_reqrsp_slave #( - // Reqrsp bus interface paramaters; - .AW ( AW ), - .DW ( DW ), - // Stimuli application and test time - .TA ( ApplTime ), - .TT ( TestTime ) - ) reqrsp_rand_slave_t; - - reqrsp_rand_slave_t rand_reqrsp_slave [NrPorts]; - for (genvar i = 0; i < NrPorts; i++) begin : gen_slv_driver - initial begin - rand_reqrsp_slave[i] = new (slave_dv[i]); - rand_reqrsp_slave[i].reset(); - @(posedge rst_n); - rand_reqrsp_slave[i].run(); - end - end - - typedef reqrsp_test::rand_reqrsp_master #( - // Reqrsp bus interface paramaters; - .AW ( AW ), - .DW ( DW ), - // Stimuli application and test time - .TA ( ApplTime ), - .TT ( TestTime ) - ) reqrsp_rand_master_t; - - reqrsp_rand_master_t rand_reqrsp_master = new (master_dv); - - // Reqrsp master. - initial begin - rand_reqrsp_master.reset(); - @(posedge rst_n); - rand_reqrsp_master.run(NrRandomTransactions); - // Wait until all transactions have ceased. - repeat(1000) @(posedge clk); - $finish; - end - - // ---------- - // Scoreboard - // ---------- - initial begin - forever begin - automatic reqrsp_test::req_t req; - automatic reqrsp_test::req_t req_slv; - automatic reqrsp_test::rsp_t rsp; - automatic reqrsp_test::rsp_t rsp_slv; - automatic select_t select; - reqrsp_mst_monitor.req_mbx.get(req); - reqrsp_mst_monitor.rsp_mbx.get(rsp); - // Check that for each master transaction we see a slave transaction on - // the right port. - // The slave select in the testbench is steered based on the - // (randomized) address. - select = req.addr % NrPorts; - reqrsp_slv_monitor[select].req_mbx.get(req_slv); - reqrsp_slv_monitor[select].rsp_mbx.get(rsp_slv); - assert(req_slv.do_compare(req)); - assert(rsp_slv.do_compare(rsp)); - end - end - - // Check that we have associated all transactions. - final begin - assert(reqrsp_mst_monitor.req_mbx.num() == 0); - assert(reqrsp_mst_monitor.rsp_mbx.num() == 0); - for (int i = 0; i < NrPorts; i++) begin - assert(reqrsp_slv_monitor[i].req_mbx.num() == 0); - assert(reqrsp_slv_monitor[i].rsp_mbx.num() == 0); - end - $display("Checked for non-empty mailboxes."); - end - -endmodule diff --git a/hw/reqrsp_interface/test/reqrsp_idempotent_tb.sv b/hw/reqrsp_interface/test/reqrsp_idempotent_tb.sv deleted file mode 100644 index 5195b8b9ac..0000000000 --- a/hw/reqrsp_interface/test/reqrsp_idempotent_tb.sv +++ /dev/null @@ -1,192 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Author: Florian Zaruba - -`include "reqrsp_interface/assign.svh" - -/// Testbench for all idempotent modules i.e., module which do not alter data -/// but only the handshaking. -module reqrsp_idempotent_tb import reqrsp_pkg::*; #( - parameter int unsigned AW = 32, - parameter int unsigned DW = 32, - parameter int unsigned NrRandomTransactions = 1000, - /// Test Isochronous spill register. - parameter bit Iso = 1, - /// Test normal spill register. - parameter bit Cut = 0 -); - localparam time ClkPeriod = 10ns; - localparam time ApplTime = 2ns; - localparam time TestTime = 8ns; - - logic clk, rst_n; - - REQRSP_BUS #( - .ADDR_WIDTH ( AW ), - .DATA_WIDTH ( DW ) - ) master (); - - REQRSP_BUS_DV #( - .ADDR_WIDTH ( AW ), - .DATA_WIDTH ( DW ) - ) master_dv (clk); - - REQRSP_BUS #( - .ADDR_WIDTH ( AW ), - .DATA_WIDTH ( DW ) - ) slave (); - - REQRSP_BUS_DV #( - .ADDR_WIDTH ( AW ), - .DATA_WIDTH ( DW ) - ) slave_dv (clk); - - // Isochronous crossing. - if (Iso) begin : gen_iso_dut - // We only want to test that the module is properly wired up so we can put it - // in bypass which makes this testbench significantly easier as we do not need - // to generate a isochronous clock. The iso feature is tested in a separate - // testbench in the common_cells repository. - reqrsp_iso_intf #( - .AddrWidth (AW), - .DataWidth (DW), - .BypassReq (1), - .BypassRsp (1) - ) i_dut ( - .src_clk_i (clk), - .src_rst_ni (rst_n), - .src (master), - .dst_clk_i (clk), - .dst_rst_ni (rst_n), - .dst (slave) - ); - // Plain synchronous cuts. - end else if (Cut) begin : gen_cut_dut - reqrsp_cut_intf #( - .AddrWidth (AW), - .DataWidth (DW), - .BypassReq (0), - .BypassRsp (0) - ) i_dut ( - .clk_i (clk), - .rst_ni (rst_n), - .slv (master), - .mst (slave) - ); - end - - `REQRSP_ASSIGN(master, master_dv) - `REQRSP_ASSIGN(slave_dv, slave) - - // ---------------- - // Clock generation - // ---------------- - initial begin - rst_n = 0; - repeat (3) begin - #(ClkPeriod/2) clk = 0; - #(ClkPeriod/2) clk = 1; - end - rst_n = 1; - forever begin - #(ClkPeriod/2) clk = 0; - #(ClkPeriod/2) clk = 1; - end - end - - // ------- - // Monitor - // ------- - typedef reqrsp_test::reqrsp_monitor #( - // Reqrsp bus interface paramaters; - .AW ( AW ), - .DW ( DW ), - // Stimuli application and test time - .TA ( ApplTime ), - .TT ( TestTime ) - ) reqrsp_monitor_t; - - reqrsp_monitor_t reqrsp_mst_monitor = new (master_dv); - // Reqrsp Monitor. - initial begin - @(posedge rst_n); - reqrsp_mst_monitor.monitor(); - end - - reqrsp_monitor_t reqrsp_slv_monitor = new (slave_dv); - // Reqrsp Monitor. - initial begin - @(posedge rst_n); - reqrsp_slv_monitor.monitor(); - end - - // ------ - // Driver - // ------ - typedef reqrsp_test::rand_reqrsp_slave #( - // Reqrsp bus interface paramaters; - .AW ( AW ), - .DW ( DW ), - // Stimuli application and test time - .TA ( ApplTime ), - .TT ( TestTime ) - ) reqrsp_rand_slave_t; - - reqrsp_rand_slave_t rand_reqrsp_slave = new (slave_dv); - initial begin - rand_reqrsp_slave.reset(); - @(posedge rst_n); - rand_reqrsp_slave.run(); - end - - typedef reqrsp_test::rand_reqrsp_master #( - // Reqrsp bus interface paramaters; - .AW ( AW ), - .DW ( DW ), - // Stimuli application and test time - .TA ( ApplTime ), - .TT ( TestTime ) - ) reqrsp_rand_master_t; - - reqrsp_rand_master_t rand_reqrsp_master = new (master_dv); - - // Reqrsp master. - initial begin - rand_reqrsp_master.reset(); - @(posedge rst_n); - rand_reqrsp_master.run(NrRandomTransactions); - // Wait until all transactions have ceased. - repeat(1000) @(posedge clk); - $finish; - end - - // ---------- - // Scoreboard - // ---------- - initial begin - forever begin - automatic reqrsp_test::req_t req; - automatic reqrsp_test::req_t req_slv; - automatic reqrsp_test::rsp_t rsp; - automatic reqrsp_test::rsp_t rsp_slv; - reqrsp_mst_monitor.req_mbx.get(req); - reqrsp_mst_monitor.rsp_mbx.get(rsp); - reqrsp_slv_monitor.req_mbx.get(req_slv); - reqrsp_slv_monitor.rsp_mbx.get(rsp_slv); - assert(req_slv.do_compare(req)); - assert(rsp_slv.do_compare(rsp)); - end - end - - // Check that we have associated all transactions. - final begin - assert(reqrsp_mst_monitor.req_mbx.num() == 0); - assert(reqrsp_mst_monitor.rsp_mbx.num() == 0); - assert(reqrsp_slv_monitor.req_mbx.num() == 0); - assert(reqrsp_slv_monitor.rsp_mbx.num() == 0); - $display("Checked for non-empty mailboxes."); - end - -endmodule diff --git a/hw/reqrsp_interface/test/reqrsp_mux_tb.sv b/hw/reqrsp_interface/test/reqrsp_mux_tb.sv deleted file mode 100644 index e72f9d6509..0000000000 --- a/hw/reqrsp_interface/test/reqrsp_mux_tb.sv +++ /dev/null @@ -1,210 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Author: Florian Zaruba - -`include "reqrsp_interface/assign.svh" - -/// Testbench for `reqrsp_mux`. Random drivers on the slave and master ports -/// drive a random pattern. The monitors track all packets and the scoreboard -/// tries to generate a legit schedule. If the testbench terminates and no -/// schedule could be found the request and response routing of the arbiter is -/// wrong. -module reqrsp_mux_tb import reqrsp_pkg::*; #( - parameter int unsigned AW = 32, - parameter int unsigned DW = 32, - parameter int unsigned NrPorts = 4, - parameter int unsigned RespDepth = 2, - parameter int unsigned RegisterReq = 1, - parameter int unsigned NrRandomTransactions = 100 -); - localparam time ClkPeriod = 10ns; - localparam time ApplTime = 2ns; - localparam time TestTime = 8ns; - - logic clk, rst_n; - - REQRSP_BUS #( - .ADDR_WIDTH ( AW ), - .DATA_WIDTH ( DW ) - ) master [NrPorts] (); - - REQRSP_BUS_DV #( - .ADDR_WIDTH ( AW ), - .DATA_WIDTH ( DW ) - ) master_dv [NrPorts] (clk); - - REQRSP_BUS #( - .ADDR_WIDTH ( AW ), - .DATA_WIDTH ( DW ) - ) slave (); - - REQRSP_BUS_DV #( - .ADDR_WIDTH ( AW ), - .DATA_WIDTH ( DW ) - ) slave_dv (clk); - - reqrsp_mux_intf #( - .NrPorts (NrPorts), - .AddrWidth (AW), - .DataWidth (DW), - .RespDepth (RespDepth), - .RegisterReq (RegisterReq) - ) dut ( - .clk_i (clk), - .rst_ni (rst_n), - .slv (master), - .mst (slave), - .idx_o (/*not connected*/) - ); - - `REQRSP_ASSIGN(slave_dv, slave) - for (genvar i = 0; i < NrPorts; i++) begin : gen_if_assignment - `REQRSP_ASSIGN(master[i], master_dv[i]) - end - - // ---------------- - // Clock generation - // ---------------- - initial begin - rst_n = 0; - repeat (3) begin - #(ClkPeriod/2) clk = 0; - #(ClkPeriod/2) clk = 1; - end - rst_n = 1; - forever begin - #(ClkPeriod/2) clk = 0; - #(ClkPeriod/2) clk = 1; - end - end - - // ------- - // Monitor - // ------- - typedef reqrsp_test::reqrsp_monitor #( - // Reqrsp bus interface paramaters; - .AW ( AW ), - .DW ( DW ), - // Stimuli application and test time - .TA ( ApplTime ), - .TT ( TestTime ) - ) reqrsp_monitor_t; - - reqrsp_monitor_t reqrsp_slv_monitor = new (slave_dv); - // Reqrsp Monitor. - initial begin - @(posedge rst_n); - reqrsp_slv_monitor.monitor(); - end - - reqrsp_monitor_t reqrsp_mst_monitor [NrPorts]; - for (genvar i = 0; i < NrPorts; i++) begin : gen_mst_mon - initial begin - reqrsp_mst_monitor[i] = new (master_dv[i]); - @(posedge rst_n); - reqrsp_mst_monitor[i].monitor(); - end - end - - // ------ - // Driver - // ------ - typedef reqrsp_test::rand_reqrsp_master #( - // Reqrsp bus interface paramaters; - .AW ( AW ), - .DW ( DW ), - // Stimuli application and test time - .TA ( ApplTime ), - .TT ( TestTime ) - ) reqrsp_rand_master_t; - - reqrsp_rand_master_t rand_reqrsp_master [NrPorts]; - for (genvar i = 0; i < NrPorts; i++) begin : gen_mst_driver - initial begin - rand_reqrsp_master[i] = new (master_dv[i]); - rand_reqrsp_master[i].reset(); - @(posedge rst_n); - rand_reqrsp_master[i].run(NrRandomTransactions); - end - end - - typedef reqrsp_test::rand_reqrsp_slave #( - // Reqrsp bus interface paramaters; - .AW ( AW ), - .DW ( DW ), - // Stimuli application and test time - .TA ( ApplTime ), - .TT ( TestTime ) - ) reqrsp_rand_slave_t; - - reqrsp_rand_slave_t rand_reqrsp_slave = new (slave_dv); - - // Reqrsp Slave. - initial begin - rand_reqrsp_slave.reset(); - @(posedge rst_n); - rand_reqrsp_slave.run(); - end - - // ---------- - // Scoreboard - // ---------- - // The arbiter is a bit more tricky to test as we do not, looking from - // outside, know where the arbitration decision actually went (because two - // exactly same requests can be issued and on the output port we have lost all - // information on which port this request originated). This scoreboard - // therefore takes a greedy approach. It tries to map each packet on the - // output to a corresponding packet observed on a input port. The first port - // that matches this will be assigned as the source and the monitor packets - // from this port will be removed. - // While the request does not necessarily must have come from that exact port, - // the exact order doesn't matter as long as all packets have been removed and - // all mailboxes are empty. - initial begin - automatic int unsigned nr_transactions = 0; - forever begin - automatic reqrsp_test::req_t req; - automatic reqrsp_test::rsp_t rsp; - automatic bit arb_found = 0; - reqrsp_slv_monitor.req_mbx.get(req); - reqrsp_slv_monitor.rsp_mbx.get(rsp); - nr_transactions++; - // Check that this transaction has been valid at one of the request - // ports. - for (int i = 0; i < NrPorts; i++) begin - // Check that the request mailbox contains at least one value, otherwise - // one early finishing port can stall the rest. Also, if the request is - // observeable on the output the input must have handshaked, so this is - // a safe operation. - if (reqrsp_mst_monitor[i].req_mbx.num() != 0) begin - automatic reqrsp_test::req_t req_inp; - automatic reqrsp_test::rsp_t rsp_inp; - reqrsp_mst_monitor[i].req_mbx.peek(req_inp); - reqrsp_mst_monitor[i].rsp_mbx.peek(rsp_inp); - if (req_inp.do_compare(req) && rsp_inp.do_compare(rsp)) begin - reqrsp_mst_monitor[i].req_mbx.get(req_inp); - reqrsp_mst_monitor[i].rsp_mbx.get(rsp_inp); - arb_found |= 1; - break; - end - end - end - - assert(arb_found) else $error("No arbitration found."); - if (nr_transactions == NrPorts * NrRandomTransactions) $finish; - end - end - - // Check that we have associated all transactions. - final begin - assert(reqrsp_slv_monitor.req_mbx.num() == 0); - assert(reqrsp_slv_monitor.rsp_mbx.num() == 0); - for (int i = 0; i < NrPorts; i++) begin - assert(reqrsp_mst_monitor[i].req_mbx.num() == 0); - assert(reqrsp_mst_monitor[i].rsp_mbx.num() == 0); - end - $display("Checked for non-empty mailboxes."); - end -endmodule diff --git a/hw/reqrsp_interface/test/reqrsp_to_axi_tb.sv b/hw/reqrsp_interface/test/reqrsp_to_axi_tb.sv deleted file mode 100644 index 183ff87ca4..0000000000 --- a/hw/reqrsp_interface/test/reqrsp_to_axi_tb.sv +++ /dev/null @@ -1,279 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Author: Florian Zaruba - -`include "reqrsp_interface/assign.svh" -`include "axi/assign.svh" - -/// Testbench for the request/response TB -module reqrsp_to_axi_tb import reqrsp_pkg::*; import snitch_pkg::*; #( - parameter int unsigned AW = 32, - parameter int unsigned DW = 32, - parameter int unsigned IW = 2, - parameter int unsigned UW = 2, - parameter int unsigned NrDirectedReads = 2000, - parameter int unsigned NrDirectedWrites = 2000, - parameter int unsigned NrRandomTransactions = 4000 -); - localparam time ClkPeriod = 10ns; - localparam time ApplTime = 2ns; - localparam time TestTime = 8ns; - - logic clk, rst_n; - - typedef logic [AW-1:0] addr_t; - typedef logic [DW-1:0] data_t; - typedef logic [DW/8-1:0] strb_t; - typedef logic [IW-1:0] id_t; - typedef logic [UW-1:0] user_t; - - // interfaces - REQRSP_BUS #( - .ADDR_WIDTH ( AW ), - .DATA_WIDTH ( DW ) - ) master (); - - REQRSP_BUS_DV #( - .ADDR_WIDTH ( AW ), - .DATA_WIDTH ( DW ) - ) master_dv (clk); - - AXI_BUS #( - .AXI_ADDR_WIDTH ( AW ), - .AXI_DATA_WIDTH ( DW ), - .AXI_ID_WIDTH ( IW ), - .AXI_USER_WIDTH ( UW ) - ) slave (); - - AXI_BUS_DV #( - .AXI_ADDR_WIDTH ( AW ), - .AXI_DATA_WIDTH ( DW ), - .AXI_ID_WIDTH ( IW ), - .AXI_USER_WIDTH ( UW ) - ) slave_dv (clk); - - reqrsp_to_axi_intf #( - .AxiIdWidth (IW), - .AddrWidth (AW), - .DataWidth (DW), - .UserWidth (UW) - ) i_reqrsp_to_axi ( - .clk_i (clk), - .rst_ni (rst_n), - .reqrsp (master), - .axi (slave) - ); - - `REQRSP_ASSIGN(master, master_dv) - `AXI_ASSIGN(slave_dv, slave) - // ---------------- - // Clock generation - // ---------------- - initial begin - rst_n = 0; - repeat (3) begin - #(ClkPeriod/2) clk = 0; - #(ClkPeriod/2) clk = 1; - end - rst_n = 1; - forever begin - #(ClkPeriod/2) clk = 0; - #(ClkPeriod/2) clk = 1; - end - end - - // ------- - // Monitor - // ------- - typedef reqrsp_test::reqrsp_monitor #( - // Reqrsp bus interface paramaters; - .AW ( AW ), - .DW ( DW ), - // Stimuli application and test time - .TA ( ApplTime ), - .TT ( TestTime ) - ) reqrsp_monitor_t; - - reqrsp_monitor_t reqrsp_monitor = new (master_dv); - // Reqrsp Monitor. - initial begin - @(posedge rst_n); - reqrsp_monitor.monitor(); - end - - // AXI Monitor - typedef axi_test::axi_monitor #( - // AXI interface parameters - .AW ( AW ), - .DW ( DW ), - .IW ( IW ), - .UW ( UW ), - // Stimuli application and test time - .TT ( TestTime ) - ) axi_monitor_t; - - axi_monitor_t axi_monitor = new (slave_dv); - initial begin - @(posedge rst_n); - axi_monitor.monitor(); - end - - // ---------- - // Scoreboard - // ---------- - initial begin - forever begin - automatic reqrsp_test::req_t req; - automatic reqrsp_test::rsp_t rsp; - automatic axi_monitor_t::ax_beat_t ax; - automatic axi_monitor_t::b_beat_t b; - automatic axi_monitor_t::r_beat_t r; - automatic axi_monitor_t::w_beat_t w; - reqrsp_monitor.req_mbx.get(req); - // check fields match - // Writes and atomics. - // For each "AXI" write (i.e. incl. ATOPs) on the reqrsp bus we want to see a `aw` beat. - if (req.write | is_amo(req.amo) | (req.amo == AMOSC)) begin - axi_monitor.aw_mbx.get(ax); - axi_monitor.w_mbx.get(w); - - if (req.amo != AMOAnd) begin - assert(w.w_data == req.data) - else $error("[Data Check] Expecting `%b` got `%b`", w.w_data, req.data); - end else begin - assert(w.w_data == (~req.data)) - else $error("[AMOAnd] Expecting `%b` got `%b`", w.w_data, req.data); - end - // Check byte strobe. - assert(w.w_strb == req.strb); - // Check exclusive access. - assert(req.amo != AMOSC || ax.ax_lock == 1); - axi_monitor.b_mbx.get(b); - reqrsp_monitor.rsp_mbx.get(rsp); - - // Check error flag. - assert(rsp.error == b.b_resp[1]) - else $error("[Write Resp] Expecting `%h` got `%h`.", b.b_resp[1], rsp.error); - // Check whether we are expecting an additional R response. - if (is_amo(req.amo)) begin - // Check that AMOs were correctly translated. - assert(ax.ax_atop == to_axi_amo(req.amo)) - else $error("Expecting `%b` got `%b`", to_axi_amo(req.amo), ax.ax_atop); - axi_monitor.r_mbx.get(r); - assert(rsp.data == r.r_data) - else $error("[Write Amo] Expecting `%h` got `%h`.", r.r_data, rsp.data); - end - // Reads - end else begin - axi_monitor.ar_mbx.get(ax); - axi_monitor.r_mbx.get(r); - - // Check exclusive access. - assert(req.amo != AMOLR || ax.ax_lock == 1); - reqrsp_monitor.rsp_mbx.get(rsp); - - // Check read data access. - assert(rsp.data == r.r_data) - else $error("Expecting `%h` got `%h` on read data.", r.r_data, rsp.data); - // Check error flag. - assert(rsp.error == r.r_resp[1]) - else $error("[Read Response] Expecting `%h` got `%h`.", r.r_resp[1], rsp.error); - end - assert(ax.ax_len == 0) - else $fatal("Testbench does not support bursts."); - assert(ax.ax_size == req.size); - assert(req.addr == ax.ax_addr) - else $error("Address does noit match. Expected `%h` got `%h`.", req.addr, ax.ax_addr); - end - end - - // Check that all transcations ceased. - final begin - assert(axi_monitor.aw_mbx.num() == 0); - assert(axi_monitor.w_mbx.num() == 0); - assert(axi_monitor.b_mbx.num() == 0); - assert(axi_monitor.ar_mbx.num() == 0); - assert(axi_monitor.r_mbx.num() == 0); - end - - // ------ - // Driver - // ------ - // AXI Driver - typedef axi_test::axi_rand_slave #( - // AXI interface parameters - .AW ( AW ), - .DW ( DW ), - .IW ( IW ), - .UW ( UW ), - // Stimuli application and test time - .TA ( ApplTime ), - .TT ( TestTime ), - .RAND_RESP (1), - .AX_MIN_WAIT_CYCLES (0), - .AX_MAX_WAIT_CYCLES (20) - ) rand_axi_slave_t; - - rand_axi_slave_t axi_rand_slave = new (slave_dv); - - typedef reqrsp_test::rand_reqrsp_master #( - // Reqrsp bus interface paramaters; - .AW ( AW ), - .DW ( DW ), - // Stimuli application and test time - .TA ( ApplTime ), - .TT ( TestTime ) - ) reqrsp_driver_t; - - reqrsp_driver_t rand_reqrsp_master = new (master_dv); - - // AXI side. - initial begin - axi_rand_slave.reset(); - @(posedge rst_n); - axi_rand_slave.run(); - end - - // Reqrsp master side. - initial begin - rand_reqrsp_master.reset(); - @(posedge rst_n); - // Directed testing. - // 1. Directed testing (read). - fork - repeat(NrDirectedReads) begin - automatic reqrsp_test::req_t req = new; - assert(req.randomize() with { amo == AMONone; write == 0;}); - rand_reqrsp_master.drv.send_req(req); - end - repeat (NrDirectedReads) begin - automatic reqrsp_test::rsp_t rsp; - rand_reqrsp_master.drv.recv_rsp(rsp); - end - join - // 2. Directed testing (write). - fork - repeat(NrDirectedWrites) begin - automatic reqrsp_test::req_t req = new; - assert(req.randomize() with { amo == AMONone; write == 1;}); - rand_reqrsp_master.drv.send_req(req); - end - repeat (NrDirectedWrites) begin - automatic reqrsp_test::rsp_t rsp; - rand_reqrsp_master.drv.recv_rsp(rsp); - end - join - // 3. Random testing. - rand_reqrsp_master.run(NrRandomTransactions); - $info("Rand reqrsp master finished. Waiting for completion."); - // Wait until req/rsp mailboxes are empty. - while (reqrsp_monitor.req_mbx.num() > 0 || reqrsp_monitor.rsp_mbx.num() > 0) begin - @(posedge clk); - end - $info("Finished Testing %d vectors", NrRandomTransactions + NrDirectedReads + NrDirectedWrites); - $finish; - end - -endmodule diff --git a/hw/snitch/.gitignore b/hw/snitch/.gitignore new file mode 100644 index 0000000000..640d5abdb9 --- /dev/null +++ b/hw/snitch/.gitignore @@ -0,0 +1,6 @@ +compile.tcl +transcript +*.log +*.lock +work +Bender.lock diff --git a/hw/snitch/include/snitch/typedef.svh b/hw/snitch/include/snitch/typedef.svh index 71a65663b3..0c7540f62a 100644 --- a/hw/snitch/include/snitch/typedef.svh +++ b/hw/snitch/include/snitch/typedef.svh @@ -8,33 +8,7 @@ `define SNITCH_TYPEDEF_SVH_ `include "reqrsp_interface/typedef.svh" - -//////////////////// -// Data interface // -//////////////////// - -`define SNITCH_DATA_REQ_CHAN_STRUCT(__data_width, __addr_width) \ - struct packed { \ - logic [``__addr_width``-1:0] addr; \ - logic write; \ - snitch_pkg::amo_op_e amo; \ - logic [``__data_width``-1:0] data; \ - logic [``__data_width``/8-1:0] strb; \ - logic [63:0] user; \ - snitch_pkg::size_t size; \ - } - -`define SNITCH_DATA_RSP_CHAN_STRUCT(__data_width) \ - struct packed { \ - logic [``__data_width``-1:0] data; \ - logic error; \ - } - -`define SNITCH_DATA_REQ_STRUCT(__data_width, __addr_width) \ - `GENERIC_REQRSP_REQ_STRUCT(`SNITCH_DATA_REQ_CHAN_STRUCT(__data_width, __addr_width)) - -`define SNITCH_DATA_RSP_STRUCT(__data_width) \ - `GENERIC_REQRSP_RSP_STRUCT(`SNITCH_DATA_RSP_CHAN_STRUCT(__data_width)) +`include "lsu_interface/typedef.svh" /////////////////////////// // Accelerator interface // @@ -58,10 +32,10 @@ } `define SNITCH_ACC_REQ_STRUCT(__data_width, __addr_width) \ - `GENERIC_REQRSP_REQ_STRUCT(`SNITCH_ACC_REQ_CHAN_STRUCT(__data_width, __addr_width)) + `REQRSP_REQ_STRUCT(`SNITCH_ACC_REQ_CHAN_STRUCT(__data_width, __addr_width)) `define SNITCH_ACC_RSP_STRUCT(__data_width) \ - `GENERIC_REQRSP_RSP_STRUCT(`SNITCH_ACC_RSP_CHAN_STRUCT(__data_width)) + `REQRSP_RSP_STRUCT(`SNITCH_ACC_RSP_CHAN_STRUCT(__data_width)) `define SNITCH_ACC_TYPEDEF_REQ_CHAN_T(__data_width, __addr_width) \ typedef `SNITCH_ACC_REQ_CHAN_STRUCT(__data_width, __addr_width) acc_req_chan_t; @@ -75,7 +49,7 @@ `define SNITCH_ACC_TYPEDEF_ALL(__data_width, __addr_width) \ `SNITCH_ACC_TYPEDEF_REQRSP_CHAN_ALL(__data_width, __addr_width) \ - `GENERIC_REQRSP_TYPEDEF_ALL(acc, acc_req_chan_t, acc_rsp_chan_t) + `REQRSP_TYPEDEF_ALL(acc, acc_req_chan_t, acc_rsp_chan_t) /////////////////////////// // Instruction interface // diff --git a/hw/snitch/src/snitch.sv b/hw/snitch/src/snitch.sv index 29f0aaf02a..043826d7a0 100644 --- a/hw/snitch/src/snitch.sv +++ b/hw/snitch/src/snitch.sv @@ -19,6 +19,8 @@ Top-level Snitch core. Parameters: BootAddr - Boot address of the core. IsaCfg - ISA configuration of the core. + NativeFpSupport - Floating point instructions are natively supported through the + accelerator interface, i.e., they have to be decoded by the core. AddrWidth - Physical Address width of the core. DataWidth - Data width of memory interface. VMSupport - Enable virtual memory support. @@ -62,8 +64,8 @@ Ports: f2i_wdata_i - FPSS-to-integer (F2I) packet. f2i_wvalid_i - F2I valid. f2i_wready_o - F2I ready. - data_req_o - Data interface (outgoing). Transactions need to be handled strictly in-order. - data_rsp_i - Data interface (incoming). Transactions need to be handled strictly in-order. + lsu_req_o - LSU interface (outgoing). Transactions need to be handled strictly in-order. + lsu_rsp_i - LSU interface (incoming). Transactions need to be handled strictly in-order. ptw_req_o - Address translation interface (outgoing). ptw_rsp_i - Address translation interface (incoming). fpu_rnd_mode_o - FPU control interface, rounding mode. @@ -75,9 +77,14 @@ Ports: barrier_o - Signals core's arrival on a cluster hardware barrier. barrier_i - Signals to the core that it can depart from a cluster hardware barrier. */ -module snitch import snitch_pkg::*; import riscv_instr::*; #( +module snitch + import snitch_pkg::*; + import lsu_pkg::*; + import snitch_riscv_instr::*; +#( parameter logic [31:0] BootAddr = 32'h0000_1000, parameter isa_cfg_t IsaCfg = '0, + parameter bit NativeFpSupport = 1'b0, parameter int unsigned AddrWidth = 48, parameter int unsigned DataWidth = 64, parameter bit VMSupport = 1, @@ -102,14 +109,17 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( localparam type x_register_t = `CV_X_IF_REGISTER_STRUCT(XifIdWidth), localparam type x_commit_t = `CV_X_IF_COMMIT_STRUCT(XifIdWidth), localparam type x_result_t = `CV_X_IF_RESULT_STRUCT(XifIdWidth), - localparam type dreq_t = `SNITCH_DATA_REQ_STRUCT(DataWidth, AddrWidth), - localparam type drsp_t = `SNITCH_DATA_RSP_STRUCT(DataWidth), + localparam type lsu_req_t = `LSU_REQ_STRUCT(DataWidth, AddrWidth, UserWidth), + localparam type lsu_rsp_t = `LSU_RSP_STRUCT(DataWidth), localparam type ptw_req_t = `SNITCH_PTW_REQ_STRUCT(AddrWidth), localparam type ptw_rsp_t = `SNITCH_PTW_RSP_STRUCT(AddrWidth) ) ( input logic clk_i, input logic rst_i, - input logic [31:0] hart_id_i, + // pragma translate_off + output snitch_trace_t trace_o, + // pragma translate_on + input hart_id_t hart_id_i, input interrupts_t irq_i, output logic flush_i_valid_o, input logic flush_i_ready_i, @@ -135,8 +145,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( input logic [31:0] f2i_wdata_i, input logic f2i_wvalid_i, output logic f2i_wready_o, - output dreq_t data_req_o, - input drsp_t data_rsp_i, + output lsu_req_t lsu_req_o, + input lsu_rsp_t lsu_rsp_i, output ptw_req_t [1:0] ptw_req_o, input ptw_rsp_t [1:0] ptw_rsp_i, output fpnew_pkg::roundmode_e fpu_rnd_mode_o, @@ -157,7 +167,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( localparam bit Xcopift = IsaCfg.Xcopift; localparam bit RVF = IsaCfg.RVF; localparam bit RVD = IsaCfg.RVD; - localparam bit XF16 = IsaCfg.XF16; + localparam bit Zfh = IsaCfg.Zfh; localparam bit XF16ALT = IsaCfg.XF16ALT; localparam bit XF8 = IsaCfg.XF8; localparam bit XF8ALT = IsaCfg.XF8ALT; @@ -182,15 +192,20 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( `SNITCH_TYPEDEF_PA_T(AddrWidth) `SNITCH_TYPEDEF_L0_PTE_T(AddrWidth) - localparam int unsigned FLEN = calculate_flen(IsaCfg); - localparam bit FP_EN = calculate_fp_enable(IsaCfg); + localparam int unsigned FLEN = calculate_flen(IsaCfg); + localparam bit FpEn = calculate_fp_enable(IsaCfg); // Debug module's base address localparam logic [31:0] DmBaseAddress = 0; localparam int RegWidth = RVE ? 4 : 5; /// Total physical address portion. localparam int unsigned PPNSize = AddrWidth - PageShift; - localparam bit NSX = XF16 | XF16ALT | XF8 | XFVEC; + /// Non-ratified extensions are enabled + localparam bit NonRatifiedExtensions = + XF16ALT | XF8 | XF8ALT | XFVEC | XFDOTP | XFAUX | Xpulpabs | + Xpulpbitop | Xpulpbr | Xpulpclip | Xpulpmacsi | Xpulpminmax | + Xpulpslet | Xpulpvect | Xpulpvectshufflepack | Xcvmem | Xssr | + Xfrep | Xcopift | Xdma; // Number of read ports localparam int unsigned NumRfReadPorts = EnableXif | Xcvmem ? 3 : 2; @@ -1502,7 +1517,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( FMSUB_S, FNMSUB_S, FNMADD_S: begin - if (FP_EN && RVF + if (NativeFpSupport && RVF && (!(inst_rsp_i.data inside {FDIV_S, FSQRT_S}) || XDivSqrt)) begin write_rd = 1'b0; is_acc_inst = 1'b1; @@ -1536,7 +1551,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( VFSGNJX_R_S, VFCPKA_S_S, VFCPKA_S_D: begin - if (FP_EN && XFVEC && RVF && RVD + if (NativeFpSupport && XFVEC && RVF && RVD && (!(inst_rsp_i.data inside {VFDIV_S, VFDIV_R_S, VFSQRT_S}) || XDivSqrt)) begin write_rd = 1'b0; is_acc_inst = 1'b1; @@ -1546,7 +1561,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end VFSUM_S, VFNSUM_S: begin - if (FP_EN && XFVEC && FLEN >= 64 && XFDOTP && RVF) begin + if (NativeFpSupport && XFVEC && FLEN >= 64 && XFDOTP && RVF) begin write_rd = 1'b0; is_acc_inst = 1'b1; end else begin @@ -1568,7 +1583,10 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( FMSUB_D, FNMSUB_D, FNMADD_D: begin - if (FP_EN && RVD && (!(inst_rsp_i.data inside {FDIV_D, FSQRT_D}) || XDivSqrt)) begin + if ( + NativeFpSupport && RVD && + (!(inst_rsp_i.data inside {FDIV_D, FSQRT_D}) || XDivSqrt) + ) begin write_rd = 1'b0; is_acc_inst = 1'b1; end else begin @@ -1577,7 +1595,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end FCVT_S_D, FCVT_D_S: begin - if (FP_EN && RVF && RVD) begin + if (NativeFpSupport && RVF && RVD) begin write_rd = 1'b0; is_acc_inst = 1'b1; end else begin @@ -1599,11 +1617,11 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( FSGNJX_H, FMIN_H, FMAX_H: begin - if (FP_EN && XF16 && fcsr_q.fmode.dst == 1'b0 && + if (NativeFpSupport && Zfh && fcsr_q.fmode.dst == 1'b0 && (!(inst_rsp_i.data inside {FDIV_H, FSQRT_H}) || XDivSqrt)) begin write_rd = 1'b0; is_acc_inst = 1'b1; - end else if (FP_EN && XF16ALT && fcsr_q.fmode.dst == 1'b1 && + end else if (NativeFpSupport && XF16ALT && fcsr_q.fmode.dst == 1'b1 && (!(inst_rsp_i.data inside {VFDIV_H, VFDIV_R_H, VFSQRT_H}) || XDivSqrt)) begin write_rd = 1'b0; is_acc_inst = 1'b1; @@ -1613,7 +1631,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end FMACEX_S_H, FMULEX_S_H: begin - if (FP_EN && RVF && XF16 && XFAUX) begin + if (NativeFpSupport && RVF && Zfh && XFAUX) begin write_rd = 1'b0; is_acc_inst = 1'b1; end else begin @@ -1621,10 +1639,10 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end end FCVT_S_H: begin - if (FP_EN && RVF && XF16 && fcsr_q.fmode.src == 1'b0) begin + if (NativeFpSupport && RVF && Zfh && fcsr_q.fmode.src == 1'b0) begin write_rd = 1'b0; is_acc_inst = 1'b1; - end else if (FP_EN && RVF && XF16ALT && fcsr_q.fmode.src == 1'b1) begin + end else if (NativeFpSupport && RVF && XF16ALT && fcsr_q.fmode.src == 1'b1) begin write_rd = 1'b0; is_acc_inst = 1'b1; end else begin @@ -1632,10 +1650,10 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end end FCVT_H_S: begin - if (FP_EN && RVF && XF16 && fcsr_q.fmode.dst == 1'b0) begin + if (NativeFpSupport && RVF && Zfh && fcsr_q.fmode.dst == 1'b0) begin write_rd = 1'b0; is_acc_inst = 1'b1; - end else if (FP_EN && RVF && XF16ALT && fcsr_q.fmode.dst == 1'b1) begin + end else if (NativeFpSupport && RVF && XF16ALT && fcsr_q.fmode.dst == 1'b1) begin write_rd = 1'b0; is_acc_inst = 1'b1; end else begin @@ -1643,10 +1661,10 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end end FCVT_D_H: begin - if (FP_EN && RVD && XF16 && fcsr_q.fmode.src == 1'b0) begin + if (NativeFpSupport && RVD && Zfh && fcsr_q.fmode.src == 1'b0) begin write_rd = 1'b0; is_acc_inst = 1'b1; - end else if (FP_EN && RVD && XF16ALT && fcsr_q.fmode.src == 1'b1) begin + end else if (NativeFpSupport && RVD && XF16ALT && fcsr_q.fmode.src == 1'b1) begin write_rd = 1'b0; is_acc_inst = 1'b1; end else begin @@ -1654,10 +1672,10 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end end FCVT_H_D: begin - if (FP_EN && RVD && XF16 && fcsr_q.fmode.dst == 1'b0) begin + if (NativeFpSupport && RVD && Zfh && fcsr_q.fmode.dst == 1'b0) begin write_rd = 1'b0; is_acc_inst = 1'b1; - end else if (FP_EN && RVD && XF16ALT && fcsr_q.fmode.dst == 1'b1) begin + end else if (NativeFpSupport && RVD && XF16ALT && fcsr_q.fmode.dst == 1'b1) begin write_rd = 1'b0; is_acc_inst = 1'b1; end else begin @@ -1665,7 +1683,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end end // FCVT_H_H: begin - // if (FP_EN && XF16 && XF16ALT && + // if (NativeFpSupport && Zfh && XF16ALT && // (fcsr_q.fmode.src != fcsr_q.fmode.dst)) begin // write_rd = 1'b0; // is_acc_inst = 1'b1; @@ -1698,8 +1716,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( VFSGNJN_R_H, VFSGNJX_H, VFSGNJX_R_H: begin - if (FP_EN && XFVEC && FLEN >= 32) begin - if (XF16 && fcsr_q.fmode.dst == 1'b0 && + if (NativeFpSupport && XFVEC && FLEN >= 32) begin + if (Zfh && fcsr_q.fmode.dst == 1'b0 && (!(inst_rsp_i.data inside {VFDIV_H, VFDIV_R_H, VFSQRT_H}) || XDivSqrt)) begin write_rd = 1'b0; is_acc_inst = 1'b1; @@ -1716,8 +1734,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end VFSUM_H, VFNSUM_H: begin - if (FP_EN && XFVEC && FLEN >= 64 && XFDOTP) begin - if ((XF16 && fcsr_q.fmode.src == 1'b0) || + if (NativeFpSupport && XFVEC && FLEN >= 64 && XFDOTP) begin + if ((Zfh && fcsr_q.fmode.src == 1'b0) || (XF16ALT && fcsr_q.fmode.src == 1'b1)) begin write_rd = 1'b0; is_acc_inst = 1'b1; @@ -1730,7 +1748,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end VFCVT_D_S, VFCVTU_D_S: begin - if (FP_EN && XFVEC && RVF && FLEN >= 32) begin + if (NativeFpSupport && XFVEC && RVF && FLEN >= 32) begin if (RVF && RVD) begin write_rd = 1'b0; is_acc_inst = 1'b1; @@ -1745,8 +1763,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( VFCPKB_H_S, VFCVT_H_S, VFCVTU_H_S: begin - if (FP_EN && XFVEC && RVF && FLEN >= 32) begin - if (XF16 && fcsr_q.fmode.dst == 1'b0) begin + if (NativeFpSupport && XFVEC && RVF && FLEN >= 32) begin + if (Zfh && fcsr_q.fmode.dst == 1'b0) begin write_rd = 1'b0; is_acc_inst = 1'b1; end else if (XF16ALT && fcsr_q.fmode.dst == 1'b1) begin @@ -1761,8 +1779,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end VFCVT_S_H, VFCVTU_S_H: begin - if (FP_EN && XFVEC && RVF && FLEN >= 32) begin - if (XF16 && fcsr_q.fmode.src == 1'b0) begin + if (NativeFpSupport && XFVEC && RVF && FLEN >= 32) begin + if (Zfh && fcsr_q.fmode.src == 1'b0) begin write_rd = 1'b0; is_acc_inst = 1'b1; end else if (XF16ALT && fcsr_q.fmode.src == 1'b1) begin @@ -1777,8 +1795,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end VFCPKA_H_D, VFCPKB_H_D: begin - if (FP_EN && XFVEC && RVD && FLEN >= 32) begin - if (XF16 && fcsr_q.fmode.dst == 1'b0) begin + if (NativeFpSupport && XFVEC && RVD && FLEN >= 32) begin + if (Zfh && fcsr_q.fmode.dst == 1'b0) begin write_rd = 1'b0; is_acc_inst = 1'b1; end else if (XF16ALT && fcsr_q.fmode.dst == 1'b1) begin @@ -1793,7 +1811,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end VFCVT_H_H, VFCVTU_H_H: begin - if (FP_EN && XFVEC && RVF && XF16 && XF16ALT && FLEN >= 32) begin + if (NativeFpSupport && XFVEC && RVF && Zfh && XF16ALT && FLEN >= 32) begin if (fcsr_q.fmode.src != fcsr_q.fmode.dst) begin write_rd = 1'b0; is_acc_inst = 1'b1; @@ -1810,8 +1828,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( VFNDOTPEX_S_R_H, VFSUMEX_S_H, VFNSUMEX_S_H: begin - if (FP_EN && XFVEC && FLEN >= 64 && XFDOTP && RVF) begin - if ((XF16 && fcsr_q.fmode.src == 1'b0) || + if (NativeFpSupport && XFVEC && FLEN >= 64 && XFDOTP && RVF) begin + if ((Zfh && fcsr_q.fmode.src == 1'b0) || (XF16ALT && fcsr_q.fmode.src == 1'b1)) begin write_rd = 1'b0; is_acc_inst = 1'b1; @@ -1837,10 +1855,10 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( FMSUB_B, FNMSUB_B, FNMADD_B: begin - if (FP_EN && XF8 && fcsr_q.fmode.dst == 1'b0) begin + if (NativeFpSupport && XF8 && fcsr_q.fmode.dst == 1'b0) begin write_rd = 1'b0; is_acc_inst = 1'b1; - end else if (FP_EN && XF8ALT && fcsr_q.fmode.dst == 1'b1) begin + end else if (NativeFpSupport && XF8ALT && fcsr_q.fmode.dst == 1'b1) begin write_rd = 1'b0; is_acc_inst = 1'b1; end else begin @@ -1849,7 +1867,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end FMACEX_S_B, FMULEX_S_B: begin - if (FP_EN && RVF && XF16 && XFAUX) begin + if (NativeFpSupport && RVF && Zfh && XFAUX) begin write_rd = 1'b0; is_acc_inst = 1'b1; end else begin @@ -1857,10 +1875,10 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end end FCVT_S_B: begin - if (FP_EN && RVF && XF8 && fcsr_q.fmode.src == 1'b0) begin + if (NativeFpSupport && RVF && XF8 && fcsr_q.fmode.src == 1'b0) begin write_rd = 1'b0; is_acc_inst = 1'b1; - end else if (FP_EN && RVF && XF8ALT && fcsr_q.fmode.src == 1'b1) begin + end else if (NativeFpSupport && RVF && XF8ALT && fcsr_q.fmode.src == 1'b1) begin write_rd = 1'b0; is_acc_inst = 1'b1; end else begin @@ -1868,10 +1886,10 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end end FCVT_B_S: begin - if (FP_EN && RVF && XF8 && fcsr_q.fmode.dst == 1'b0) begin + if (NativeFpSupport && RVF && XF8 && fcsr_q.fmode.dst == 1'b0) begin write_rd = 1'b0; is_acc_inst = 1'b1; - end else if (FP_EN && RVF && XF8ALT && fcsr_q.fmode.dst == 1'b1) begin + end else if (NativeFpSupport && RVF && XF8ALT && fcsr_q.fmode.dst == 1'b1) begin write_rd = 1'b0; is_acc_inst = 1'b1; end else begin @@ -1879,10 +1897,10 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end end FCVT_D_B: begin - if (FP_EN && RVD && XF8 && fcsr_q.fmode.src == 1'b0) begin + if (NativeFpSupport && RVD && XF8 && fcsr_q.fmode.src == 1'b0) begin write_rd = 1'b0; is_acc_inst = 1'b1; - end else if (FP_EN && RVD && XF8ALT && fcsr_q.fmode.src == 1'b1) begin + end else if (NativeFpSupport && RVD && XF8ALT && fcsr_q.fmode.src == 1'b1) begin write_rd = 1'b0; is_acc_inst = 1'b1; end else begin @@ -1890,10 +1908,10 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end end FCVT_B_D: begin - if (FP_EN && RVD && XF8 && fcsr_q.fmode.dst == 1'b0) begin + if (NativeFpSupport && RVD && XF8 && fcsr_q.fmode.dst == 1'b0) begin write_rd = 1'b0; is_acc_inst = 1'b1; - end else if (FP_EN && RVF && XF8ALT && fcsr_q.fmode.dst == 1'b1) begin + end else if (NativeFpSupport && RVF && XF8ALT && fcsr_q.fmode.dst == 1'b1) begin write_rd = 1'b0; is_acc_inst = 1'b1; end else begin @@ -1901,10 +1919,10 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end end FCVT_H_B: begin - if (FP_EN) begin + if (NativeFpSupport) begin if ((XF8 && fcsr_q.fmode.src == 1'b0) || (XF8ALT && fcsr_q.fmode.src == 1'b1)) begin - if ((XF16 && fcsr_q.fmode.dst == 1'b0) || + if ((Zfh && fcsr_q.fmode.dst == 1'b0) || (XF16ALT && fcsr_q.fmode.dst == 1'b1)) begin write_rd = 1'b0; is_acc_inst = 1'b1; @@ -1919,8 +1937,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end end FCVT_B_H: begin - if (FP_EN) begin - if ((XF16 && fcsr_q.fmode.src == 1'b0) || + if (NativeFpSupport) begin + if ((Zfh && fcsr_q.fmode.src == 1'b0) || (XF16ALT && fcsr_q.fmode.src == 1'b1)) begin if ((XF8 && fcsr_q.fmode.dst == 1'b0) || (XF8ALT && fcsr_q.fmode.dst == 1'b1)) begin @@ -1960,7 +1978,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( VFSGNJN_R_B, VFSGNJX_B, VFSGNJX_R_B: begin - if (FP_EN && XFVEC && XF8 && FLEN >= 16 + if (NativeFpSupport && XFVEC && XF8 && FLEN >= 16 && (!(inst_rsp_i.data inside {VFDIV_B, VFDIV_R_B, VFSQRT_B}) || XDivSqrt)) begin write_rd = 1'b0; is_acc_inst = 1'b1; @@ -1970,7 +1988,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end VFSUM_B, VFNSUM_B: begin - if (FP_EN && XFVEC && FLEN >= 32 && XFDOTP) begin + if (NativeFpSupport && XFVEC && FLEN >= 32 && XFDOTP) begin if ((XF8 && fcsr_q.fmode.src == 1'b0) || (XF8ALT && fcsr_q.fmode.src == 1'b1)) begin write_rd = 1'b0; @@ -1988,7 +2006,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( VFCPKB_B_S, VFCPKC_B_S, VFCPKD_B_S: begin - if (FP_EN && XFVEC && RVF && FLEN >= 16) begin + if (NativeFpSupport && XFVEC && RVF && FLEN >= 16) begin if (XF8 && fcsr_q.fmode.dst == 1'b0) begin write_rd = 1'b0; is_acc_inst = 1'b1; @@ -2004,7 +2022,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end VFCVT_S_B, VFCVTU_S_B: begin - if (FP_EN && XFVEC && RVF && FLEN >= 16) begin + if (NativeFpSupport && XFVEC && RVF && FLEN >= 16) begin if (XF8 && fcsr_q.fmode.src == 1'b0) begin write_rd = 1'b0; is_acc_inst = 1'b1; @@ -2022,7 +2040,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( VFCPKB_B_D, VFCPKC_B_D, VFCPKD_B_D: begin - if (FP_EN && XFVEC && RVD && FLEN >= 16) begin + if (NativeFpSupport && XFVEC && RVD && FLEN >= 16) begin if (XF8 && fcsr_q.fmode.dst == 1'b0) begin write_rd = 1'b0; is_acc_inst = 1'b1; @@ -2038,8 +2056,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end VFCVT_B_H, VFCVTU_B_H: begin - if (FP_EN && XFVEC && FLEN >= 16) begin - if ((XF16 && fcsr_q.fmode.src == 1'b0) || + if (NativeFpSupport && XFVEC && FLEN >= 16) begin + if ((Zfh && fcsr_q.fmode.src == 1'b0) || (XF16ALT && fcsr_q.fmode.src == 1'b1)) begin if ((XF8 && fcsr_q.fmode.dst == 1'b0) || (XF8ALT && fcsr_q.fmode.dst == 1'b1)) begin @@ -2057,10 +2075,10 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end VFCVT_H_B, VFCVTU_H_B: begin - if (FP_EN && XFVEC && FLEN >= 16) begin + if (NativeFpSupport && XFVEC && FLEN >= 16) begin if ((XF8 && fcsr_q.fmode.src == 1'b0) || (XF8ALT && fcsr_q.fmode.src == 1'b1)) begin - if ((XF16 && fcsr_q.fmode.dst == 1'b0) || + if ((Zfh && fcsr_q.fmode.dst == 1'b0) || (XF16ALT && fcsr_q.fmode.dst == 1'b1)) begin write_rd = 1'b0; is_acc_inst = 1'b1; @@ -2076,7 +2094,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end VFCVT_B_B, VFCVTU_B_B: begin - if (FP_EN && XFVEC && RVF && XF8 && XF8ALT && FLEN >= 16) begin + if (NativeFpSupport && XFVEC && RVF && XF8 && XF8ALT && FLEN >= 16) begin if (fcsr_q.fmode.src != fcsr_q.fmode.dst) begin write_rd = 1'b0; is_acc_inst = 1'b1; @@ -2093,10 +2111,10 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( VFNDOTPEX_H_R_B, VFSUMEX_H_B, VFNSUMEX_H_B: begin - if (FP_EN && XFVEC && FLEN >= 32 && XFDOTP) begin + if (NativeFpSupport && XFVEC && FLEN >= 32 && XFDOTP) begin if ((XF8 && fcsr_q.fmode.src == 1'b0) || (XF8ALT && fcsr_q.fmode.src == 1'b1)) begin - if ((XF16 && fcsr_q.fmode.dst == 1'b0) || + if ((Zfh && fcsr_q.fmode.dst == 1'b0) || (XF16ALT && fcsr_q.fmode.dst == 1'b1)) begin write_rd = 1'b0; is_acc_inst = 1'b1; @@ -2118,7 +2136,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( FCLASS_D, FCVT_W_D, FCVT_WU_D: begin - if (FP_EN && RVD) begin + if (NativeFpSupport && RVD) begin write_rd = 1'b0; uses_rd = 1'b1; is_acc_inst = 1'b1; @@ -2135,7 +2153,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( FCVT_W_S, FCVT_WU_S, FMV_X_W: begin - if (FP_EN && RVF) begin + if (NativeFpSupport && RVF) begin write_rd = 1'b0; uses_rd = 1'b1; is_acc_inst = 1'b1; @@ -2158,7 +2176,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( VFGT_S, VFGT_R_S, VFCLASS_S: begin - if (FP_EN && XFVEC && RVF && FLEN >= 64) begin + if (NativeFpSupport && XFVEC && RVF && FLEN >= 64) begin write_rd = 1'b0; uses_rd = 1'b1; is_acc_inst = 1'b1; @@ -2175,12 +2193,12 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( FCVT_W_H, FCVT_WU_H, FMV_X_H: begin - if (FP_EN && XF16 && fcsr_q.fmode.src == 1'b0) begin + if (NativeFpSupport && Zfh && fcsr_q.fmode.src == 1'b0) begin write_rd = 1'b0; uses_rd = 1'b1; is_acc_inst = 1'b1; acc_register_rd = 1'b1; // No RS in GPR but RD in GPR, register in int scoreboard - end else if (FP_EN && XF16ALT && fcsr_q.fmode.src == 1'b1) begin + end else if (NativeFpSupport && XF16ALT && fcsr_q.fmode.src == 1'b1) begin write_rd = 1'b0; uses_rd = 1'b1; is_acc_inst = 1'b1; @@ -2203,8 +2221,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( VFGT_H, VFGT_R_H, VFCLASS_H: begin - if (FP_EN && XFVEC && FLEN >= 32) begin - if (XF16 && fcsr_q.fmode.dst == 1'b0) begin + if (NativeFpSupport && XFVEC && FLEN >= 32) begin + if (Zfh && fcsr_q.fmode.dst == 1'b0) begin write_rd = 1'b0; uses_rd = 1'b1; is_acc_inst = 1'b1; @@ -2222,8 +2240,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( VFMV_X_H, VFCVT_X_H, VFCVT_XU_H: begin - if (FP_EN && XFVEC && FLEN >= 32 && ~RVD) begin - if (XF16 && fcsr_q.fmode.src == 1'b0) begin + if (NativeFpSupport && XFVEC && FLEN >= 32 && ~RVD) begin + if (Zfh && fcsr_q.fmode.src == 1'b0) begin write_rd = 1'b0; uses_rd = 1'b1; is_acc_inst = 1'b1; @@ -2246,12 +2264,12 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( FCVT_W_B, FCVT_WU_B, FMV_X_B: begin - if (FP_EN && XF8 && fcsr_q.fmode.src == 1'b0) begin + if (NativeFpSupport && XF8 && fcsr_q.fmode.src == 1'b0) begin write_rd = 1'b0; uses_rd = 1'b1; is_acc_inst = 1'b1; acc_register_rd = 1'b1; // No RS in GPR but RD in GPR, register in int scoreboard - end else if (FP_EN && XF8ALT && fcsr_q.fmode.src == 1'b1) begin + end else if (NativeFpSupport && XF8ALT && fcsr_q.fmode.src == 1'b1) begin write_rd = 1'b0; uses_rd = 1'b1; is_acc_inst = 1'b1; @@ -2273,7 +2291,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( VFLE_R_B, VFGT_B, VFGT_R_B: begin - if (FP_EN && XFVEC && FLEN >= 16) begin + if (NativeFpSupport && XFVEC && FLEN >= 16) begin if (XF8 && fcsr_q.fmode.src == 1'b0) begin write_rd = 1'b0; uses_rd = 1'b1; @@ -2293,7 +2311,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( VFCLASS_B, VFCVT_X_B, VFCVT_XU_B: begin - if (FP_EN && XFVEC && FLEN >= 16 && ~RVD) begin + if (NativeFpSupport && XFVEC && FLEN >= 16 && ~RVD) begin if (XF8 && fcsr_q.fmode.src == 1'b0) begin write_rd = 1'b0; uses_rd = 1'b1; @@ -2313,7 +2331,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( // Double Precision Floating-Point FCVT_D_W, FCVT_D_WU: begin - if (FP_EN && RVD) begin + if (NativeFpSupport && RVD) begin opa_select = RegRs1; write_rd = 1'b0; is_acc_inst = 1'b1; @@ -2325,7 +2343,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( FMV_W_X, FCVT_S_W, FCVT_S_WU: begin - if (FP_EN && RVF) begin + if (NativeFpSupport && RVF) begin opa_select = RegRs1; write_rd = 1'b0; is_acc_inst = 1'b1; @@ -2337,11 +2355,11 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( FMV_H_X, FCVT_H_W, FCVT_H_WU: begin - if (FP_EN && XF16 && (fcsr_q.fmode.dst == 1'b0)) begin + if (NativeFpSupport && Zfh && (fcsr_q.fmode.dst == 1'b0)) begin opa_select = RegRs1; write_rd = 1'b0; is_acc_inst = 1'b1; - end else if (FP_EN && XF16ALT && (fcsr_q.fmode.dst == 1'b1)) begin + end else if (NativeFpSupport && XF16ALT && (fcsr_q.fmode.dst == 1'b1)) begin opa_select = RegRs1; write_rd = 1'b0; is_acc_inst = 1'b1; @@ -2353,8 +2371,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( VFMV_H_X, VFCVT_H_X, VFCVT_H_XU: begin - if (FP_EN && XFVEC && FLEN >= 32 && ~RVD) begin - if (XF16 && fcsr_q.fmode.dst == 1'b0) begin + if (NativeFpSupport && XFVEC && FLEN >= 32 && ~RVD) begin + if (Zfh && fcsr_q.fmode.dst == 1'b0) begin write_rd = 1'b0; is_acc_inst = 1'b1; end else if (XF16ALT && fcsr_q.fmode.dst == 1'b1) begin @@ -2369,11 +2387,11 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( FMV_B_X, FCVT_B_W, FCVT_B_WU: begin - if (FP_EN && XF8 && fcsr_q.fmode.dst == 1'b0) begin + if (NativeFpSupport && XF8 && fcsr_q.fmode.dst == 1'b0) begin opa_select = RegRs1; write_rd = 1'b0; is_acc_inst = 1'b1; - end else if (FP_EN && XF8ALT && fcsr_q.fmode.dst == 1'b1) begin + end else if (NativeFpSupport && XF8ALT && fcsr_q.fmode.dst == 1'b1) begin opa_select = RegRs1; write_rd = 1'b0; is_acc_inst = 1'b1; @@ -2385,7 +2403,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( VFMV_B_X, VFCVT_B_X, VFCVT_B_XU: begin - if (FP_EN && XFVEC && FLEN >= 16 && ~RVD) begin + if (NativeFpSupport && XFVEC && FLEN >= 16 && ~RVD) begin if (XF8 && fcsr_q.fmode.dst == 1'b0) begin write_rd = 1'b0; is_acc_inst = 1'b1; @@ -2457,7 +2475,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end endcase end else begin - if (Xfrep && FP_EN && (inst_rsp_i.data ==? FREP_O)) begin + if (Xfrep && (inst_rsp_i.data ==? FREP_O)) begin opa_select = RegRs1; write_rd = 1'b0; is_acc_inst = 1'b1; @@ -2675,7 +2693,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( // Floating-Point Load/Store // Single Precision Floating-Point FLW: begin - if (FP_EN && RVF) begin + if (NativeFpSupport && RVF) begin opa_select = RegRs1; opb_select = IImmediate; write_rd = 1'b0; @@ -2687,7 +2705,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end end FSW: begin - if (FP_EN && RVF) begin + if (NativeFpSupport && RVF) begin opa_select = RegRs1; opb_select = SFImmediate; write_rd = 1'b0; @@ -2700,7 +2718,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end // Double Precision Floating-Point FLD: begin - if (FP_EN && (RVD || XFVEC)) begin + if (NativeFpSupport && (RVD || XFVEC)) begin opa_select = RegRs1; opb_select = IImmediate; write_rd = 1'b0; @@ -2712,7 +2730,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end end FSD: begin - if (FP_EN && (RVD || XFVEC)) begin + if (NativeFpSupport && (RVD || XFVEC)) begin opa_select = RegRs1; opb_select = SFImmediate; write_rd = 1'b0; @@ -2725,7 +2743,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end // Half Precision Floating-Point FLH: begin - if (FP_EN && (XF16 || XF16ALT)) begin + if (NativeFpSupport && (Zfh || XF16ALT)) begin opa_select = RegRs1; opb_select = IImmediate; write_rd = 1'b0; @@ -2737,7 +2755,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end end FSH: begin - if (FP_EN && (XF16 || XF16ALT)) begin + if (NativeFpSupport && (Zfh || XF16ALT)) begin opa_select = RegRs1; opb_select = SFImmediate; write_rd = 1'b0; @@ -2750,7 +2768,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end // Quarter Precision Floating-Point FLB: begin - if (FP_EN && (XF8 || XF8ALT)) begin + if (NativeFpSupport && (XF8 || XF8ALT)) begin opa_select = RegRs1; opb_select = IImmediate; write_rd = 1'b0; @@ -2762,7 +2780,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end end FSB: begin - if (FP_EN && (XF8 || XF8ALT)) begin + if (NativeFpSupport && (XF8 || XF8ALT)) begin opa_select = RegRs1; opb_select = SFImmediate; write_rd = 1'b0; @@ -2871,7 +2889,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end FCVT_D_W_COPIFT, FCVT_D_WU_COPIFT: begin - if (FP_EN && RVD && Xcopift) begin + if (NativeFpSupport && RVD && Xcopift) begin write_rd = 1'b0; is_acc_inst = 1'b1; end else begin @@ -2902,7 +2920,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end else begin unique casez (inst_rsp_i.data) SCFGRI, FLT_D_COPIFT: begin - if (FP_EN && RVD && Xcopift) begin + if (NativeFpSupport && RVD && Xcopift) begin write_rd = 1'b0; is_acc_inst = 1'b1; end else if (Xssr) begin @@ -2996,6 +3014,15 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( if (unsupported_inst) begin if (EnableXif) begin write_rd = x_issue_ready_i & x_issue_valid_o & x_issue_resp_i.writeback; + // For XIF non-writeback instructions (e.g. FP ops whose destination lives + // in the coprocessor's own register file), rd in the encoding does NOT map + // to Snitch's integer register file. Setting uses_rd=1 (the default) would + // cause dst_ready to check sb_q[rd], which can be spuriously set by a + // preceding integer-writeback XIF instruction that happens to share the same + // register number (e.g. feq.d a5 sets sb_q[15] while fld fa5 also has + // rd=15). Only gate on the integer scoreboard when the result will actually + // be written back to Snitch's GPR. + uses_rd = x_issue_resp_i.writeback; opa_select = RegRs1; opb_select = RegRs2; @@ -3152,11 +3179,11 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( // C - Compressed extension | (0 << 2) // D - Double precsision floating-point extension - | ((FP_EN & RVD) << 3) + | (RVD << 3) // E - RV32E base ISA - | ((FP_EN & RVE) << 4) + | (RVE << 4) // F - Single precsision floating-point extension - | ((FP_EN & RVF) << 5) + | (RVF << 5) // I - RV32I/64I/128I base ISA | (1 << 8) // M - Integer Multiply/Divide extension @@ -3167,8 +3194,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( | (0 << 18) // U - User mode implemented | (0 << 20) - // X - Non-standard extensions present - | (((NSX & FP_EN) | Xdma | Xssr) << 23) + // X - Non-ratified extensions present + | (NonRatifiedExtensions << 23) // RV32 | (1 << 30); CSR_MHARTID: begin @@ -3215,7 +3242,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( CSR_MSTATUS: begin automatic snitch_pkg::status_rv32_t mstatus, mstatus_d; mstatus = '0; - if (FP_EN) begin + if (FpEn) begin mstatus.fs = snitch_pkg::XDirty; mstatus.sd = 1'b1; end @@ -3322,25 +3349,25 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end // F/D Extension CSR_FFLAGS: begin - if (FP_EN) begin + if (FpEn) begin csr_rvalue = {27'b0, fcsr_q.fflags}; if (!exception) fcsr_d.fflags = fpnew_pkg::status_t'(alu_result[4:0]); end else illegal_csr = 1'b1; end CSR_FRM: begin - if (FP_EN) begin + if (FpEn) begin csr_rvalue = {29'b0, fcsr_q.frm}; if (!exception) fcsr_d.frm = fpnew_pkg::roundmode_e'(alu_result[2:0]); end else illegal_csr = 1'b1; end CSR_FMODE: begin - if (FP_EN) begin + if (FpEn) begin csr_rvalue = {30'b0, fcsr_q.fmode}; if (!exception) fcsr_d.fmode = fpnew_pkg::fmt_mode_t'(alu_result[1:0]); end else illegal_csr = 1'b1; end CSR_FCSR: begin - if (FP_EN) begin + if (FpEn) begin csr_rvalue = {22'b0, fcsr_q}; if (!exception) fcsr_d = fcsr_t'(alu_result[9:0]); end else illegal_csr = 1'b1; @@ -3433,14 +3460,14 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end // Return from Environment. - if (inst_rsp_i.data == riscv_instr::MRET) begin + if (inst_rsp_i.data == snitch_riscv_instr::MRET) begin priv_lvl_d = mpp_q; ie_d[M] = pie_q[M]; pie_d[M] = 1'b1; mpp_d = snitch_pkg::PrivLvlU; // set default back to U-Mode end - if (inst_rsp_i.data == riscv_instr::SRET) begin + if (inst_rsp_i.data == snitch_riscv_instr::SRET) begin priv_lvl_d = snitch_pkg::priv_lvl_t'({1'b0, spp_q}); spp_d = 1'b0; end @@ -3471,6 +3498,43 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( end // pragma translate_on + // pragma translate_off + assign trace_o.pc_q = pc_q; + assign trace_o.priv_lvl_q = priv_lvl_q; + assign trace_o.instr = inst_rsp_i.data; + assign trace_o.extras.source = snitch_pkg::SrcSnitch; + assign trace_o.extras.stall = stall; + assign trace_o.extras.exception = exception; + assign trace_o.extras.rs1 = rs1; + assign trace_o.extras.rs2 = rs2; + assign trace_o.extras.rd = rd; + assign trace_o.extras.is_load = is_load; + assign trace_o.extras.is_store = is_store; + assign trace_o.extras.is_branch = is_branch; + assign trace_o.extras.pc_d = pc_d; + assign trace_o.extras.opa = opa; + assign trace_o.extras.opb = opb; + assign trace_o.extras.opa_select = opa_select; + assign trace_o.extras.opb_select = opb_select; + assign trace_o.extras.opc_select = opc_select; + assign trace_o.extras.write_rd = write_rd; + assign trace_o.extras.csr_addr = inst_rsp_i.data[31:20]; + assign trace_o.extras.writeback = gpr_wdata[0]; + assign trace_o.extras.gpr_rdata_1 = gpr_rdata[1]; + assign trace_o.extras.ls_size = ls_size; + assign trace_o.extras.ld_result_32 = ld_result[31:0]; + assign trace_o.extras.lsu_rd = lsu_rd; + assign trace_o.extras.retire_load = retire_load; + assign trace_o.extras.alu_result = alu_result; + assign trace_o.extras.ls_amo = ls_amo; + assign trace_o.extras.retire_acc = retire_acc; + assign trace_o.extras.acc_pid = acc_rsp_i.p.id; + assign trace_o.extras.acc_pdata_32 = acc_rsp_i.p.data[31:0]; + assign trace_o.extras.fpu_offload = acc_rsp_i.q_ready && acc_req_o.q_valid && + acc_req_o.q.addr == FP_SS; + assign trace_o.extras.is_seq_insn = inst_rsp_i.data ==? FREP_O; + // pragma translate_on + // -------------------- // COPIFT Queue // -------------------- @@ -3752,16 +3816,14 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( // Do *not* issue request when a non-accelerator (CAQ-unrelated) stall is blocking progress. assign caq_qvalid = caq_ena & acc_rsp_i.q_ready & ~nonacc_stall; - snitch_lsu #( + lsu #( .AddrWidth (AddrWidth), .DataWidth (DataWidth), - .UserWidth (64), - .dreq_t (dreq_t), - .drsp_t (drsp_t), + .UserWidth (UserWidth), .tag_t (logic[RegWidth-1:0]), .NumOutstandingMem (NumIntOutstandingMem), .NumOutstandingLoads (NumIntOutstandingLoads), - .Caq (FP_EN), + .Caq (1'b1), .CaqDepth (CaqDepth), .CaqTagWidth (CaqTagWidth), .CaqRespTrackSeq (1'b0) @@ -3792,8 +3854,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( .caq_pvalid_i, .caq_pvalid_o ( ), .caq_empty_o (caq_empty), - .data_req_o, - .data_rsp_i + .data_req_o (lsu_req_o), + .data_rsp_i (lsu_rsp_i) ); assign lsu_tlb_qvalid = valid_instr & (is_load | is_store) diff --git a/hw/snitch/src/snitch_lsu.sv b/hw/snitch/src/snitch_lsu.sv deleted file mode 100644 index ceb6b02c98..0000000000 --- a/hw/snitch/src/snitch_lsu.sv +++ /dev/null @@ -1,321 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Author: Florian Zaruba - -/// Load Store Unit (can handle `NumOutstandingLoads` outstanding loads and -/// `NumOutstandingMem` requests in total) and optionally NaNBox if used in a -/// floating-point setting. It expects its memory sub-system to keep order (as if -/// issued with a single ID). -module snitch_lsu import cc_pkg::*; #( - parameter int unsigned AddrWidth = 32, - parameter int unsigned DataWidth = 32, - parameter int unsigned UserWidth = 0, - /// Tag passed from input to output. All transactions are in-order. - parameter type tag_t = logic [4:0], - /// Number of outstanding memory transactions. - parameter int unsigned NumOutstandingMem = 1, - /// Number of outstanding loads. - parameter int unsigned NumOutstandingLoads = 1, - /// Whether to NaN Box values. Used for floating-point load/stores. - parameter bit NaNBox = 0, - /// Whether to instantiate a consistency address queue (CAQ). The CAQ enables - /// consistency with another LSU in the same hart (i.e. in the FPSS) strictly - /// *downstream* of the issuing Snitch core. For all offloaded accesses, the - /// word address LSBs are pushed into the Snitch core's CAQ on offload and - /// popped when completed by the downstream LSU. Incoming accesses possibly - /// overtaking pending downstream accesses in the CAQ are stalled. - parameter bit Caq = 0, - /// CAQ Depth; should match the number of downstream LSU outstanding requests. - parameter int unsigned CaqDepth = 0, - /// Size of CAQ address LSB tags; provides a pessimism-complexity tradeoff. - parameter int unsigned CaqTagWidth = 0, - /// Whether the LSU should track repeated instructions issued by a sequencer - /// and accordingly filter them from its CAQ responses as is necessary. - parameter bit CaqRespTrackSeq = 0, - parameter type dreq_t = logic, - parameter type drsp_t = logic, - /// Derived parameter *Do not override* - parameter type addr_t = logic [iomsb(AddrWidth):0], - parameter type data_t = logic [iomsb(DataWidth):0], - parameter type user_t = logic [iomsb(UserWidth):0] -) ( - input logic clk_i, - input logic rst_i, - // request channel - input tag_t lsu_qtag_i, - input logic lsu_qwrite_i, - input logic lsu_qsigned_i, - input addr_t lsu_qaddr_i, - input data_t lsu_qdata_i, - input logic [1:0] lsu_qsize_i, - input snitch_pkg::amo_op_e lsu_qamo_i, - input logic lsu_qrepd_i, // Whether this is a sequencer repetition - input user_t lsu_quser_i, // User field for the axi transmission - input logic lsu_qvalid_i, - output logic lsu_qready_o, - // response channel - output data_t lsu_pdata_o, - output tag_t lsu_ptag_o, - output logic lsu_perror_o, - output logic lsu_pvalid_o, - input logic lsu_pready_i, - /// CAQ request snoop channel. Only some address bits will be read. - /// Fork offloaded loads/stores to here iff `Caq` is 1. - input addr_t caq_qaddr_i, - input logic caq_qwrite_i, - input logic caq_qvalid_i, - output logic caq_qready_o, - /// Incoming CAQ response snoop channel. - /// Fork responses to offloaded loads/stores to here iff `Caq` is 1. - input logic caq_pvalid_i, - /// Outgoing CAQ response snoop channel. - /// Signals whether access response was handshaked. - output logic caq_pvalid_o, - /// High if there is currently no transaction pending. - output logic lsu_empty_o, - /// High if the CAQ is empty. - output logic caq_empty_o, - // Memory Interface Channel - output dreq_t data_req_o, - input drsp_t data_rsp_i -); - - `include "common_cells/assertions.svh" - - localparam int unsigned DataAlign = $clog2(DataWidth/8); - - // ------------------------------- - // Consistency Address Queue (CAQ) - // ------------------------------- - - // TODO: What about exceptions? We *should* get a response for all offloaded - // loads/stores anyways as already issued instructions should conclude, but - // if this is not the case, things go south! - - logic lsu_postcaq_qvalid, lsu_postcaq_qready; - - if (Caq) begin : gen_caq - - logic caq_lsu_gnt, caq_lsu_exists; - logic caq_out_valid, caq_out_gnt; - logic caq_pass, caq_alters_mem; - - // CAQ passes requests to downstream LSU only once they are known not to collide. - // This is assumed to be *stable* once given as the Snitch core is stalled on a - // load/store and elements can only be popped from the queue, not pushed. - assign caq_pass = caq_lsu_gnt & ~caq_lsu_exists; - - // We need to stall on collisions with anything altering memory, including atomics - assign caq_alters_mem = lsu_qwrite_i | (lsu_qamo_i != snitch_pkg::AMONone); - - // Gate downstream LSU on CAQ pass - assign lsu_postcaq_qvalid = caq_pass & lsu_qvalid_i; - assign lsu_qready_o = caq_pass & lsu_postcaq_qready; - - cc_id_queue #( - .data_t ( logic [CaqTagWidth:0] ), // Store address tag *and* write enable - .IdWidth ( 1 ), // De facto 0: no reorder capability here - .Capacity ( CaqDepth ), - .FullBw ( 1 ) - ) i_caq ( - .clk_i, - .rst_ni ( ~rst_i ), - .clr_i ( 1'b0 ), - // Push in snooped accesses offloaded to downstream LSU - .inp_id_i ( '0 ), - .inp_data_i ( {caq_qwrite_i, caq_qaddr_i[CaqTagWidth+DataAlign-1:DataAlign]} ), - .inp_req_i ( caq_qvalid_i ), - .inp_gnt_o ( caq_qready_o ), - // Check if currently presented request collides with any snooped ones. - // Check address tag in any case. Check the write enable only when it - // is necessary. If we receive a write, stall on any address match - // (i.e. exclude MSB from the collision check, can be 0 or 1). If we - // receive a non-altering access, we stall only if a write collides. - .exists_mask_i ( {~caq_alters_mem, {(CaqTagWidth){1'b1}}} ), - .exists_data_i ( {1'b1, lsu_qaddr_i[CaqTagWidth+DataAlign-1:DataAlign]} ), - .exists_req_i ( lsu_qvalid_i ), - .exists_gnt_o ( caq_lsu_gnt ), - .exists_o ( caq_lsu_exists ), - // Pop output whenever we get a response for a snooped request. - // This has no backpressure as we should snoop as many responses as requests. - .oup_id_i ( '0 ), - .oup_pop_i ( caq_pvalid_i ), - .oup_req_i ( caq_pvalid_i ), - .oup_data_o ( ), - .oup_data_valid_o ( caq_out_valid ), - .oup_gnt_o ( caq_out_gnt ), - // Status interface - .full_o ( ), - .empty_o ( caq_empty_o ) - ); - - // Check that we do not pop more snooped responses than we pushed requests. - `ASSERT(CaqPopEmpty, (caq_pvalid_i |-> caq_out_gnt && caq_out_valid), clk_i, rst_i) - - // Check that once asserted, `caq_pass` is stable until we handshake the load/store - `ASSERT(CaqPassStable, ($rose(caq_pass) |-> - (caq_pass until_with lsu_qvalid_i & lsu_qready_o)), clk_i, rst_i) - - end else begin : gen_no_caq - - // No CAQ can stall us; forward request handshake to LSU logic - assign lsu_postcaq_qvalid = lsu_qvalid_i; - assign lsu_qready_o = lsu_postcaq_qready; - - // Tie CAQ interface - assign caq_qready_o = '1; - - end - - // -------------- - // Downstream LSU - // -------------- - - logic [63:0] ld_result; - logic [63:0] lsu_qdata, data_qdata; - - typedef struct packed { - tag_t tag; - logic sign_ext; - logic [DataAlign-1:0] offset; - logic [1:0] size; - } laq_t; - - // Load Address Queue (LAQ) - laq_t laq_in, laq_out; - logic mem_out; - logic laq_full, mem_full; - logic laq_push; - - cc_fifo #( - .FallThrough ( 1'b0 ), - .Depth ( NumOutstandingLoads ), - .data_t ( laq_t ) - ) i_fifo_laq ( - .clk_i, - .rst_ni (~rst_i), - .clr_i (1'b0), - .flush_i (1'b0), - .full_o (laq_full), - .empty_o (/* open */), - .usage_o (/* open */), - .data_i (laq_in), - .push_i (laq_push), - .data_o (laq_out), - .pop_i (data_rsp_i.p_valid & data_req_o.p_ready & ~mem_out) - ); - - // For each memory transaction save whether this was a load or a store. We - // need this information to suppress stores. - logic [CaqRespTrackSeq:0] req_queue_in, req_queue_out; - - assign req_queue_in[0] = lsu_qwrite_i; - assign mem_out = req_queue_out[0]; - - if (CaqRespTrackSeq) begin : gen_caq_resp_track_seq - assign req_queue_in[1] = lsu_qrepd_i; - // When tracking a sequencer, repeated accesses are masked as the core issues them only once. - // Thus, for sequenced loads or stores, only the *first issue* is popped in the CAQ. - // This means that the first issue will block on collisions and subsequent repeats will not. - // Like SSRs, loads or stores in sequencer loops (i.e. FREP) do *not* guarantee consistency. - assign caq_pvalid_o = data_rsp_i.p_valid & data_req_o.p_ready & ~req_queue_out[1]; - end else begin : gen_no_caq_resp_track_seq - // When not tracking a sequencer, simply signal the response handshake. - assign caq_pvalid_o = data_rsp_i.p_valid & data_req_o.p_ready; - end - - cc_fifo #( - .FallThrough (1'b0), - .Depth (NumOutstandingMem), - .DataWidth (1 + CaqRespTrackSeq) - ) i_fifo_mem ( - .clk_i, - .rst_ni (~rst_i), - .clr_i (1'b0), - .flush_i (1'b0), - .full_o (mem_full), - .empty_o (lsu_empty_o), - .usage_o ( /* open */ ), - .data_i (req_queue_in), - .push_i (data_req_o.q_valid & data_rsp_i.q_ready), - .data_o (req_queue_out), - .pop_i (data_rsp_i.p_valid & data_req_o.p_ready) - ); - - assign laq_in = '{ - tag: lsu_qtag_i, - sign_ext: lsu_qsigned_i, - offset: lsu_qaddr_i[DataAlign-1:0], - size: lsu_qsize_i - }; - - // Only make a request when we got a valid request and if it is a load also - // check that we can actually store the necessary information to process it in - // the upcoming cycle(s). - assign data_req_o.q_valid = lsu_postcaq_qvalid & (lsu_qwrite_i | ~laq_full) & ~mem_full; - assign data_req_o.q.write = lsu_qwrite_i; - assign data_req_o.q.addr = lsu_qaddr_i; - assign data_req_o.q.user = lsu_quser_i; - assign data_req_o.q.amo = lsu_qamo_i; - assign data_req_o.q.size = lsu_qsize_i; - - // Generate byte enable mask. - always_comb begin - unique case (lsu_qsize_i) - 2'b00: data_req_o.q.strb = ('b1 << lsu_qaddr_i[DataAlign-1:0]); - 2'b01: data_req_o.q.strb = ('b11 << lsu_qaddr_i[DataAlign-1:0]); - 2'b10: data_req_o.q.strb = ('b1111 << lsu_qaddr_i[DataAlign-1:0]); - 2'b11: data_req_o.q.strb = '1; - default: data_req_o.q.strb = '0; - endcase - end - - // Re-align write data. - /* verilator lint_off WIDTH */ - assign lsu_qdata = lsu_qdata_i; - always_comb begin - unique case (lsu_qaddr_i[DataAlign-1:0]) - 3'b000: data_qdata = lsu_qdata; - 3'b001: data_qdata = {lsu_qdata[55:0], lsu_qdata[63:56]}; - 3'b010: data_qdata = {lsu_qdata[47:0], lsu_qdata[63:48]}; - 3'b011: data_qdata = {lsu_qdata[39:0], lsu_qdata[63:40]}; - 3'b100: data_qdata = {lsu_qdata[31:0], lsu_qdata[63:32]}; - 3'b101: data_qdata = {lsu_qdata[23:0], lsu_qdata[63:24]}; - 3'b110: data_qdata = {lsu_qdata[15:0], lsu_qdata[63:16]}; - 3'b111: data_qdata = {lsu_qdata[7:0], lsu_qdata[63:8]}; - default: data_qdata = lsu_qdata; - endcase - end - assign data_req_o.q.data = data_qdata[DataWidth-1:0]; - /* verilator lint_on WIDTH */ - - // The interface didn't accept our request yet - assign lsu_postcaq_qready = ~(data_req_o.q_valid & ~data_rsp_i.q_ready) - & (lsu_qwrite_i | ~laq_full) & ~mem_full; - assign laq_push = ~lsu_qwrite_i & data_rsp_i.q_ready & data_req_o.q_valid & ~laq_full; - - // Return Path - // shift the load data back - logic [63:0] shifted_data; - assign shifted_data = data_rsp_i.p.data >> {laq_out.offset, 3'b000}; - always_comb begin - unique case (laq_out.size) - 2'b00: ld_result = {{56{(shifted_data[7] | NaNBox) & laq_out.sign_ext}}, shifted_data[7:0]}; - 2'b01: ld_result = {{48{(shifted_data[15] | NaNBox) & laq_out.sign_ext}}, shifted_data[15:0]}; - 2'b10: ld_result = {{32{(shifted_data[31] | NaNBox) & laq_out.sign_ext}}, shifted_data[31:0]}; - 2'b11: ld_result = shifted_data; - default: ld_result = shifted_data; - endcase - end - - assign lsu_perror_o = data_rsp_i.p.error; - assign lsu_pdata_o = ld_result[DataWidth-1:0]; - assign lsu_ptag_o = laq_out.tag; - // In case of a write, don't signal a valid transaction. Stores are always - // without ans answer to the core. - assign lsu_pvalid_o = data_rsp_i.p_valid & ~mem_out; - assign data_req_o.p_ready = lsu_pready_i | mem_out; - -endmodule diff --git a/hw/snitch/src/snitch_pkg.sv b/hw/snitch/src/snitch_pkg.sv index a91dd2d492..0dede4d822 100644 --- a/hw/snitch/src/snitch_pkg.sv +++ b/hw/snitch/src/snitch_pkg.sv @@ -7,6 +7,13 @@ package snitch_pkg; + /// RISC-V hart ID width (32 bits per spec). + localparam int unsigned HartIdWidth = 32; + typedef logic [HartIdWidth-1:0] hart_id_t; + + // Snitch AWUSER width, fixed to 64b corresponding to {USER_HIGH, USER_LOW} CSRs + localparam int unsigned UserWidth = 64; + typedef enum logic [3:0] { None, RegRs1, RegRs2, RegRs3, RegRd, IImmediate, UImmediate, JImmediate, SImmediate, SFImmediate, PC, Csr, CsrImmediate, PBImmediate @@ -130,6 +137,8 @@ package snitch_pkg; typedef struct packed { /// Reduced-register extension. bit RVE; + /// RISC-V V extension for Spatz + bit RVV; /// Enable Snitch DMA as accelerator. bit Xdma; bit Xssr; @@ -139,7 +148,7 @@ package snitch_pkg; bit RVF; /// Enable D Extension. bit RVD; - bit XF16; + bit Zfh; bit XF16ALT; bit XF8; bit XF8ALT; @@ -164,24 +173,9 @@ package snitch_pkg; // SSRs localparam logic [11:0] CsrMseg = 12'hBC0; - // Same semantic as AXI. - typedef logic [2:0] size_t; - - typedef enum logic [3:0] { - AMONone = 4'h0, - AMOSwap = 4'h1, - AMOAdd = 4'h2, - AMOAnd = 4'h3, - AMOOr = 4'h4, - AMOXor = 4'h5, - AMOMax = 4'h6, - AMOMaxu = 4'h7, - AMOMin = 4'h8, - AMOMinu = 4'h9, - AMOLR = 4'hA, - AMOSC = 4'hB - } amo_op_e; - + // Snitch (and not the CC) defines the accelerators it supports, since they have to be known + // by Snitch to properly address them in the decoder. This is unlike the CV-X-IF interface + // where coprocessors don't have to be addressed by the processor. typedef enum logic [31:0] { FP_SS = 0, IPU = 1, @@ -200,7 +194,7 @@ package snitch_pkg; function automatic int unsigned calculate_flen(isa_cfg_t isa); return isa.RVD ? 64 : // D ext. isa.RVF ? 32 : // F ext. - isa.XF16 ? 16 : // Xf16 ext. + isa.Zfh ? 16 : // Zfh ext. isa.XF16ALT ? 16 : // Xf16alt ext. isa.XF8 ? 8 : // Xf8 ext. isa.XF8ALT ? 8 : // Xf8alt ext. @@ -208,7 +202,7 @@ package snitch_pkg; endfunction function automatic bit calculate_fp_enable(isa_cfg_t isa); - return isa.RVF || isa.RVD || isa.XF16 || isa.XF16ALT || isa.XF8 || isa.XF8ALT || + return isa.RVF || isa.RVD || isa.Zfh || isa.XF16ALT || isa.XF8 || isa.XF8ALT || isa.XFVEC || isa.XFAUX || isa.XFDOTP; endfunction @@ -259,47 +253,53 @@ package snitch_pkg; longint acc_pdata_32; longint fpu_offload; longint is_seq_insn; - } snitch_trace_port_t; + } snitch_trace_extras_t; + + typedef struct packed { + logic [31:0] pc_q; + priv_lvl_t priv_lvl_q; + logic [31:0] instr; + snitch_trace_extras_t extras; + } snitch_trace_t; // verilog_lint: waive-start line-length - function automatic string print_snitch_trace(snitch_trace_port_t snitch_trace); + function automatic string print_snitch_extras(snitch_trace_extras_t trace); string extras_str = "{"; - extras_str = $sformatf("%s'%s': '%s', ", extras_str, "source", snitch_trace.source.name); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "stall", snitch_trace.stall); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "exception", snitch_trace.exception); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "rs1", snitch_trace.rs1); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "rs2", snitch_trace.rs2); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "rd", snitch_trace.rd); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "is_load", snitch_trace.is_load); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "is_store", snitch_trace.is_store); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "is_branch", snitch_trace.is_branch); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "pc_d", snitch_trace.pc_d); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "opa", snitch_trace.opa); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "opb", snitch_trace.opb); - extras_str = $sformatf("%s'%s': '%s', ", extras_str, "opa_select", snitch_trace.opa_select.name); - extras_str = $sformatf("%s'%s': '%s', ", extras_str, "opb_select", snitch_trace.opb_select.name); - extras_str = $sformatf("%s'%s': '%s', ", extras_str, "opc_select", snitch_trace.opc_select.name); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "write_rd", snitch_trace.write_rd); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "csr_addr", snitch_trace.csr_addr); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "writeback", snitch_trace.writeback); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "gpr_rdata_1", snitch_trace.gpr_rdata_1); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "ls_size", snitch_trace.ls_size); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "ld_result_32", snitch_trace.ld_result_32); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "lsu_rd", snitch_trace.lsu_rd); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "retire_load", snitch_trace.retire_load); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "alu_result", snitch_trace.alu_result); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "ls_amo", snitch_trace.ls_amo); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "retire_acc", snitch_trace.retire_acc); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "acc_pid", snitch_trace.acc_pid); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "acc_pdata_32", snitch_trace.acc_pdata_32); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "fpu_offload", snitch_trace.fpu_offload); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "is_seq_insn", snitch_trace.is_seq_insn); + extras_str = $sformatf("%s'%s': '%s', ", extras_str, "source", trace.source.name); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "stall", trace.stall); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "exception", trace.exception); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "rs1", trace.rs1); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "rs2", trace.rs2); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "rd", trace.rd); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "is_load", trace.is_load); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "is_store", trace.is_store); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "is_branch", trace.is_branch); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "pc_d", trace.pc_d); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "opa", trace.opa); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "opb", trace.opb); + extras_str = $sformatf("%s'%s': '%s', ", extras_str, "opa_select", trace.opa_select.name); + extras_str = $sformatf("%s'%s': '%s', ", extras_str, "opb_select", trace.opb_select.name); + extras_str = $sformatf("%s'%s': '%s', ", extras_str, "opc_select", trace.opc_select.name); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "write_rd", trace.write_rd); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "csr_addr", trace.csr_addr); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "writeback", trace.writeback); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "gpr_rdata_1", trace.gpr_rdata_1); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "ls_size", trace.ls_size); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "ld_result_32", trace.ld_result_32); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "lsu_rd", trace.lsu_rd); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "retire_load", trace.retire_load); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "alu_result", trace.alu_result); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "ls_amo", trace.ls_amo); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "retire_acc", trace.retire_acc); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "acc_pid", trace.acc_pid); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "acc_pdata_32", trace.acc_pdata_32); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "fpu_offload", trace.fpu_offload); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "is_seq_insn", trace.is_seq_insn); extras_str = $sformatf("%s}", extras_str); return extras_str; endfunction // verilog_lint: waive-stop line-length - // Trace-Port Definitions typedef struct packed { trace_src_e source; longint acc_q_hs; @@ -334,43 +334,43 @@ package snitch_pkg; longint fpr_waddr; longint fpr_wdata; longint fpr_we; - } fpu_trace_port_t; + } fpss_trace_t; - function automatic string print_fpu_trace(fpu_trace_port_t fpu_trace); + function automatic string print_fpss_extras(fpss_trace_t trace); string extras_str = "{"; - extras_str = $sformatf("%s'%s': '%s', ", extras_str, "source", fpu_trace.source.name); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "acc_q_hs", fpu_trace.acc_q_hs); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "fpu_out_hs", fpu_trace.fpu_out_hs); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "lsu_q_hs", fpu_trace.lsu_q_hs); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "op_in", fpu_trace.op_in); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "rs1", fpu_trace.rs1); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "rs2", fpu_trace.rs2); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "rs3", fpu_trace.rs3); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "rd", fpu_trace.rd); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "op_sel_0", fpu_trace.op_sel_0); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "op_sel_1", fpu_trace.op_sel_1); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "op_sel_2", fpu_trace.op_sel_2); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "src_fmt", fpu_trace.src_fmt); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "dst_fmt", fpu_trace.dst_fmt); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "int_fmt", fpu_trace.int_fmt); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "acc_qdata_0", fpu_trace.acc_qdata_0); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "acc_qdata_1", fpu_trace.acc_qdata_1); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "acc_qdata_2", fpu_trace.acc_qdata_2); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "op_0", fpu_trace.op_0); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "op_1", fpu_trace.op_1); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "op_2", fpu_trace.op_2); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "use_fpu", fpu_trace.use_fpu); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "fpu_in_rd", fpu_trace.fpu_in_rd); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "fpu_in_acc", fpu_trace.fpu_in_acc); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "ls_size", fpu_trace.ls_size); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "is_load", fpu_trace.is_load); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "is_store", fpu_trace.is_store); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "lsu_qaddr", fpu_trace.lsu_qaddr); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "lsu_rd", fpu_trace.lsu_rd); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "fpu_out_acc", fpu_trace.fpu_out_acc); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "fpr_waddr", fpu_trace.fpr_waddr); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "fpr_wdata", fpu_trace.fpr_wdata); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "fpr_we", fpu_trace.fpr_we); + extras_str = $sformatf("%s'%s': '%s', ", extras_str, "source", trace.source.name); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "acc_q_hs", trace.acc_q_hs); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "fpu_out_hs", trace.fpu_out_hs); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "lsu_q_hs", trace.lsu_q_hs); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "op_in", trace.op_in); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "rs1", trace.rs1); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "rs2", trace.rs2); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "rs3", trace.rs3); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "rd", trace.rd); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "op_sel_0", trace.op_sel_0); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "op_sel_1", trace.op_sel_1); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "op_sel_2", trace.op_sel_2); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "src_fmt", trace.src_fmt); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "dst_fmt", trace.dst_fmt); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "int_fmt", trace.int_fmt); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "acc_qdata_0", trace.acc_qdata_0); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "acc_qdata_1", trace.acc_qdata_1); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "acc_qdata_2", trace.acc_qdata_2); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "op_0", trace.op_0); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "op_1", trace.op_1); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "op_2", trace.op_2); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "use_fpu", trace.use_fpu); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "fpu_in_rd", trace.fpu_in_rd); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "fpu_in_acc", trace.fpu_in_acc); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "ls_size", trace.ls_size); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "is_load", trace.is_load); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "is_store", trace.is_store); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "lsu_qaddr", trace.lsu_qaddr); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "lsu_rd", trace.lsu_rd); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "fpu_out_acc", trace.fpu_out_acc); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "fpr_waddr", trace.fpr_waddr); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "fpr_wdata", trace.fpr_wdata); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "fpr_we", trace.fpr_we); extras_str = $sformatf("%s}", extras_str); return extras_str; endfunction @@ -382,16 +382,16 @@ package snitch_pkg; longint max_iter; longint stg_max; longint stg_mask; - } fpu_sequencer_trace_port_t; + } fpu_sequencer_trace_t; - function automatic string print_fpu_sequencer_trace(fpu_sequencer_trace_port_t fpu_sequencer); + function automatic string print_fpu_sequencer_extras(fpu_sequencer_trace_t trace); string extras_str = "{"; - extras_str = $sformatf("%s'%s': '%s', ", extras_str, "source", fpu_sequencer.source.name); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "cbuf_push", fpu_sequencer.cbuf_push); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "max_inst", fpu_sequencer.max_inst); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "max_iter", fpu_sequencer.max_iter); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "stg_max", fpu_sequencer.stg_max); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "stg_mask", fpu_sequencer.stg_mask); + extras_str = $sformatf("%s'%s': '%s', ", extras_str, "source", trace.source.name); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "cbuf_push", trace.cbuf_push); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "max_inst", trace.max_inst); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "max_iter", trace.max_iter); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "stg_max", trace.stg_max); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "stg_mask", trace.stg_mask); extras_str = $sformatf("%s}", extras_str); return extras_str; endfunction @@ -413,25 +413,25 @@ package snitch_pkg; longint tag; longint status; longint result; - } dca_trace_port_t; + } dca_trace_t; - function automatic string print_dca_trace(dca_trace_port_t dca_trace); + function automatic string print_dca_extras(dca_trace_t trace); string extras_str = "{"; - extras_str = $sformatf("%s'%s': '%s', ", extras_str, "source", dca_trace.source.name); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "req_hs", dca_trace.req_hs); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "rsp_hs", dca_trace.rsp_hs); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "op", dca_trace.op); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "op_mod", dca_trace.op_mod); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "rnd_mode", dca_trace.rnd_mode); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "vectorial_op", dca_trace.vectorial_op); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "operand0", dca_trace.operand0); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "operand1", dca_trace.operand1); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "operand2", dca_trace.operand2); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "src_fmt", dca_trace.src_fmt); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "dst_fmt", dca_trace.dst_fmt); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "int_fmt", dca_trace.int_fmt); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "status", dca_trace.status); - extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "result", dca_trace.result); + extras_str = $sformatf("%s'%s': '%s', ", extras_str, "source", trace.source.name); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "req_hs", trace.req_hs); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "rsp_hs", trace.rsp_hs); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "op", trace.op); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "op_mod", trace.op_mod); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "rnd_mode", trace.rnd_mode); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "vectorial_op", trace.vectorial_op); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "operand0", trace.operand0); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "operand1", trace.operand1); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "operand2", trace.operand2); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "src_fmt", trace.src_fmt); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "dst_fmt", trace.dst_fmt); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "int_fmt", trace.int_fmt); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "status", trace.status); + extras_str = $sformatf("%s'%s': 0x%0x, ", extras_str, "result", trace.result); extras_str = $sformatf("%s}", extras_str); return extras_str; endfunction diff --git a/hw/snitch/src/riscv_instr.sv b/hw/snitch/src/snitch_riscv_instr.sv similarity index 76% rename from hw/snitch/src/riscv_instr.sv rename to hw/snitch/src/snitch_riscv_instr.sv index f3f426c9d1..08863e7530 100644 --- a/hw/snitch/src/riscv_instr.sv +++ b/hw/snitch/src/snitch_riscv_instr.sv @@ -3,9 +3,10 @@ // SPDX-License-Identifier: SHL-0.51 // verilog_lint: waive-start parameter-name-style +// verilog_lint: waive-start explicit-parameter-storage-type /* Automatically generated by parse_opcodes */ -package riscv_instr; +package snitch_riscv_instr; localparam [31:0] ADD = 32'b0000000??????????000?????0110011; localparam [31:0] ADDI = 32'b?????????????????000?????0010011; localparam [31:0] ADDIW = 32'b?????????????????000?????0011011; @@ -706,15 +707,41 @@ package riscv_instr; localparam [31:0] SW = 32'b?????????????????010?????0100011; localparam [31:0] UNSHFL = 32'b0000100??????????101?????0110011; localparam [31:0] UNSHFLI = 32'b0000100??????????101?????0010011; + localparam [31:0] VAADD_VV = 32'b001001???????????010?????1010111; + localparam [31:0] VAADD_VX = 32'b001001???????????110?????1010111; + localparam [31:0] VAADDU_VV = 32'b001000???????????010?????1010111; + localparam [31:0] VAADDU_VX = 32'b001000???????????110?????1010111; + localparam [31:0] VADC_VIM = 32'b0100000??????????011?????1010111; + localparam [31:0] VADC_VVM = 32'b0100000??????????000?????1010111; + localparam [31:0] VADC_VXM = 32'b0100000??????????100?????1010111; + localparam [31:0] VADD_VI = 32'b000000???????????011?????1010111; + localparam [31:0] VADD_VV = 32'b000000???????????000?????1010111; + localparam [31:0] VADD_VX = 32'b000000???????????100?????1010111; + localparam [31:0] VAND_VI = 32'b001001???????????011?????1010111; + localparam [31:0] VAND_VV = 32'b001001???????????000?????1010111; + localparam [31:0] VAND_VX = 32'b001001???????????100?????1010111; + localparam [31:0] VASUB_VV = 32'b001011???????????010?????1010111; + localparam [31:0] VASUB_VX = 32'b001011???????????110?????1010111; + localparam [31:0] VASUBU_VV = 32'b001010???????????010?????1010111; + localparam [31:0] VASUBU_VX = 32'b001010???????????110?????1010111; + localparam [31:0] VCOMPRESS_VM = 32'b0101111??????????010?????1010111; + localparam [31:0] VCPOP_M = 32'b010000??????10000010?????1010111; + localparam [31:0] VDIV_VV = 32'b100001???????????010?????1010111; + localparam [31:0] VDIV_VX = 32'b100001???????????110?????1010111; + localparam [31:0] VDIVU_VV = 32'b100000???????????010?????1010111; + localparam [31:0] VDIVU_VX = 32'b100000???????????110?????1010111; localparam [31:0] VFADD_B = 32'b1000001??????????011?????0110011; localparam [31:0] VFADD_H = 32'b1000001??????????010?????0110011; localparam [31:0] VFADD_R_B = 32'b1000001??????????111?????0110011; localparam [31:0] VFADD_R_H = 32'b1000001??????????110?????0110011; localparam [31:0] VFADD_R_S = 32'b1000001??????????100?????0110011; localparam [31:0] VFADD_S = 32'b1000001??????????000?????0110011; + localparam [31:0] VFADD_VF = 32'b000000???????????101?????1010111; + localparam [31:0] VFADD_VV = 32'b000000???????????001?????1010111; localparam [31:0] VFCLASS_B = 32'b100110000001?????011?????0110011; localparam [31:0] VFCLASS_H = 32'b100110000001?????010?????0110011; localparam [31:0] VFCLASS_S = 32'b100110000001?????000?????0110011; + localparam [31:0] VFCLASS_V = 32'b010011??????10000001?????1010111; localparam [31:0] VFCPKA_B_D = 32'b1011010??????????011?????0110011; localparam [31:0] VFCPKA_B_S = 32'b1011000??????????011?????0110011; localparam [31:0] VFCPKA_H_D = 32'b1011010??????????010?????0110011; @@ -745,19 +772,25 @@ package riscv_instr; localparam [31:0] VFCVT_B_X = 32'b100110000011?????011?????0110011; localparam [31:0] VFCVT_B_XU = 32'b100110000011?????111?????0110011; localparam [31:0] VFCVT_D_S = 32'b100110000100?????001?????0110011; + localparam [31:0] VFCVT_F_X_V = 32'b010010??????00011001?????1010111; + localparam [31:0] VFCVT_F_XU_V = 32'b010010??????00010001?????1010111; localparam [31:0] VFCVT_H_B = 32'b100110000111?????010?????0110011; localparam [31:0] VFCVT_H_H = 32'b100110000101?????010?????0110011; localparam [31:0] VFCVT_H_S = 32'b100110000100?????010?????0110011; localparam [31:0] VFCVT_H_X = 32'b100110000011?????010?????0110011; localparam [31:0] VFCVT_H_XU = 32'b100110000011?????110?????0110011; + localparam [31:0] VFCVT_RTZ_X_F_V = 32'b010010??????00111001?????1010111; + localparam [31:0] VFCVT_RTZ_XU_F_V = 32'b010010??????00110001?????1010111; localparam [31:0] VFCVT_S_B = 32'b100110000111?????000?????0110011; localparam [31:0] VFCVT_S_H = 32'b100110000110?????000?????0110011; localparam [31:0] VFCVT_S_X = 32'b100110000011?????000?????0110011; localparam [31:0] VFCVT_S_XU = 32'b100110000011?????100?????0110011; localparam [31:0] VFCVT_X_B = 32'b100110000010?????011?????0110011; + localparam [31:0] VFCVT_X_F_V = 32'b010010??????00001001?????1010111; localparam [31:0] VFCVT_X_H = 32'b100110000010?????010?????0110011; localparam [31:0] VFCVT_X_S = 32'b100110000010?????000?????0110011; localparam [31:0] VFCVT_XU_B = 32'b100110000010?????111?????0110011; + localparam [31:0] VFCVT_XU_F_V = 32'b010010??????00000001?????1010111; localparam [31:0] VFCVT_XU_H = 32'b100110000010?????110?????0110011; localparam [31:0] VFCVT_XU_S = 32'b100110000010?????100?????0110011; localparam [31:0] VFCVTU_B_B = 32'b100110000111?????111?????0110011; @@ -775,6 +808,8 @@ package riscv_instr; localparam [31:0] VFDIV_R_H = 32'b1000100??????????110?????0110011; localparam [31:0] VFDIV_R_S = 32'b1000100??????????100?????0110011; localparam [31:0] VFDIV_S = 32'b1000100??????????000?????0110011; + localparam [31:0] VFDIV_VF = 32'b100000???????????101?????1010111; + localparam [31:0] VFDIV_VV = 32'b100000???????????001?????1010111; localparam [31:0] VFDOTPEX_H_B = 32'b1001011??????????010?????0110011; localparam [31:0] VFDOTPEX_H_R_B = 32'b1001011??????????110?????0110011; localparam [31:0] VFDOTPEX_S_H = 32'b1001011??????????000?????0110011; @@ -797,6 +832,7 @@ package riscv_instr; localparam [31:0] VFGT_R_H = 32'b1010101??????????110?????0110011; localparam [31:0] VFGT_R_S = 32'b1010101??????????100?????0110011; localparam [31:0] VFGT_S = 32'b1010101??????????000?????0110011; + localparam [31:0] VFIRST_M = 32'b010000??????10001010?????1010111; localparam [31:0] VFLE_B = 32'b1010100??????????011?????0110011; localparam [31:0] VFLE_H = 32'b1010100??????????010?????0110011; localparam [31:0] VFLE_R_B = 32'b1010100??????????111?????0110011; @@ -815,36 +851,62 @@ package riscv_instr; localparam [31:0] VFMAC_R_H = 32'b1001000??????????110?????0110011; localparam [31:0] VFMAC_R_S = 32'b1001000??????????100?????0110011; localparam [31:0] VFMAC_S = 32'b1001000??????????000?????0110011; + localparam [31:0] VFMACC_VF = 32'b101100???????????101?????1010111; + localparam [31:0] VFMACC_VV = 32'b101100???????????001?????1010111; + localparam [31:0] VFMADD_VF = 32'b101000???????????101?????1010111; + localparam [31:0] VFMADD_VV = 32'b101000???????????001?????1010111; localparam [31:0] VFMAX_B = 32'b1000110??????????011?????0110011; localparam [31:0] VFMAX_H = 32'b1000110??????????010?????0110011; localparam [31:0] VFMAX_R_B = 32'b1000110??????????111?????0110011; localparam [31:0] VFMAX_R_H = 32'b1000110??????????110?????0110011; localparam [31:0] VFMAX_R_S = 32'b1000110??????????100?????0110011; localparam [31:0] VFMAX_S = 32'b1000110??????????000?????0110011; + localparam [31:0] VFMAX_VF = 32'b000110???????????101?????1010111; + localparam [31:0] VFMAX_VV = 32'b000110???????????001?????1010111; + localparam [31:0] VFMERGE_VFM = 32'b0101110??????????101?????1010111; localparam [31:0] VFMIN_B = 32'b1000101??????????011?????0110011; localparam [31:0] VFMIN_H = 32'b1000101??????????010?????0110011; localparam [31:0] VFMIN_R_B = 32'b1000101??????????111?????0110011; localparam [31:0] VFMIN_R_H = 32'b1000101??????????110?????0110011; localparam [31:0] VFMIN_R_S = 32'b1000101??????????100?????0110011; localparam [31:0] VFMIN_S = 32'b1000101??????????000?????0110011; + localparam [31:0] VFMIN_VF = 32'b000100???????????101?????1010111; + localparam [31:0] VFMIN_VV = 32'b000100???????????001?????1010111; localparam [31:0] VFMRE_B = 32'b1001001??????????011?????0110011; localparam [31:0] VFMRE_H = 32'b1001001??????????010?????0110011; localparam [31:0] VFMRE_R_B = 32'b1001001??????????111?????0110011; localparam [31:0] VFMRE_R_H = 32'b1001001??????????110?????0110011; localparam [31:0] VFMRE_R_S = 32'b1001001??????????100?????0110011; localparam [31:0] VFMRE_S = 32'b1001001??????????000?????0110011; + localparam [31:0] VFMSAC_VF = 32'b101110???????????101?????1010111; + localparam [31:0] VFMSAC_VV = 32'b101110???????????001?????1010111; + localparam [31:0] VFMSUB_VF = 32'b101010???????????101?????1010111; + localparam [31:0] VFMSUB_VV = 32'b101010???????????001?????1010111; localparam [31:0] VFMUL_B = 32'b1000011??????????011?????0110011; localparam [31:0] VFMUL_H = 32'b1000011??????????010?????0110011; localparam [31:0] VFMUL_R_B = 32'b1000011??????????111?????0110011; localparam [31:0] VFMUL_R_H = 32'b1000011??????????110?????0110011; localparam [31:0] VFMUL_R_S = 32'b1000011??????????100?????0110011; localparam [31:0] VFMUL_S = 32'b1000011??????????000?????0110011; + localparam [31:0] VFMUL_VF = 32'b100100???????????101?????1010111; + localparam [31:0] VFMUL_VV = 32'b100100???????????001?????1010111; localparam [31:0] VFMV_B_X = 32'b100110000000?????111?????0110011; + localparam [31:0] VFMV_F_S = 32'b0100001?????00000001?????1010111; localparam [31:0] VFMV_H_X = 32'b100110000000?????110?????0110011; + localparam [31:0] VFMV_S_F = 32'b010000100000?????101?????1010111; localparam [31:0] VFMV_S_X = 32'b100110000000?????100?????0110011; + localparam [31:0] VFMV_V_F = 32'b010111100000?????101?????1010111; localparam [31:0] VFMV_X_B = 32'b100110000000?????011?????0110011; localparam [31:0] VFMV_X_H = 32'b100110000000?????010?????0110011; localparam [31:0] VFMV_X_S = 32'b100110000000?????000?????0110011; + localparam [31:0] VFNCVT_F_F_W = 32'b010010??????10100001?????1010111; + localparam [31:0] VFNCVT_F_X_W = 32'b010010??????10011001?????1010111; + localparam [31:0] VFNCVT_F_XU_W = 32'b010010??????10010001?????1010111; + localparam [31:0] VFNCVT_ROD_F_F_W = 32'b010010??????10101001?????1010111; + localparam [31:0] VFNCVT_RTZ_X_F_W = 32'b010010??????10111001?????1010111; + localparam [31:0] VFNCVT_RTZ_XU_F_W = 32'b010010??????10110001?????1010111; + localparam [31:0] VFNCVT_X_F_W = 32'b010010??????10001001?????1010111; + localparam [31:0] VFNCVT_XU_F_W = 32'b010010??????10000001?????1010111; localparam [31:0] VFNDOTPEX_H_B = 32'b1011101??????????010?????0110011; localparam [31:0] VFNDOTPEX_H_R_B = 32'b1011101??????????110?????0110011; localparam [31:0] VFNDOTPEX_S_H = 32'b1011101??????????000?????0110011; @@ -855,43 +917,357 @@ package riscv_instr; localparam [31:0] VFNE_R_H = 32'b1010001??????????110?????0110011; localparam [31:0] VFNE_R_S = 32'b1010001??????????100?????0110011; localparam [31:0] VFNE_S = 32'b1010001??????????000?????0110011; + localparam [31:0] VFNMACC_VF = 32'b101101???????????101?????1010111; + localparam [31:0] VFNMACC_VV = 32'b101101???????????001?????1010111; + localparam [31:0] VFNMADD_VF = 32'b101001???????????101?????1010111; + localparam [31:0] VFNMADD_VV = 32'b101001???????????001?????1010111; + localparam [31:0] VFNMSAC_VF = 32'b101111???????????101?????1010111; + localparam [31:0] VFNMSAC_VV = 32'b101111???????????001?????1010111; + localparam [31:0] VFNMSUB_VF = 32'b101011???????????101?????1010111; + localparam [31:0] VFNMSUB_VV = 32'b101011???????????001?????1010111; localparam [31:0] VFNSUM_B = 32'b101011100111?????011?????0110011; localparam [31:0] VFNSUM_H = 32'b101011111110?????010?????0110011; localparam [31:0] VFNSUM_S = 32'b101011111100?????000?????0110011; localparam [31:0] VFNSUMEX_H_B = 32'b101011110111?????010?????0110011; localparam [31:0] VFNSUMEX_S_H = 32'b101011110110?????000?????0110011; + localparam [31:0] VFRDIV_VF = 32'b100001???????????101?????1010111; + localparam [31:0] VFREC7_V = 32'b010011??????00101001?????1010111; + localparam [31:0] VFREDMAX_VS = 32'b000111???????????001?????1010111; + localparam [31:0] VFREDMIN_VS = 32'b000101???????????001?????1010111; + localparam [31:0] VFREDOSUM_VS = 32'b000011???????????001?????1010111; + localparam [31:0] VFREDUSUM_VS = 32'b000001???????????001?????1010111; + localparam [31:0] VFRSQRT7_V = 32'b010011??????00100001?????1010111; + localparam [31:0] VFRSUB_VF = 32'b100111???????????101?????1010111; localparam [31:0] VFSGNJ_B = 32'b1001101??????????011?????0110011; localparam [31:0] VFSGNJ_H = 32'b1001101??????????010?????0110011; localparam [31:0] VFSGNJ_R_B = 32'b1001101??????????111?????0110011; localparam [31:0] VFSGNJ_R_H = 32'b1001101??????????110?????0110011; localparam [31:0] VFSGNJ_R_S = 32'b1001101??????????100?????0110011; localparam [31:0] VFSGNJ_S = 32'b1001101??????????000?????0110011; + localparam [31:0] VFSGNJ_VF = 32'b001000???????????101?????1010111; + localparam [31:0] VFSGNJ_VV = 32'b001000???????????001?????1010111; localparam [31:0] VFSGNJN_B = 32'b1001110??????????011?????0110011; localparam [31:0] VFSGNJN_H = 32'b1001110??????????010?????0110011; localparam [31:0] VFSGNJN_R_B = 32'b1001110??????????111?????0110011; localparam [31:0] VFSGNJN_R_H = 32'b1001110??????????110?????0110011; localparam [31:0] VFSGNJN_R_S = 32'b1001110??????????100?????0110011; localparam [31:0] VFSGNJN_S = 32'b1001110??????????000?????0110011; + localparam [31:0] VFSGNJN_VF = 32'b001001???????????101?????1010111; + localparam [31:0] VFSGNJN_VV = 32'b001001???????????001?????1010111; localparam [31:0] VFSGNJX_B = 32'b1001111??????????011?????0110011; localparam [31:0] VFSGNJX_H = 32'b1001111??????????010?????0110011; localparam [31:0] VFSGNJX_R_B = 32'b1001111??????????111?????0110011; localparam [31:0] VFSGNJX_R_H = 32'b1001111??????????110?????0110011; localparam [31:0] VFSGNJX_R_S = 32'b1001111??????????100?????0110011; localparam [31:0] VFSGNJX_S = 32'b1001111??????????000?????0110011; + localparam [31:0] VFSGNJX_VF = 32'b001010???????????101?????1010111; + localparam [31:0] VFSGNJX_VV = 32'b001010???????????001?????1010111; + localparam [31:0] VFSLIDE1DOWN_VF = 32'b001111???????????101?????1010111; + localparam [31:0] VFSLIDE1UP_VF = 32'b001110???????????101?????1010111; localparam [31:0] VFSQRT_B = 32'b100011100000?????011?????0110011; localparam [31:0] VFSQRT_H = 32'b100011100000?????010?????0110011; localparam [31:0] VFSQRT_S = 32'b100011100000?????000?????0110011; + localparam [31:0] VFSQRT_V = 32'b010011??????00000001?????1010111; localparam [31:0] VFSUB_B = 32'b1000010??????????011?????0110011; localparam [31:0] VFSUB_H = 32'b1000010??????????010?????0110011; localparam [31:0] VFSUB_R_B = 32'b1000010??????????111?????0110011; localparam [31:0] VFSUB_R_H = 32'b1000010??????????110?????0110011; localparam [31:0] VFSUB_R_S = 32'b1000010??????????100?????0110011; localparam [31:0] VFSUB_S = 32'b1000010??????????000?????0110011; + localparam [31:0] VFSUB_VF = 32'b000010???????????101?????1010111; + localparam [31:0] VFSUB_VV = 32'b000010???????????001?????1010111; localparam [31:0] VFSUM_B = 32'b100011100111?????011?????0110011; localparam [31:0] VFSUM_H = 32'b100011111110?????010?????0110011; localparam [31:0] VFSUM_S = 32'b100011111100?????000?????0110011; localparam [31:0] VFSUMEX_H_B = 32'b100011110111?????010?????0110011; localparam [31:0] VFSUMEX_S_H = 32'b100011110110?????000?????0110011; + localparam [31:0] VFWADD_VF = 32'b110000???????????101?????1010111; + localparam [31:0] VFWADD_VV = 32'b110000???????????001?????1010111; + localparam [31:0] VFWADD_WF = 32'b110100???????????101?????1010111; + localparam [31:0] VFWADD_WV = 32'b110100???????????001?????1010111; + localparam [31:0] VFWCVT_F_F_V = 32'b010010??????01100001?????1010111; + localparam [31:0] VFWCVT_F_X_V = 32'b010010??????01011001?????1010111; + localparam [31:0] VFWCVT_F_XU_V = 32'b010010??????01010001?????1010111; + localparam [31:0] VFWCVT_RTZ_X_F_V = 32'b010010??????01111001?????1010111; + localparam [31:0] VFWCVT_RTZ_XU_F_V = 32'b010010??????01110001?????1010111; + localparam [31:0] VFWCVT_X_F_V = 32'b010010??????01001001?????1010111; + localparam [31:0] VFWCVT_XU_F_V = 32'b010010??????01000001?????1010111; + localparam [31:0] VFWMACC_VF = 32'b111100???????????101?????1010111; + localparam [31:0] VFWMACC_VV = 32'b111100???????????001?????1010111; + localparam [31:0] VFWMSAC_VF = 32'b111110???????????101?????1010111; + localparam [31:0] VFWMSAC_VV = 32'b111110???????????001?????1010111; + localparam [31:0] VFWMUL_VF = 32'b111000???????????101?????1010111; + localparam [31:0] VFWMUL_VV = 32'b111000???????????001?????1010111; + localparam [31:0] VFWNMACC_VF = 32'b111101???????????101?????1010111; + localparam [31:0] VFWNMACC_VV = 32'b111101???????????001?????1010111; + localparam [31:0] VFWNMSAC_VF = 32'b111111???????????101?????1010111; + localparam [31:0] VFWNMSAC_VV = 32'b111111???????????001?????1010111; + localparam [31:0] VFWREDOSUM_VS = 32'b110011???????????001?????1010111; + localparam [31:0] VFWREDUSUM_VS = 32'b110001???????????001?????1010111; + localparam [31:0] VFWSUB_VF = 32'b110010???????????101?????1010111; + localparam [31:0] VFWSUB_VV = 32'b110010???????????001?????1010111; + localparam [31:0] VFWSUB_WF = 32'b110110???????????101?????1010111; + localparam [31:0] VFWSUB_WV = 32'b110110???????????001?????1010111; + localparam [31:0] VID_V = 32'b010100?0000010001010?????1010111; + localparam [31:0] VIOTA_M = 32'b010100??????10000010?????1010111; + localparam [31:0] VL1RE16_V = 32'b000000101000?????101?????0000111; + localparam [31:0] VL1RE32_V = 32'b000000101000?????110?????0000111; + localparam [31:0] VL1RE64_V = 32'b000000101000?????111?????0000111; + localparam [31:0] VL1RE8_V = 32'b000000101000?????000?????0000111; + localparam [31:0] VL2RE16_V = 32'b001000101000?????101?????0000111; + localparam [31:0] VL2RE32_V = 32'b001000101000?????110?????0000111; + localparam [31:0] VL2RE64_V = 32'b001000101000?????111?????0000111; + localparam [31:0] VL2RE8_V = 32'b001000101000?????000?????0000111; + localparam [31:0] VL4RE16_V = 32'b011000101000?????101?????0000111; + localparam [31:0] VL4RE32_V = 32'b011000101000?????110?????0000111; + localparam [31:0] VL4RE64_V = 32'b011000101000?????111?????0000111; + localparam [31:0] VL4RE8_V = 32'b011000101000?????000?????0000111; + localparam [31:0] VL8RE16_V = 32'b111000101000?????101?????0000111; + localparam [31:0] VL8RE32_V = 32'b111000101000?????110?????0000111; + localparam [31:0] VL8RE64_V = 32'b111000101000?????111?????0000111; + localparam [31:0] VL8RE8_V = 32'b111000101000?????000?????0000111; + localparam [31:0] VLE16_V = 32'b???000?00000?????101?????0000111; + localparam [31:0] VLE16FF_V = 32'b???000?10000?????101?????0000111; + localparam [31:0] VLE32_V = 32'b???000?00000?????110?????0000111; + localparam [31:0] VLE32FF_V = 32'b???000?10000?????110?????0000111; + localparam [31:0] VLE64_V = 32'b???000?00000?????111?????0000111; + localparam [31:0] VLE64FF_V = 32'b???000?10000?????111?????0000111; + localparam [31:0] VLE8_V = 32'b???000?00000?????000?????0000111; + localparam [31:0] VLE8FF_V = 32'b???000?10000?????000?????0000111; + localparam [31:0] VLM_V = 32'b000000101011?????000?????0000111; + localparam [31:0] VLOXEI16_V = 32'b???011???????????101?????0000111; + localparam [31:0] VLOXEI32_V = 32'b???011???????????110?????0000111; + localparam [31:0] VLOXEI64_V = 32'b???011???????????111?????0000111; + localparam [31:0] VLOXEI8_V = 32'b???011???????????000?????0000111; + localparam [31:0] VLSE16_V = 32'b???010???????????101?????0000111; + localparam [31:0] VLSE32_V = 32'b???010???????????110?????0000111; + localparam [31:0] VLSE64_V = 32'b???010???????????111?????0000111; + localparam [31:0] VLSE8_V = 32'b???010???????????000?????0000111; + localparam [31:0] VLUXEI16_V = 32'b???001???????????101?????0000111; + localparam [31:0] VLUXEI32_V = 32'b???001???????????110?????0000111; + localparam [31:0] VLUXEI64_V = 32'b???001???????????111?????0000111; + localparam [31:0] VLUXEI8_V = 32'b???001???????????000?????0000111; + localparam [31:0] VMACC_VV = 32'b101101???????????010?????1010111; + localparam [31:0] VMACC_VX = 32'b101101???????????110?????1010111; + localparam [31:0] VMADC_VI = 32'b0100011??????????011?????1010111; + localparam [31:0] VMADC_VIM = 32'b0100010??????????011?????1010111; + localparam [31:0] VMADC_VV = 32'b0100011??????????000?????1010111; + localparam [31:0] VMADC_VVM = 32'b0100010??????????000?????1010111; + localparam [31:0] VMADC_VX = 32'b0100011??????????100?????1010111; + localparam [31:0] VMADC_VXM = 32'b0100010??????????100?????1010111; + localparam [31:0] VMADD_VV = 32'b101001???????????010?????1010111; + localparam [31:0] VMADD_VX = 32'b101001???????????110?????1010111; + localparam [31:0] VMAND_MM = 32'b0110011??????????010?????1010111; + localparam [31:0] VMANDN_MM = 32'b0110001??????????010?????1010111; + localparam [31:0] VMAX_VV = 32'b000111???????????000?????1010111; + localparam [31:0] VMAX_VX = 32'b000111???????????100?????1010111; + localparam [31:0] VMAXU_VV = 32'b000110???????????000?????1010111; + localparam [31:0] VMAXU_VX = 32'b000110???????????100?????1010111; + localparam [31:0] VMERGE_VIM = 32'b0101110??????????011?????1010111; + localparam [31:0] VMERGE_VVM = 32'b0101110??????????000?????1010111; + localparam [31:0] VMERGE_VXM = 32'b0101110??????????100?????1010111; + localparam [31:0] VMFEQ_VF = 32'b011000???????????101?????1010111; + localparam [31:0] VMFEQ_VV = 32'b011000???????????001?????1010111; + localparam [31:0] VMFGE_VF = 32'b011111???????????101?????1010111; + localparam [31:0] VMFGT_VF = 32'b011101???????????101?????1010111; + localparam [31:0] VMFLE_VF = 32'b011001???????????101?????1010111; + localparam [31:0] VMFLE_VV = 32'b011001???????????001?????1010111; + localparam [31:0] VMFLT_VF = 32'b011011???????????101?????1010111; + localparam [31:0] VMFLT_VV = 32'b011011???????????001?????1010111; + localparam [31:0] VMFNE_VF = 32'b011100???????????101?????1010111; + localparam [31:0] VMFNE_VV = 32'b011100???????????001?????1010111; + localparam [31:0] VMIN_VV = 32'b000101???????????000?????1010111; + localparam [31:0] VMIN_VX = 32'b000101???????????100?????1010111; + localparam [31:0] VMINU_VV = 32'b000100???????????000?????1010111; + localparam [31:0] VMINU_VX = 32'b000100???????????100?????1010111; + localparam [31:0] VMNAND_MM = 32'b0111011??????????010?????1010111; + localparam [31:0] VMNOR_MM = 32'b0111101??????????010?????1010111; + localparam [31:0] VMOR_MM = 32'b0110101??????????010?????1010111; + localparam [31:0] VMORN_MM = 32'b0111001??????????010?????1010111; + localparam [31:0] VMSBC_VV = 32'b0100111??????????000?????1010111; + localparam [31:0] VMSBC_VVM = 32'b0100110??????????000?????1010111; + localparam [31:0] VMSBC_VX = 32'b0100111??????????100?????1010111; + localparam [31:0] VMSBC_VXM = 32'b0100110??????????100?????1010111; + localparam [31:0] VMSBF_M = 32'b010100??????00001010?????1010111; + localparam [31:0] VMSEQ_VI = 32'b011000???????????011?????1010111; + localparam [31:0] VMSEQ_VV = 32'b011000???????????000?????1010111; + localparam [31:0] VMSEQ_VX = 32'b011000???????????100?????1010111; + localparam [31:0] VMSGT_VI = 32'b011111???????????011?????1010111; + localparam [31:0] VMSGT_VX = 32'b011111???????????100?????1010111; + localparam [31:0] VMSGTU_VI = 32'b011110???????????011?????1010111; + localparam [31:0] VMSGTU_VX = 32'b011110???????????100?????1010111; + localparam [31:0] VMSIF_M = 32'b010100??????00011010?????1010111; + localparam [31:0] VMSLE_VI = 32'b011101???????????011?????1010111; + localparam [31:0] VMSLE_VV = 32'b011101???????????000?????1010111; + localparam [31:0] VMSLE_VX = 32'b011101???????????100?????1010111; + localparam [31:0] VMSLEU_VI = 32'b011100???????????011?????1010111; + localparam [31:0] VMSLEU_VV = 32'b011100???????????000?????1010111; + localparam [31:0] VMSLEU_VX = 32'b011100???????????100?????1010111; + localparam [31:0] VMSLT_VV = 32'b011011???????????000?????1010111; + localparam [31:0] VMSLT_VX = 32'b011011???????????100?????1010111; + localparam [31:0] VMSLTU_VV = 32'b011010???????????000?????1010111; + localparam [31:0] VMSLTU_VX = 32'b011010???????????100?????1010111; + localparam [31:0] VMSNE_VI = 32'b011001???????????011?????1010111; + localparam [31:0] VMSNE_VV = 32'b011001???????????000?????1010111; + localparam [31:0] VMSNE_VX = 32'b011001???????????100?????1010111; + localparam [31:0] VMSOF_M = 32'b010100??????00010010?????1010111; + localparam [31:0] VMUL_VV = 32'b100101???????????010?????1010111; + localparam [31:0] VMUL_VX = 32'b100101???????????110?????1010111; + localparam [31:0] VMULH_VV = 32'b100111???????????010?????1010111; + localparam [31:0] VMULH_VX = 32'b100111???????????110?????1010111; + localparam [31:0] VMULHSU_VV = 32'b100110???????????010?????1010111; + localparam [31:0] VMULHSU_VX = 32'b100110???????????110?????1010111; + localparam [31:0] VMULHU_VV = 32'b100100???????????010?????1010111; + localparam [31:0] VMULHU_VX = 32'b100100???????????110?????1010111; + localparam [31:0] VMV1R_V = 32'b1001111?????00000011?????1010111; + localparam [31:0] VMV2R_V = 32'b1001111?????00001011?????1010111; + localparam [31:0] VMV4R_V = 32'b1001111?????00011011?????1010111; + localparam [31:0] VMV8R_V = 32'b1001111?????00111011?????1010111; + localparam [31:0] VMV_S_X = 32'b010000100000?????110?????1010111; + localparam [31:0] VMV_V_I = 32'b010111100000?????011?????1010111; + localparam [31:0] VMV_V_V = 32'b010111100000?????000?????1010111; + localparam [31:0] VMV_V_X = 32'b010111100000?????100?????1010111; + localparam [31:0] VMV_X_S = 32'b0100001?????00000010?????1010111; + localparam [31:0] VMXNOR_MM = 32'b0111111??????????010?????1010111; + localparam [31:0] VMXOR_MM = 32'b0110111??????????010?????1010111; + localparam [31:0] VNCLIP_WI = 32'b101111???????????011?????1010111; + localparam [31:0] VNCLIP_WV = 32'b101111???????????000?????1010111; + localparam [31:0] VNCLIP_WX = 32'b101111???????????100?????1010111; + localparam [31:0] VNCLIPU_WI = 32'b101110???????????011?????1010111; + localparam [31:0] VNCLIPU_WV = 32'b101110???????????000?????1010111; + localparam [31:0] VNCLIPU_WX = 32'b101110???????????100?????1010111; + localparam [31:0] VNMSAC_VV = 32'b101111???????????010?????1010111; + localparam [31:0] VNMSAC_VX = 32'b101111???????????110?????1010111; + localparam [31:0] VNMSUB_VV = 32'b101011???????????010?????1010111; + localparam [31:0] VNMSUB_VX = 32'b101011???????????110?????1010111; + localparam [31:0] VNSRA_WI = 32'b101101???????????011?????1010111; + localparam [31:0] VNSRA_WV = 32'b101101???????????000?????1010111; + localparam [31:0] VNSRA_WX = 32'b101101???????????100?????1010111; + localparam [31:0] VNSRL_WI = 32'b101100???????????011?????1010111; + localparam [31:0] VNSRL_WV = 32'b101100???????????000?????1010111; + localparam [31:0] VNSRL_WX = 32'b101100???????????100?????1010111; + localparam [31:0] VOR_VI = 32'b001010???????????011?????1010111; + localparam [31:0] VOR_VV = 32'b001010???????????000?????1010111; + localparam [31:0] VOR_VX = 32'b001010???????????100?????1010111; + localparam [31:0] VREDAND_VS = 32'b000001???????????010?????1010111; + localparam [31:0] VREDMAX_VS = 32'b000111???????????010?????1010111; + localparam [31:0] VREDMAXU_VS = 32'b000110???????????010?????1010111; + localparam [31:0] VREDMIN_VS = 32'b000101???????????010?????1010111; + localparam [31:0] VREDMINU_VS = 32'b000100???????????010?????1010111; + localparam [31:0] VREDOR_VS = 32'b000010???????????010?????1010111; + localparam [31:0] VREDSUM_VS = 32'b000000???????????010?????1010111; + localparam [31:0] VREDXOR_VS = 32'b000011???????????010?????1010111; + localparam [31:0] VREM_VV = 32'b100011???????????010?????1010111; + localparam [31:0] VREM_VX = 32'b100011???????????110?????1010111; + localparam [31:0] VREMU_VV = 32'b100010???????????010?????1010111; + localparam [31:0] VREMU_VX = 32'b100010???????????110?????1010111; + localparam [31:0] VRGATHER_VI = 32'b001100???????????011?????1010111; + localparam [31:0] VRGATHER_VV = 32'b001100???????????000?????1010111; + localparam [31:0] VRGATHER_VX = 32'b001100???????????100?????1010111; + localparam [31:0] VRGATHEREI16_VV = 32'b001110???????????000?????1010111; + localparam [31:0] VRSUB_VI = 32'b000011???????????011?????1010111; + localparam [31:0] VRSUB_VX = 32'b000011???????????100?????1010111; + localparam [31:0] VS1R_V = 32'b000000101000?????000?????0100111; + localparam [31:0] VS2R_V = 32'b001000101000?????000?????0100111; + localparam [31:0] VS4R_V = 32'b011000101000?????000?????0100111; + localparam [31:0] VS8R_V = 32'b111000101000?????000?????0100111; + localparam [31:0] VSADD_VI = 32'b100001???????????011?????1010111; + localparam [31:0] VSADD_VV = 32'b100001???????????000?????1010111; + localparam [31:0] VSADD_VX = 32'b100001???????????100?????1010111; + localparam [31:0] VSADDU_VI = 32'b100000???????????011?????1010111; + localparam [31:0] VSADDU_VV = 32'b100000???????????000?????1010111; + localparam [31:0] VSADDU_VX = 32'b100000???????????100?????1010111; + localparam [31:0] VSBC_VVM = 32'b0100100??????????000?????1010111; + localparam [31:0] VSBC_VXM = 32'b0100100??????????100?????1010111; + localparam [31:0] VSE16_V = 32'b???000?00000?????101?????0100111; + localparam [31:0] VSE32_V = 32'b???000?00000?????110?????0100111; + localparam [31:0] VSE64_V = 32'b???000?00000?????111?????0100111; + localparam [31:0] VSE8_V = 32'b???000?00000?????000?????0100111; + localparam [31:0] VSETIVLI = 32'b11???????????????111?????1010111; + localparam [31:0] VSETVL = 32'b1000000??????????111?????1010111; + localparam [31:0] VSETVLI = 32'b0????????????????111?????1010111; + localparam [31:0] VSEXT_VF2 = 32'b010010??????00111010?????1010111; + localparam [31:0] VSEXT_VF4 = 32'b010010??????00101010?????1010111; + localparam [31:0] VSEXT_VF8 = 32'b010010??????00011010?????1010111; + localparam [31:0] VSLIDE1DOWN_VX = 32'b001111???????????110?????1010111; + localparam [31:0] VSLIDE1UP_VX = 32'b001110???????????110?????1010111; + localparam [31:0] VSLIDEDOWN_VI = 32'b001111???????????011?????1010111; + localparam [31:0] VSLIDEDOWN_VX = 32'b001111???????????100?????1010111; + localparam [31:0] VSLIDEUP_VI = 32'b001110???????????011?????1010111; + localparam [31:0] VSLIDEUP_VX = 32'b001110???????????100?????1010111; + localparam [31:0] VSLL_VI = 32'b100101???????????011?????1010111; + localparam [31:0] VSLL_VV = 32'b100101???????????000?????1010111; + localparam [31:0] VSLL_VX = 32'b100101???????????100?????1010111; + localparam [31:0] VSM_V = 32'b000000101011?????000?????0100111; + localparam [31:0] VSMUL_VV = 32'b100111???????????000?????1010111; + localparam [31:0] VSMUL_VX = 32'b100111???????????100?????1010111; + localparam [31:0] VSOXEI16_V = 32'b???011???????????101?????0100111; + localparam [31:0] VSOXEI32_V = 32'b???011???????????110?????0100111; + localparam [31:0] VSOXEI64_V = 32'b???011???????????111?????0100111; + localparam [31:0] VSOXEI8_V = 32'b???011???????????000?????0100111; + localparam [31:0] VSRA_VI = 32'b101001???????????011?????1010111; + localparam [31:0] VSRA_VV = 32'b101001???????????000?????1010111; + localparam [31:0] VSRA_VX = 32'b101001???????????100?????1010111; + localparam [31:0] VSRL_VI = 32'b101000???????????011?????1010111; + localparam [31:0] VSRL_VV = 32'b101000???????????000?????1010111; + localparam [31:0] VSRL_VX = 32'b101000???????????100?????1010111; + localparam [31:0] VSSE16_V = 32'b???010???????????101?????0100111; + localparam [31:0] VSSE32_V = 32'b???010???????????110?????0100111; + localparam [31:0] VSSE64_V = 32'b???010???????????111?????0100111; + localparam [31:0] VSSE8_V = 32'b???010???????????000?????0100111; + localparam [31:0] VSSRA_VI = 32'b101011???????????011?????1010111; + localparam [31:0] VSSRA_VV = 32'b101011???????????000?????1010111; + localparam [31:0] VSSRA_VX = 32'b101011???????????100?????1010111; + localparam [31:0] VSSRL_VI = 32'b101010???????????011?????1010111; + localparam [31:0] VSSRL_VV = 32'b101010???????????000?????1010111; + localparam [31:0] VSSRL_VX = 32'b101010???????????100?????1010111; + localparam [31:0] VSSUB_VV = 32'b100011???????????000?????1010111; + localparam [31:0] VSSUB_VX = 32'b100011???????????100?????1010111; + localparam [31:0] VSSUBU_VV = 32'b100010???????????000?????1010111; + localparam [31:0] VSSUBU_VX = 32'b100010???????????100?????1010111; + localparam [31:0] VSUB_VV = 32'b000010???????????000?????1010111; + localparam [31:0] VSUB_VX = 32'b000010???????????100?????1010111; + localparam [31:0] VSUXEI16_V = 32'b???001???????????101?????0100111; + localparam [31:0] VSUXEI32_V = 32'b???001???????????110?????0100111; + localparam [31:0] VSUXEI64_V = 32'b???001???????????111?????0100111; + localparam [31:0] VSUXEI8_V = 32'b???001???????????000?????0100111; + localparam [31:0] VWADD_VV = 32'b110001???????????010?????1010111; + localparam [31:0] VWADD_VX = 32'b110001???????????110?????1010111; + localparam [31:0] VWADD_WV = 32'b110101???????????010?????1010111; + localparam [31:0] VWADD_WX = 32'b110101???????????110?????1010111; + localparam [31:0] VWADDU_VV = 32'b110000???????????010?????1010111; + localparam [31:0] VWADDU_VX = 32'b110000???????????110?????1010111; + localparam [31:0] VWADDU_WV = 32'b110100???????????010?????1010111; + localparam [31:0] VWADDU_WX = 32'b110100???????????110?????1010111; + localparam [31:0] VWMACC_VV = 32'b111101???????????010?????1010111; + localparam [31:0] VWMACC_VX = 32'b111101???????????110?????1010111; + localparam [31:0] VWMACCSU_VV = 32'b111111???????????010?????1010111; + localparam [31:0] VWMACCSU_VX = 32'b111111???????????110?????1010111; + localparam [31:0] VWMACCU_VV = 32'b111100???????????010?????1010111; + localparam [31:0] VWMACCU_VX = 32'b111100???????????110?????1010111; + localparam [31:0] VWMACCUS_VX = 32'b111110???????????110?????1010111; + localparam [31:0] VWMUL_VV = 32'b111011???????????010?????1010111; + localparam [31:0] VWMUL_VX = 32'b111011???????????110?????1010111; + localparam [31:0] VWMULSU_VV = 32'b111010???????????010?????1010111; + localparam [31:0] VWMULSU_VX = 32'b111010???????????110?????1010111; + localparam [31:0] VWMULU_VV = 32'b111000???????????010?????1010111; + localparam [31:0] VWMULU_VX = 32'b111000???????????110?????1010111; + localparam [31:0] VWREDSUM_VS = 32'b110001???????????000?????1010111; + localparam [31:0] VWREDSUMU_VS = 32'b110000???????????000?????1010111; + localparam [31:0] VWSUB_VV = 32'b110011???????????010?????1010111; + localparam [31:0] VWSUB_VX = 32'b110011???????????110?????1010111; + localparam [31:0] VWSUB_WV = 32'b110111???????????010?????1010111; + localparam [31:0] VWSUB_WX = 32'b110111???????????110?????1010111; + localparam [31:0] VWSUBU_VV = 32'b110010???????????010?????1010111; + localparam [31:0] VWSUBU_VX = 32'b110010???????????110?????1010111; + localparam [31:0] VWSUBU_WV = 32'b110110???????????010?????1010111; + localparam [31:0] VWSUBU_WX = 32'b110110???????????110?????1010111; + localparam [31:0] VXOR_VI = 32'b001011???????????011?????1010111; + localparam [31:0] VXOR_VV = 32'b001011???????????000?????1010111; + localparam [31:0] VXOR_VX = 32'b001011???????????100?????1010111; + localparam [31:0] VZEXT_VF2 = 32'b010010??????00110010?????1010111; + localparam [31:0] VZEXT_VF4 = 32'b010010??????00100010?????1010111; + localparam [31:0] VZEXT_VF8 = 32'b010010??????00010010?????1010111; localparam [31:0] WFI = 32'b00010000010100000000000001110011; localparam [31:0] XNOR = 32'b0100000??????????100?????0110011; localparam [31:0] XOR = 32'b0000000??????????100?????0110011; @@ -1370,3 +1746,4 @@ package riscv_instr; endpackage // verilog_lint: waive-stop parameter-name-style +// verilog_lint: waive-stop explicit-parameter-storage-type diff --git a/hw/reqrsp_interface/util/compile.sh b/hw/snitch/util/compile.sh similarity index 81% rename from hw/reqrsp_interface/util/compile.sh rename to hw/snitch/util/compile.sh index 51d3ba4ebc..98148b69e1 100755 --- a/hw/reqrsp_interface/util/compile.sh +++ b/hw/snitch/util/compile.sh @@ -8,9 +8,11 @@ set -e +SN_ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/../../.." && pwd) + [ ! -z "$VSIM" ] || VSIM=vsim -$SN_BENDER script vsim -t test -t snitch_cluster:tb \ +$SN_BENDER -d "$SN_ROOT" script vsim -t test -t snitch:tb \ --vlog-arg="-svinputport=compat" \ --vlog-arg="-override_timescale 1ns/1ps" \ --vlog-arg="-suppress 2583" \ diff --git a/hw/reqrsp_interface/util/run_vsim.sh b/hw/snitch/util/run_vsim.sh similarity index 68% rename from hw/reqrsp_interface/util/run_vsim.sh rename to hw/snitch/util/run_vsim.sh index 9eeee2e14c..299ef25105 100755 --- a/hw/reqrsp_interface/util/run_vsim.sh +++ b/hw/snitch/util/run_vsim.sh @@ -16,11 +16,4 @@ call_vsim() { grep "Errors: 0," vsim.log } -call_vsim axi_to_reqrsp_tb -call_vsim reqrsp_to_axi_tb -call_vsim reqrsp_mux_tb -call_vsim reqrsp_demux_tb -# Test `reqrsp_cut` -call_vsim reqrsp_idempotent_tb -gCut=1 -gIso=0 -# Test `reqrsp_iso` -call_vsim reqrsp_idempotent_tb -gCut=0 -gIso=1 +call_vsim snitch_l0_tlb_tb diff --git a/hw/snitch_cc/src/snitch_cc.sv b/hw/snitch_cc/src/snitch_cc.sv new file mode 100644 index 0000000000..cb9e85f538 --- /dev/null +++ b/hw/snitch_cc/src/snitch_cc.sv @@ -0,0 +1,1033 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// Author: Florian Zaruba + +`include "common_cells/assertions.svh" +`include "common_cells/registers.svh" +`include "snitch/typedef.svh" +`include "reqrsp_interface/typedef.svh" +`include "tcdm_interface/typedef.svh" +`include "dca_interface/typedef.svh" + +/// Snitch Core Complex (CC) +/// Contains the Snitch Integer Core + FPU + Private Accelerators +module snitch_cc + import snitch_cc_pkg::*; +#( + /// Address width of the buses + parameter int unsigned AddrWidth = 0, + /// Data width of the buses. + parameter int unsigned DataWidth = 0, + /// Address width of the TCDM bus. + parameter int unsigned TcdmAddrWidth = 0, + /// User width of the TCDM bus. + parameter int unsigned TcdmUserWidth = 0, + /// Data width of the AXI DMA buses. + parameter int unsigned DMADataWidth = 0, + /// Id width of the AXI DMA bus. + parameter int unsigned DMAIdWidth = 0, + /// User width of the AXI DMA bus. + parameter int unsigned DMAUserWidth = 0, + parameter int unsigned DMANumAxInFlight = 0, + parameter int unsigned DMAReqFifoDepth = 0, + parameter int unsigned DMANumChannels = 0, + parameter type axi_ar_chan_t = logic, + parameter type axi_aw_chan_t = logic, + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic, + parameter type hive_req_t = logic, + parameter type hive_rsp_t = logic, + parameter type dma_events_t = logic, + // XIF parameters + parameter bit EnableXif = 1, + parameter int unsigned XifIdWidth = 4, + // XIF port types + parameter type x_issue_req_t = logic, + parameter type x_issue_resp_t = logic, + parameter type x_register_t = logic, + parameter type x_commit_t = logic, + parameter type x_result_t = logic, + parameter fpnew_pkg::fpu_implementation_t FPUImplementation = '0, + /// Boot address of core. + parameter logic [31:0] BootAddr = 32'h0000_1000, + /// Core ISA configuration. + parameter snitch_pkg::isa_cfg_t IsaCfg = '0, + /// Enable private IPU. + parameter bit PrivateIpu = 0, + /// Has virtual memory support. + parameter bit VMSupport = 1, + parameter int unsigned NumIntOutstandingLoads = 0, + parameter int unsigned NumIntOutstandingMem = 0, + parameter int unsigned NumFPOutstandingLoads = 0, + parameter int unsigned NumFPOutstandingMem = 0, + parameter int unsigned NumDTLBEntries = 0, + parameter int unsigned NumITLBEntries = 0, + parameter int unsigned NumSequencerInstr = 0, + parameter int unsigned NumSequencerLoops = 0, + parameter int unsigned NumSsrs = 0, + parameter int unsigned SsrMuxRspDepth = 0, + parameter snitch_ssr_pkg::ssr_cfg_t [cc_pkg::iomsb(NumSsrs):0] SsrCfgs = '0, + parameter logic [cc_pkg::iomsb(NumSsrs):0][4:0] SsrRegs = '0, + /// Spatz parameters + parameter int unsigned NumSpatzOutstandingLoads = 4, + parameter bit SpatzDoubleBw = 0, + /// Add isochronous clock-domain crossings e.g., make it possible to operate + /// the core in a slower clock domain. + parameter bit IsoCrossing = 0, + /// Timing Parameters + /// Insert Pipeline registers into off-loading path (request) + parameter bit RegisterOffloadReq = 0, + /// Insert Pipeline registers into off-loading path (response) + parameter bit RegisterOffloadRsp = 0, + /// Insert Pipeline registers into data memory path (request) + parameter bit RegisterCoreReq = 0, + /// Insert Pipeline registers into data memory path (response) + parameter bit RegisterCoreRsp = 0, + /// Insert Pipeline register into the FPU data path (request) + parameter bit RegisterFPUReq = 0, + /// Insert Pipeline registers after sequencer + parameter bit RegisterSequencer = 0, + /// Insert Pipeline registers immediately before FPU datapath + parameter bit RegisterFPUIn = 0, + /// Insert Pipeline registers immediately after FPU datapath + parameter bit RegisterFPUOut = 0, + /// Cut DCA request to FPU + parameter bit RegisterDcaReq = 0, + /// Cut DCA response from FPU + parameter bit RegisterDcaRsp = 0, + parameter snitch_pma_pkg::snitch_pma_t SnitchPMACfg = '{default: 0}, + /// Consistency Address Queue (CAQ) parameters. + parameter int unsigned CaqDepth = 0, + parameter int unsigned CaqTagWidth = 0, + /// Enable debug support. + parameter bit DebugSupport = 1, + /// Optional fixed TCDM alias. + parameter bit TCDMAliasEnable = 1'b0, + parameter logic [AddrWidth-1:0] TCDMAliasStart = '0, + /// Width of the collective operation field + parameter int unsigned CollectiveWidth = 1, + /// Enable direct compute access (DCA). + parameter bit EnableDca = 0, + /// Derived parameter *Do not override* + localparam int unsigned NumTcdmPorts = snitch_cc_pkg::get_tcdm_ports( + IsaCfg, + NumSsrs, + spatz_pkg::N_FU, + SpatzDoubleBw + ), + localparam type addr_t = logic [AddrWidth-1:0], + localparam type lsu_req_t = `LSU_REQ_STRUCT(DataWidth, AddrWidth, snitch_pkg::UserWidth), + localparam type lsu_rsp_t = `LSU_RSP_STRUCT(DataWidth), + localparam type tcdm_req_t = `TCDM_REQ_STRUCT(DataWidth, TcdmAddrWidth, TcdmUserWidth), + localparam type tcdm_rsp_t = `TCDM_RSP_STRUCT(DataWidth), + localparam type dca_req_t = `DCA_REQ_STRUCT(DataWidth), + localparam type dca_rsp_t = `DCA_RSP_STRUCT(DataWidth) +) ( + input logic clk_i, + input logic clk_d2_i, + input logic rst_ni, + input logic rst_int_ss_ni, + input logic rst_fp_ss_ni, + input snitch_pkg::hart_id_t hart_id_i, + input snitch_pkg::interrupts_t irq_i, + output hive_req_t hive_req_o, + input hive_rsp_t hive_rsp_i, + // SoC data port + output lsu_req_t soc_req_o, + input lsu_rsp_t soc_rsp_i, + // TCDM ports + output tcdm_req_t [NumTcdmPorts-1:0] tcdm_req_o, + input tcdm_rsp_t [NumTcdmPorts-1:0] tcdm_rsp_i, + // X-interface + output x_issue_req_t x_issue_req_o, + input x_issue_resp_t x_issue_resp_i, + output logic x_issue_valid_o, + input logic x_issue_ready_i, + output x_register_t x_register_o, + output logic x_register_valid_o, + input logic x_register_ready_i, + output x_commit_t x_commit_o, + output logic x_commit_valid_o, + input x_result_t x_result_i, + input logic x_result_valid_i, + output logic x_result_ready_o, + // DMA ports + output axi_req_t [DMANumChannels-1:0] axi_dma_req_o, + input axi_rsp_t [DMANumChannels-1:0] axi_dma_res_i, + output logic [DMANumChannels-1:0] axi_dma_busy_o, + output dma_events_t [DMANumChannels-1:0] axi_dma_events_o, + // Core event strobes + output snitch_pkg::core_events_t core_events_o, + input addr_t tcdm_addr_base_i, + // Cluster HW barrier + output logic barrier_o, + input logic barrier_i, + // Direct Compute Access (DCA) interface + input dca_req_t dca_req_i, + output dca_rsp_t dca_rsp_o +); + + localparam bit NativeFpSupport = snitch_pkg::calculate_fp_enable(IsaCfg) && !IsaCfg.RVV; + localparam bit Xpulpv2 = snitch_pkg::calculate_xpulpv2(IsaCfg); + localparam int unsigned NumSpatzMemPorts = snitch_cc_pkg::num_spatz_mem_ports( + spatz_pkg::N_FU, + SpatzDoubleBw + ); + typedef logic [DataWidth-1:0] data_t; + + // Define lsu_req_chan_t and lsu_rsp_chan_t + `LSU_TYPEDEF_REQRSP_CHAN_ALL(lsu, DataWidth, AddrWidth, snitch_pkg::UserWidth) + + // Define tcdm_lsu_req_t and tcdm_lsu_rsp_t + `LSU_TYPEDEF_ALL(tcdm_lsu, DataWidth, TcdmAddrWidth, TcdmUserWidth) + + // Define tcdm_req_chan_t and tcdm_rsp_chan_t + `TCDM_TYPEDEF_REQRSP_CHAN_ALL(tcdm, DataWidth, TcdmAddrWidth, TcdmUserWidth) + + // Define dca_req_chan_t and dca_rsp_chan_t + `DCA_TYPEDEF_REQRSP_CHAN_ALL(dca, DataWidth) + + // Define acc_req_t, acc_rsp_t, acc_req_chan_t and acc_rsp_chan_t + `SNITCH_ACC_TYPEDEF_ALL(DataWidth, AddrWidth) + + // Accelerator offload interface + acc_req_t snitch_acc_req; + acc_rsp_t snitch_acc_rsp; + acc_req_t snitch_acc_req_q; + acc_rsp_t snitch_acc_rsp_q; + acc_req_t [snitch_pkg::NUM_ACC-1:0] snitch_acc_req_demuxed; + acc_rsp_t [snitch_pkg::NUM_ACC-1:0] snitch_acc_rsp_demuxed; + + // COPIFT interface + logic [31:0] i2f_rdata; + logic i2f_rvalid; + logic i2f_rready; + logic [31:0] f2i_wdata; + logic f2i_wvalid; + logic f2i_wready; + logic en_copift; + + // FPU control/status signals + fpnew_pkg::roundmode_e fpu_rnd_mode, spatz_fpu_rnd_mode, fpss_fpu_rnd_mode; + fpnew_pkg::fmt_mode_t fpu_fmt_mode, spatz_fpu_fmt_mode, fpss_fpu_fmt_mode; + fpnew_pkg::status_t fpu_status, spatz_fpu_status, fpss_fpu_status; + + // Consistency Address Queue (CAQ) interface + logic caq_pvalid, caq_pvalid_q; + + // Events + snitch_pkg::core_events_t snitch_events; + snitch_pkg::core_events_t fpss_events; + + // Snitch LSU interface + lsu_req_t snitch_lsu_req_d, snitch_lsu_req_q; + lsu_rsp_t snitch_lsu_rsp_d, snitch_lsu_rsp_q; + + // CPU-side XIF + x_issue_req_t x_issue_req; + x_issue_resp_t x_issue_resp; + logic x_issue_valid; + logic x_issue_ready; + x_register_t x_register; + logic x_register_valid; + logic x_register_ready; + x_commit_t x_commit; + logic x_commit_valid; + x_result_t x_result; + logic x_result_valid; + logic x_result_ready; + + // Registered XIF result channel + x_result_t x_result_q; + logic x_result_valid_q; + logic x_result_ready_q; + + // Coprocessor-side XIF + x_issue_req_t [NumCopro-1:0] cop_issue_req; + logic [NumCopro-1:0] cop_issue_valid; + x_issue_resp_t [NumCopro-1:0] cop_issue_resp; + logic [NumCopro-1:0] cop_issue_ready; + x_register_t [NumCopro-1:0] cop_register; + logic [NumCopro-1:0] cop_register_valid; + logic [NumCopro-1:0] cop_register_ready; + x_commit_t [NumCopro-1:0] cop_commit; + logic [NumCopro-1:0] cop_commit_valid; + x_result_t [NumCopro-1:0] cop_result; + logic [NumCopro-1:0] cop_result_valid; + logic [NumCopro-1:0] cop_result_ready; + + // FPSS LSU interface + lsu_req_t fpss_lsu_req; + lsu_rsp_t fpss_lsu_rsp; + + // Registered DCA interface + dca_req_t dca_req_q; + dca_rsp_t dca_rsp_q; + + // SSR interface + logic [2:0][4:0] ssr_raddr; + data_t [2:0] ssr_rdata; + logic [2:0] ssr_rvalid; + logic [2:0] ssr_rready; + logic [2:0] ssr_rdone; + logic [0:0][4:0] ssr_waddr; + data_t [0:0] ssr_wdata; + logic [0:0] ssr_wvalid; + logic [0:0] ssr_wready; + logic [0:0] ssr_wdone; + logic ssr_streamctl_done; + logic ssr_streamctl_valid; + logic ssr_streamctl_ready; + + // SSR TCDM interface + tcdm_req_t [cc_pkg::iomsb(NumSsrs):0] ssr_tcdm_req; + tcdm_rsp_t [cc_pkg::iomsb(NumSsrs):0] ssr_tcdm_rsp; + tcdm_req_t ssr_tcdm_req_0; + tcdm_rsp_t ssr_tcdm_rsp_0; + tcdm_req_t [cc_pkg::iomsb(NumSsrs-1):0] ssr_tcdm_req_extra; + tcdm_rsp_t [cc_pkg::iomsb(NumSsrs-1):0] ssr_tcdm_rsp_extra; + + // LSU/SSR0 muxed TCDM interface + tcdm_req_t muxed_tcdm_req; + tcdm_rsp_t muxed_tcdm_rsp; + + // Spatz FLSU interface + lsu_req_t spatz_flsu_req; + lsu_rsp_t spatz_flsu_rsp; + + // Spatz TCDM interface + tcdm_req_chan_t [NumSpatzMemPorts-1:0] spatz_tcdm_req_chan; + logic [NumSpatzMemPorts-1:0] spatz_tcdm_req_valid; + logic [NumSpatzMemPorts-1:0] spatz_tcdm_req_ready; + tcdm_rsp_chan_t [NumSpatzMemPorts-1:0] spatz_tcdm_rsp_chan; + logic [NumSpatzMemPorts-1:0] spatz_tcdm_rsp_valid; + tcdm_req_t [NumSpatzMemPorts-1:0] spatz_tcdm_req; + tcdm_rsp_t [NumSpatzMemPorts-1:0] spatz_tcdm_rsp; + + // Muxed LSU request + lsu_req_t muxed_lsu_req; + lsu_rsp_t muxed_lsu_rsp; + + // LSU request towards TCDM + lsu_req_t lsu_tcdm_req; + lsu_rsp_t lsu_tcdm_rsp; + + // LSU request resized to match TCDM bus widths + tcdm_lsu_req_t core_lsu_req_resized; + tcdm_lsu_rsp_t core_lsu_rsp_resized; + + // LSU request converted to TCDM protocol + tcdm_req_t core_tcdm_req; + tcdm_rsp_t core_tcdm_rsp; + + // Trace interfaces + // pragma translate_off + snitch_pkg::snitch_trace_t snitch_trace; + snitch_pkg::fpss_trace_t fpss_trace; + snitch_pkg::fpu_sequencer_trace_t fpu_sequencer_trace; + snitch_pkg::dca_trace_t dca_trace; + // pragma translate_on + + //////////// + // Snitch // + //////////// + + snitch #( + .BootAddr (BootAddr), + .IsaCfg (IsaCfg), + .NativeFpSupport (NativeFpSupport), + .AddrWidth (AddrWidth), + .DataWidth (DataWidth), + .VMSupport (VMSupport), + .DebugSupport (DebugSupport), + .EnableXif (EnableXif | IsaCfg.RVV), + .XifIdWidth (XifIdWidth), + .NumIntOutstandingLoads(NumIntOutstandingLoads), + .NumIntOutstandingMem (NumIntOutstandingMem), + .NumDTLBEntries (NumDTLBEntries), + .NumITLBEntries (NumITLBEntries), + .SnitchPMACfg (SnitchPMACfg), + .CaqDepth (CaqDepth), + .CaqTagWidth (CaqTagWidth) + ) i_snitch ( + .clk_i (clk_d2_i), + .rst_i (~rst_ni), + // pragma translate_off + .trace_o (snitch_trace), + // pragma translate_on + .hart_id_i, + .irq_i, + .flush_i_valid_o (hive_req_o.flush_i_valid), + .flush_i_ready_i (hive_rsp_i.flush_i_ready), + .inst_req_o (hive_req_o.instr_req), + .inst_rsp_i (hive_rsp_i.instr_rsp), + .acc_req_o (snitch_acc_req), + .acc_rsp_i (snitch_acc_rsp), + .x_issue_req_o (x_issue_req), + .x_issue_resp_i (x_issue_resp), + .x_issue_valid_o (x_issue_valid), + .x_issue_ready_i (x_issue_ready), + .x_register_o (x_register), + .x_register_valid_o(x_register_valid), + .x_register_ready_i(x_register_ready), + .x_commit_o (x_commit), + .x_commit_valid_o (x_commit_valid), + .x_result_i (x_result_q), + .x_result_valid_i (x_result_valid_q), + .x_result_ready_o (x_result_ready_q), + .i2f_rdata_o (i2f_rdata), + .i2f_rvalid_o (i2f_rvalid), + .i2f_rready_i (i2f_rready), + .f2i_wdata_i (f2i_wdata), + .f2i_wvalid_i (f2i_wvalid), + .f2i_wready_o (f2i_wready), + .caq_pvalid_i (caq_pvalid_q), + .lsu_req_o (snitch_lsu_req_d), + .lsu_rsp_i (snitch_lsu_rsp_d), + .ptw_req_o (hive_req_o.ptw_req), + .ptw_rsp_i (hive_rsp_i.ptw_rsp), + .fpu_rnd_mode_o (fpu_rnd_mode), + .fpu_fmt_mode_o (fpu_fmt_mode), + .fpu_status_i (fpu_status), + .core_events_o (snitch_events), + .barrier_o (barrier_o), + .barrier_i (barrier_i), + .en_copift_o (en_copift) + ); + + // Cut Snitch's LSU interface + reqrsp_iso #( + .req_chan_t(lsu_req_chan_t), + .rsp_chan_t(lsu_rsp_chan_t), + .BypassReq(!RegisterCoreReq), + .BypassRsp(!IsoCrossing && !RegisterCoreRsp) + ) i_data_cut ( + .src_clk_i (clk_d2_i), + .src_rst_ni(rst_ni), + .src_req_i (snitch_lsu_req_d), + .src_rsp_o (snitch_lsu_rsp_d), + .dst_clk_i (clk_i), + .dst_rst_ni(rst_ni), + .dst_req_o (snitch_lsu_req_q), + .dst_rsp_i (snitch_lsu_rsp_q) + ); + + // Cut Snitch's accelerator interface + reqrsp_cut #( + .req_chan_t(acc_req_chan_t), + .rsp_chan_t(acc_rsp_chan_t), + .BypassReq (!RegisterOffloadReq), + .BypassRsp (!RegisterOffloadRsp) + ) i_acc_cut ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .slv_req_i(snitch_acc_req), + .slv_rsp_o(snitch_acc_rsp), + .mst_req_o(snitch_acc_req_q), + .mst_rsp_i(snitch_acc_rsp_q) + ); + + // Cut CAQ response for proper handshake with divided clock + cc_isochronous_spill_register #( + .data_t(logic), + .Bypass(!IsoCrossing) + ) i_spill_register_caq_pvalid ( + .src_clk_i (clk_i), + .src_rst_ni (rst_ni), + .src_valid_i(caq_pvalid), + .src_ready_o(), + .src_data_i ('0), + .dst_clk_i (clk_d2_i), + .dst_rst_ni (rst_ni), + .dst_valid_o(caq_pvalid_q), + .dst_ready_i(1'b1), + .dst_data_o () + ); + + // Cut XIF result channel + // ---------------------- + // Break the XIF result combinational loop: a coprocessor's x_issue_ready_o + // can depend combinationally on x_result_ready_i (e.g. Spatz), which feeds + // back through the demux result arbiter and Snitch's retire logic. A + // non-bypass spill_register on the CPU-side result channel decouples the + // ready signal and cuts the loop for any coprocessor. + cc_spill_register #( + .data_t(x_result_t), + .Bypass(1'b0) + ) i_xif_result_cut ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .clr_i (1'b0), + .valid_i(x_result_valid), + .ready_o(x_result_ready), + .data_i (x_result), + .valid_o(x_result_valid_q), + .ready_i(x_result_ready_q), + .data_o (x_result_q) + ); + + // Demux FPU control/status signals to Spatz and FPSS + assign fpss_fpu_rnd_mode = fpu_rnd_mode; + assign fpss_fpu_fmt_mode = fpu_fmt_mode; + assign spatz_fpu_rnd_mode = fpu_rnd_mode; + assign spatz_fpu_fmt_mode = fpu_fmt_mode; + assign fpu_status = fpss_fpu_status | spatz_fpu_status; + + // Demux accelerator interface to all accelerators. + // NOTE: `Ordered` is explicitly disabled here to preserve this dispatch + // path's pre-existing (long-standing, not a regression) behavior, where + // responses from different accelerators are not guaranteed to be returned + // in request order. + reqrsp_demux #( + .NrPorts (snitch_pkg::NUM_ACC), + .Ordered (1'b0), + .req_chan_t(acc_req_chan_t), + .rsp_chan_t(acc_rsp_chan_t) + ) i_acc_demux ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .slv_req_i(snitch_acc_req_q), + .slv_rsp_o(snitch_acc_rsp_q), + .mst_req_o(snitch_acc_req_demuxed), + .mst_rsp_i(snitch_acc_rsp_demuxed), + .select_i (snitch_acc_req_q.q.addr[$clog2(snitch_pkg::NUM_ACC)-1:0]) + ); + + // Demux XIF to all coprocessors + cvxif_demux #( + .NumCopro (NumCopro), + .x_issue_req_t (x_issue_req_t), + .x_issue_resp_t(x_issue_resp_t), + .x_register_t (x_register_t), + .x_commit_t (x_commit_t), + .x_result_t (x_result_t) + ) i_cvxif_demux ( + .clk_i, + .rst_ni, + .cpu_issue_req_i (x_issue_req), + .cpu_issue_resp_o (x_issue_resp), + .cpu_issue_valid_i (x_issue_valid), + .cpu_issue_ready_o (x_issue_ready), + .cpu_register_i (x_register), + .cpu_register_valid_i (x_register_valid), + .cpu_register_ready_o (x_register_ready), + .cpu_commit_i (x_commit), + .cpu_commit_valid_i (x_commit_valid), + .cpu_result_o (x_result), + .cpu_result_valid_o (x_result_valid), + .cpu_result_ready_i (x_result_ready), + .copro_issue_req_o (cop_issue_req), + .copro_issue_valid_o (cop_issue_valid), + .copro_issue_resp_i (cop_issue_resp), + .copro_issue_ready_i (cop_issue_ready), + .copro_register_o (cop_register), + .copro_register_valid_o(cop_register_valid), + .copro_register_ready_i(cop_register_ready), + .copro_commit_o (cop_commit), + .copro_commit_valid_o (cop_commit_valid), + .copro_result_i (cop_result), + .copro_result_valid_i (cop_result_valid), + .copro_result_ready_o (cop_result_ready) + ); + + // Connect external coprocessor port + assign x_issue_req_o = cop_issue_req[ExternalCopro]; + assign x_issue_valid_o = cop_issue_valid[ExternalCopro]; + assign cop_issue_resp[ExternalCopro] = x_issue_resp_i; + assign cop_issue_ready[ExternalCopro] = x_issue_ready_i; + assign x_register_o = cop_register[ExternalCopro]; + assign x_register_valid_o = cop_register_valid[ExternalCopro]; + assign cop_register_ready[ExternalCopro] = x_register_ready_i; + assign x_commit_o = cop_commit[ExternalCopro]; + assign x_commit_valid_o = cop_commit_valid[ExternalCopro]; + assign cop_result[ExternalCopro] = x_result_i; + assign cop_result_valid[ExternalCopro] = x_result_valid_i; + assign x_result_ready_o = cop_result_ready[ExternalCopro]; + + ///////// + // DMA // + ///////// + + if (IsaCfg.Xdma) begin : gen_dma + idma_inst64_top #( + .AxiAddrWidth (AddrWidth), + .AxiDataWidth (DMADataWidth), + .AxiIdWidth (DMAIdWidth), + .AxiUserWidth (DMAUserWidth), + .NumAxInFlight (DMANumAxInFlight), + .DMAReqFifoDepth(DMAReqFifoDepth), + .NumChannels (DMANumChannels), + .DMATracing (1), + .axi_ar_chan_t (axi_ar_chan_t), + .axi_aw_chan_t (axi_aw_chan_t), + .axi_req_t (axi_req_t), + .axi_res_t (axi_rsp_t), + .acc_req_t (acc_req_chan_t), + .acc_res_t (acc_rsp_chan_t), + .dma_events_t (dma_events_t) + ) i_idma_inst64_top ( + .clk_i, + .rst_ni, + .axi_req_o (axi_dma_req_o), + .axi_res_i (axi_dma_res_i), + .busy_o (axi_dma_busy_o), + .acc_req_i (snitch_acc_req_demuxed[snitch_pkg::DMA_SS].q), + .acc_req_valid_i(snitch_acc_req_demuxed[snitch_pkg::DMA_SS].q_valid), + .acc_req_ready_o(snitch_acc_rsp_demuxed[snitch_pkg::DMA_SS].q_ready), + .acc_res_o (snitch_acc_rsp_demuxed[snitch_pkg::DMA_SS].p), + .acc_res_valid_o(snitch_acc_rsp_demuxed[snitch_pkg::DMA_SS].p_valid), + .acc_res_ready_i(snitch_acc_req_demuxed[snitch_pkg::DMA_SS].p_ready), + .hart_id_i (hart_id_i), + .events_o (axi_dma_events_o) + ); + end else begin : gen_no_dma + assign axi_dma_req_o = '0; + assign axi_dma_busy_o = '0; + assign snitch_acc_rsp_demuxed[snitch_pkg::DMA_SS] = '0; + assign axi_dma_events_o = '0; + end + + ///////// + // IPU // + ///////// + + if (PrivateIpu) begin : gen_ipu + snitch_ipu #( + .IdWidth (5), + .Xpulpv2 (Xpulpv2), + .acc_rsp_t(acc_rsp_t), + .acc_req_t(acc_req_t) + ) i_snitch_ipu ( + .clk_i, + .rst_ni, + .acc_req_i(snitch_acc_req_demuxed[snitch_pkg::IPU]), + .acc_rsp_o(snitch_acc_rsp_demuxed[snitch_pkg::IPU]) + ); + assign hive_req_o.acc_req = '0; + end else begin + assign hive_req_o.acc_req = snitch_acc_req_demuxed[snitch_pkg::IPU]; + assign snitch_acc_rsp_demuxed[snitch_pkg::IPU] = hive_rsp_i.acc_rsp; + end + + ////////////////// + // FP subsystem // + ////////////////// + + // Cut DCA interface + reqrsp_cut #( + .req_chan_t(dca_req_chan_t), + .rsp_chan_t(dca_rsp_chan_t), + .BypassReq (!EnableDca || !RegisterDcaReq), + .BypassRsp (!EnableDca || !RegisterDcaRsp) + ) i_dca_cut ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .slv_req_i(dca_req_i), + .slv_rsp_o(dca_rsp_o), + .mst_req_o(dca_req_q), + .mst_rsp_i(dca_rsp_q) + ); + + if (NativeFpSupport) begin : gen_fpu + snitch_fp_ss #( + .AddrWidth (AddrWidth), + .DataWidth (DataWidth), + .NumFPOutstandingLoads(NumFPOutstandingLoads), + .NumFPOutstandingMem (NumFPOutstandingMem), + .NumFPUSequencerInstr (NumSequencerInstr), + .NumFPUSequencerLoops (NumSequencerLoops), + .FpuImplementation (FPUImplementation), + .IsaCfg (IsaCfg), + .NumSsrs (NumSsrs), + .SsrRegs (SsrRegs), + .RegisterSequencer (RegisterSequencer), + .RegisterFpuReq (RegisterFPUIn), + .RegisterFpuRsp (RegisterFPUOut), + .EnableDca (EnableDca) + ) i_snitch_fp_ss ( + .clk_i, + .rst_i (~rst_ni | (~rst_fp_ss_ni)), + // pragma translate_off + .trace_o (fpss_trace), + .sequencer_trace_o (fpu_sequencer_trace), + .dca_trace_o (dca_trace), + // pragma translate_on + .hart_id_i (hart_id_i), + .acc_req_i (snitch_acc_req_demuxed[snitch_pkg::FP_SS]), + .acc_rsp_o (snitch_acc_rsp_demuxed[snitch_pkg::FP_SS]), + .i2f_rdata_i (i2f_rdata), + .i2f_rvalid_i (i2f_rvalid), + .i2f_rready_o (i2f_rready), + .f2i_wdata_o (f2i_wdata), + .f2i_wvalid_o (f2i_wvalid), + .f2i_wready_i (f2i_wready), + .caq_pvalid_o (caq_pvalid), + .data_req_o (fpss_lsu_req), + .data_rsp_i (fpss_lsu_rsp), + .fpu_rnd_mode_i (fpss_fpu_rnd_mode), + .fpu_fmt_mode_i (fpss_fpu_fmt_mode), + .fpu_status_o (fpss_fpu_status), + .ssr_raddr_o (ssr_raddr), + .ssr_rdata_i (ssr_rdata), + .ssr_rvalid_o (ssr_rvalid), + .ssr_rready_i (ssr_rready), + .ssr_rdone_o (ssr_rdone), + .ssr_waddr_o (ssr_waddr), + .ssr_wdata_o (ssr_wdata), + .ssr_wvalid_o (ssr_wvalid), + .ssr_wready_i (ssr_wready), + .ssr_wdone_o (ssr_wdone), + .streamctl_done_i (ssr_streamctl_done), + .streamctl_valid_i (ssr_streamctl_valid), + .streamctl_ready_o (ssr_streamctl_ready), + .core_events_o (fpss_events), + .en_copift_i (en_copift), + .dca_req_i (dca_req_q), + .dca_rsp_o (dca_rsp_q) + ); + end else begin : gen_no_fpu + assign fpss_trace = '0; + assign fpu_sequencer_trace = '0; + assign dca_trace = '0; + assign snitch_acc_rsp_demuxed[snitch_pkg::FP_SS] = '0; + assign i2f_rready = '0; + assign f2i_wdata = '0; + assign f2i_wvalid = '0; + assign caq_pvalid = '0; + assign fpss_lsu_req = '0; + assign fpss_fpu_status = '0; + assign ssr_raddr = '0; + assign ssr_rvalid = '0; + assign ssr_rdone = '0; + assign ssr_waddr = '0; + assign ssr_wdata = '0; + assign ssr_wvalid = '0; + assign ssr_wdone = '0; + assign ssr_streamctl_ready = '0; + assign fpss_events = '0; + assign dca_rsp_q = '0; + end + + /////////// + // Spatz // + /////////// + + if (IsaCfg.RVV) begin : gen_spatz + spatz #( + .NrMemPorts (NumSpatzMemPorts), + .NumOutstandingLoads(NumSpatzOutstandingLoads), + .FPUImplementation (FPUImplementation), + .AddrWidth (AddrWidth), + .RegisterRsp (RegisterOffloadRsp), + .dreq_t (lsu_req_t), + .drsp_t (lsu_rsp_t), + .spatz_mem_req_t (tcdm_req_chan_t), + .spatz_mem_rsp_t (tcdm_rsp_chan_t), + // X-IF types (used; Spatz must be compiled with `define X_INTERFACE). + .x_issue_req_t (x_issue_req_t), + .x_issue_resp_t (x_issue_resp_t), + .x_register_t (x_register_t), + .x_commit_t (x_commit_t), + .x_result_t (x_result_t) + ) i_spatz ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .testmode_i (1'b0), + .hart_id_i (hart_id_i), + .x_issue_valid_i (cop_issue_valid[SpatzCopro]), + .x_issue_ready_o (cop_issue_ready[SpatzCopro]), + .x_issue_req_i (cop_issue_req[SpatzCopro]), + .x_issue_resp_o (cop_issue_resp[SpatzCopro]), + .x_register_valid_i (cop_register_valid[SpatzCopro]), + .x_register_ready_o (cop_register_ready[SpatzCopro]), + .x_register_i (cop_register[SpatzCopro]), + .x_commit_valid_i (cop_commit_valid[SpatzCopro]), + .x_commit_i (cop_commit[SpatzCopro]), + .x_result_valid_o (cop_result_valid[SpatzCopro]), + .x_result_ready_i (cop_result_ready[SpatzCopro]), + .x_result_o (cop_result[SpatzCopro]), + .spatz_mem_req_o (spatz_tcdm_req_chan), + .spatz_mem_req_valid_o (spatz_tcdm_req_valid), + .spatz_mem_req_ready_i (spatz_tcdm_req_ready), + .spatz_mem_rsp_i (spatz_tcdm_rsp_chan), + .spatz_mem_rsp_valid_i (spatz_tcdm_rsp_valid), + .spatz_mem_finished_o (/*TODO: wire to fence instruction*/), + .spatz_mem_str_finished_o(), + .fp_lsu_mem_req_o (spatz_flsu_req), + .fp_lsu_mem_rsp_i (spatz_flsu_rsp), + .fpu_rnd_mode_i (spatz_fpu_rnd_mode), + .fpu_fmt_mode_i (spatz_fpu_fmt_mode), + .fpu_status_o (spatz_fpu_status) + ); + + // Convert Spatz TCDM requests to TCDM protocol + for (genvar p = 0; p < NumSpatzMemPorts; p++) begin: gen_spatz_tcdm_assignment + assign spatz_tcdm_req[p] = '{ + q: spatz_tcdm_req_chan[p], + q_valid: spatz_tcdm_req_valid[p] + }; + assign spatz_tcdm_req_ready[p] = spatz_tcdm_rsp[p].q_ready; + assign spatz_tcdm_rsp_chan[p] = spatz_tcdm_rsp[p].p; + assign spatz_tcdm_rsp_valid[p] = spatz_tcdm_rsp[p].p_valid; + end + + end else begin : gen_no_spatz + assign cop_issue_ready[SpatzCopro] = '0; + assign cop_issue_resp[SpatzCopro] = '0; + assign cop_register_ready[SpatzCopro] = '0; + assign cop_result_valid[SpatzCopro] = '0; + assign cop_result[SpatzCopro] = '0; + assign spatz_tcdm_req = '0; + assign spatz_flsu_req = '0; + assign spatz_fpu_status = '0; + end + + ///////////////////////////////////////////// + // Mux Snitch, FPSS and Spatz LSU requests // + ///////////////////////////////////////////// + + reqrsp_mux #( + .NrPorts (3), + .req_chan_t (lsu_req_chan_t), + .rsp_chan_t (lsu_rsp_chan_t), + // TODO(zarubaf): Wire-up to top-level. + .RspDepth (8), + .RegisterReq({1'b0, RegisterFPUReq, RegisterFPUReq}) + ) i_reqrsp_mux ( + .clk_i, + .rst_ni, + .slv_req_i ({snitch_lsu_req_q, fpss_lsu_req, spatz_flsu_req}), + .slv_rsp_o ({snitch_lsu_rsp_q, fpss_lsu_rsp, spatz_flsu_rsp}), + .mst_req_o (muxed_lsu_req), + .mst_rsp_i (muxed_lsu_rsp), + .rsp_route_i('0), + .idx_o () + ); + + ////////////////////////////// + // Demux LSU -> SoC or TCDM // + ////////////////////////////// + + typedef struct packed { + int unsigned idx; + logic [AddrWidth-1:0] base; + logic [AddrWidth-1:0] mask; + } reqrsp_rule_t; + + // Define the addrmap for the demux select logic. + reqrsp_rule_t [TCDMAliasEnable:0] addr_map; + assign addr_map[0] = '{ + idx: DreqSelectTcdm, + base: tcdm_addr_base_i, + mask: ({AddrWidth{1'b1}} << TcdmAddrWidth) + }; + if (TCDMAliasEnable) begin : gen_tcdm_alias_rule + assign addr_map[1] = '{ + idx: DreqSelectTcdm, + base: TCDMAliasStart, + mask: ({AddrWidth{1'b1}} << TcdmAddrWidth) + }; + end + + // Collective communication operations are performed within the interconnect at the SoC + // level. However, requests destined to the TCDM never arrive at the SoC interconnect, + // as they are routed internally within the cluster. In order for collectives destined to + // the TCDM to work, we need to handle them differently, and always forward them to the + // SoC interconnect, which will reroute them back to the TCDM from outside the cluster. + // The collective mask, in the user field, is used to detect collective operations. + addr_t collective_mask; + logic is_collective; + assign collective_mask = addr_t'(muxed_lsu_req.q.user[CollectiveWidth+:AddrWidth]); + assign is_collective = (collective_mask != 0); + + reqrsp_demux_mapped #( + .NrPorts (2), + .req_chan_t(lsu_req_chan_t), + .rsp_chan_t(lsu_rsp_chan_t), + // TODO(zarubaf): Make a parameter. + .RspDepth (4), + .NoRules (1 + TCDMAliasEnable), + .addr_t (logic [AddrWidth-1:0]), + .rule_t (reqrsp_rule_t) + ) i_reqrsp_demux_mapped ( + .clk_i, + .rst_ni, + .addr_map_i (addr_map), + .default_select_i (DreqSelectSoc), + .ext_select_i (DreqSelectSoc), + .ext_select_override_i(is_collective), + .slv_req_i (muxed_lsu_req), + .slv_rsp_o (muxed_lsu_rsp), + .mst_req_o ({lsu_tcdm_req, soc_req_o}), + .mst_rsp_i ({lsu_tcdm_rsp, soc_rsp_i}) + ); + + // Resize LSU request to match TCDM bus widths + lsu_width_converter #( + .InAddrWidth (AddrWidth), + .InDataWidth (DataWidth), + .InUserWidth (snitch_pkg::UserWidth), + .OutAddrWidth(TcdmAddrWidth), + .OutDataWidth(DataWidth), + .OutUserWidth(TcdmUserWidth) + ) i_lsu_width_converter ( + .lsu_req_i(lsu_tcdm_req), + .lsu_rsp_o(lsu_tcdm_rsp), + .lsu_req_o(core_lsu_req_resized), + .lsu_rsp_i(core_lsu_rsp_resized) + ); + + // Convert LSU request to TCDM protocol + lsu_to_tcdm #( + // TODO(zarubaf): Make a parameter. + .BufDepth (4), + .AddrWidth(TcdmAddrWidth), + .UserWidth(TcdmUserWidth), + .DataWidth(DataWidth) + ) i_lsu_to_tcdm ( + .clk_i, + .rst_ni, + .lsu_req_i (core_lsu_req_resized), + .lsu_rsp_o (core_lsu_rsp_resized), + .tcdm_req_o(core_tcdm_req), + .tcdm_rsp_i(core_tcdm_rsp) + ); + + ////////// + // SSRs // + ////////// + + snitch_ssr_subsystem #( + .IsaCfg (IsaCfg), + .NumSsrs (NumSsrs), + .SsrCfgs (SsrCfgs), + .SsrRegs (SsrRegs), + .SsrMuxRspDepth(SsrMuxRspDepth), + .TcdmAddrWidth (TcdmAddrWidth), + .DataWidth (DataWidth), + .TcdmUserWidth (TcdmUserWidth), + .acc_req_t (acc_req_t), + .acc_rsp_t (acc_rsp_t), + .tcdm_req_t (tcdm_req_t), + .tcdm_rsp_t (tcdm_rsp_t) + ) i_snitch_ssr_subsystem ( + .clk_i, + .rst_ni, + .acc_req_i (snitch_acc_req_demuxed[snitch_pkg::SSR_CFG]), + .acc_rsp_o (snitch_acc_rsp_demuxed[snitch_pkg::SSR_CFG]), + .ssr_raddr_i (ssr_raddr), + .ssr_rdata_o (ssr_rdata), + .ssr_rvalid_i (ssr_rvalid), + .ssr_rready_o (ssr_rready), + .ssr_rdone_i (ssr_rdone), + .ssr_waddr_i (ssr_waddr), + .ssr_wdata_i (ssr_wdata), + .ssr_wvalid_i (ssr_wvalid), + .ssr_wready_o (ssr_wready), + .ssr_wdone_i (ssr_wdone), + .ssr_streamctl_done_o (ssr_streamctl_done), + .ssr_streamctl_valid_o(ssr_streamctl_valid), + .ssr_streamctl_ready_i(ssr_streamctl_ready), + .tcdm_req_o (ssr_tcdm_req), + .tcdm_rsp_i (ssr_tcdm_rsp) + ); + + // Separate SSR0 TCDM request, to mux with core TCDM request + assign ssr_tcdm_req_0 = ssr_tcdm_req[0]; + assign ssr_tcdm_rsp[0] = ssr_tcdm_rsp_0; + if (NumSsrs > 1) begin : gen_multi_ssr + assign ssr_tcdm_req_extra = ssr_tcdm_req[NumSsrs-1:1]; + assign ssr_tcdm_rsp[NumSsrs-1:1] = ssr_tcdm_rsp_extra; + end + + // Mux TCDM requests from core and SSR0 onto TCDM port 0 + tcdm_mux #( + .NrPorts (2), + .RspDepth (SsrMuxRspDepth), + .AddrWidth(TcdmAddrWidth), + .DataWidth(DataWidth), + .UserWidth(TcdmUserWidth) + ) i_tcdm_mux ( + .clk_i, + .rst_ni, + .slv_req_i({core_tcdm_req, ssr_tcdm_req_0}), + .slv_rsp_o({core_tcdm_rsp, ssr_tcdm_rsp_0}), + .mst_req_o(muxed_tcdm_req), + .mst_rsp_i(muxed_tcdm_rsp) + ); + + // Pack TCDM requests from SSRs[>0] and Spatz onto higher TCDM ports + always_comb begin + automatic int unsigned i; + i = 0; + tcdm_req_o[i] = muxed_tcdm_req; + muxed_tcdm_rsp = tcdm_rsp_i[i]; + i++; + if (NumSsrs > 1) begin + for (int j = 0; j < NumSsrs - 1; j++) begin + tcdm_req_o[i] = ssr_tcdm_req_extra[j]; + ssr_tcdm_rsp_extra[j] = tcdm_rsp_i[i]; + i++; + end + end + if (IsaCfg.RVV) begin + for (int j = 0; j < NumSpatzMemPorts; j++) begin + tcdm_req_o[i] = spatz_tcdm_req[j]; + spatz_tcdm_rsp[j] = tcdm_rsp_i[i]; + i++; + end + end + end + + ///////////////// + // Core events // + ///////////////// + + always_comb begin + core_events_o = snitch_events; + core_events_o.issue_fpu = fpss_events.issue_fpu; + core_events_o.issue_fpu_seq = fpss_events.issue_fpu_seq; + core_events_o.issue_core_to_fpu = fpss_events.issue_core_to_fpu; + end + + //////////// + // Tracer // + //////////// + +`ifndef TRACE_OFF + // pragma translate_off + snitch_tracer #( + .FpEn (NativeFpSupport), + .Xfrep (IsaCfg.Xfrep), + .EnableDca(EnableDca) + ) i_snitch_tracer ( + .clk_i, + .rst_ni, + .hart_id_i, + .trace_port_i (snitch_trace), + .fpss_trace_i (fpss_trace), + .fpu_sequencer_trace_i(fpu_sequencer_trace), + .dca_trace_i (dca_trace) + ); + // pragma translate_on +`endif + + //////////////// + // Assertions // + //////////////// + + // Boot addr must be aligned to 4 bytes (32-bit instruction) + `ASSERT_INIT(BootAddrAligned, BootAddr[1:0] == 2'b00) + + // DCA extension currently only supports 64-bit datawidth + `ASSERT_INIT(DcaCoreConfiguration, (!EnableDca) || IsaCfg.RVD) + `ASSERT_INIT(DcaDataWidth, (!EnableDca) || (DataWidth == 64)) + + // Spatz and SSRs/FREP/DCA are not compatible + `ASSERT_INIT(IllegalSpatzSsrCombo, (!IsaCfg.RVV) || (!IsaCfg.Xssr)) + `ASSERT_INIT(IllegalSpatzFrepCombo, (!IsaCfg.RVV) || (!IsaCfg.Xfrep)) + `ASSERT_INIT(IllegalSpatzDcaCombo, (!IsaCfg.RVV) || !EnableDca) + +endmodule diff --git a/hw/snitch_cc/src/snitch_cc_pkg.sv b/hw/snitch_cc/src/snitch_cc_pkg.sv new file mode 100644 index 0000000000..fc20df52f0 --- /dev/null +++ b/hw/snitch_cc/src/snitch_cc_pkg.sv @@ -0,0 +1,41 @@ +// Copyright 2021 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +package snitch_cc_pkg; + + // LSU requests can go either to the TCDM or out of the cluster to the SoC. + localparam int unsigned DreqPaths = 2; + localparam int unsigned DreqSelectWidth = cc_pkg::idx_width(DreqPaths); + typedef logic [DreqSelectWidth-1:0] dreq_select_t; + typedef enum dreq_select_t {DreqSelectTcdm = 1, DreqSelectSoc = 0} dreq_select_e; + + // Coprocessor IDs + typedef enum logic [1:0] { + ExternalCopro = 0, + SpatzCopro = 1, + NumCopro = 2 + } copro_id_e; + + function automatic int unsigned num_spatz_mem_ports( + int unsigned spatz_num_fu, + bit spatz_double_bw + ); + return spatz_double_bw ? spatz_num_fu * 2 : spatz_num_fu; + endfunction + + function automatic int unsigned get_tcdm_ports( + snitch_pkg::isa_cfg_t isa, + int unsigned num_ssrs, + int unsigned spatz_num_fu, + bit spatz_double_bw + ); + int unsigned ssr_ports, spatz_ports; + ssr_ports = num_ssrs; + spatz_ports = isa.RVV ? num_spatz_mem_ports(spatz_num_fu, spatz_double_bw) : 0; + // SSR 0 shares port with LSU, take the maximum between one port + // and the number of SSR ports. + return cc_pkg::max(ssr_ports, 1) + spatz_ports; + endfunction + +endpackage diff --git a/hw/snitch_cc/src/snitch_ssr_subsystem.sv b/hw/snitch_cc/src/snitch_ssr_subsystem.sv new file mode 100644 index 0000000000..2d8646ad30 --- /dev/null +++ b/hw/snitch_cc/src/snitch_ssr_subsystem.sv @@ -0,0 +1,211 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Author: Florian Zaruba + +`include "common_cells/assertions.svh" +`include "common_cells/registers.svh" + +/// Stream Semantic Register (SSR) subsystem of the Snitch Core Complex (CC). +/// Decodes the SCFG* configuration instructions offloaded on the accelerator +/// bus, drives the SSR streamer, and muxes the resulting TCDM traffic with +/// the core's own TCDM port. If `IsaCfg.Xssr` is disabled, the core TCDM port +/// is simply passed through and the SSR interfaces are tied off. +module snitch_ssr_subsystem #( + parameter snitch_pkg::isa_cfg_t IsaCfg = '0, + parameter int unsigned NumSsrs = 0, + parameter snitch_ssr_pkg::ssr_cfg_t [cc_pkg::iomsb(NumSsrs):0] SsrCfgs = '0, + parameter logic [cc_pkg::iomsb(NumSsrs):0][4:0] SsrRegs = '0, + parameter int unsigned SsrMuxRspDepth = 0, + parameter int unsigned TcdmAddrWidth = 0, + parameter int unsigned DataWidth = 0, + parameter int unsigned TcdmUserWidth = 0, + parameter type acc_req_t = logic, + parameter type acc_rsp_t = logic, + parameter type tcdm_req_t = logic, + parameter type tcdm_rsp_t = logic, + /// Derived parameter *Do not override* + localparam type data_t = logic [DataWidth-1:0] +) ( + input logic clk_i, + input logic rst_ni, + // SSR configuration - accelerator bus (SSR_CFG offload) + input acc_req_t acc_req_i, + output acc_rsp_t acc_rsp_o, + // SSR data streams - FP subsystem side + input logic [2:0][4:0] ssr_raddr_i, + output data_t [2:0] ssr_rdata_o, + input logic [2:0] ssr_rvalid_i, + output logic [2:0] ssr_rready_o, + input logic [2:0] ssr_rdone_i, + input logic [0:0][4:0] ssr_waddr_i, + input data_t [0:0] ssr_wdata_i, + input logic [0:0] ssr_wvalid_i, + output logic [0:0] ssr_wready_o, + input logic [0:0] ssr_wdone_i, + output logic ssr_streamctl_done_o, + output logic ssr_streamctl_valid_o, + input logic ssr_streamctl_ready_i, + // TCDM ports + output tcdm_req_t [NumSsrs-1:0] tcdm_req_o, + input tcdm_rsp_t [NumSsrs-1:0] tcdm_rsp_i +); + + typedef struct packed { + logic [4:0] id; + logic [11:0] word; + logic [31:0] data; + logic write; + } ssr_cfg_req_t; + + typedef struct packed { + logic [4:0] id; + logic [31:0] data; + } ssr_cfg_rsp_t; + + logic ssr_qvalid, ssr_qready; + logic ssr_pvalid, ssr_pready; + + assign ssr_qvalid = acc_req_i.q_valid; + assign ssr_pready = acc_req_i.p_ready; + assign acc_rsp_o.q_ready = ssr_qready; + assign acc_rsp_o.p_valid = ssr_pvalid; + + if (IsaCfg.Xssr) begin : gen_ssrs + tcdm_req_t [NumSsrs-1:0] ssr_req; + tcdm_rsp_t [NumSsrs-1:0] ssr_rsp; + tcdm_req_t tcdm_req; + tcdm_rsp_t tcdm_rsp; + + ssr_cfg_req_t ssr_cfg_req, cfg_req; + ssr_cfg_rsp_t ssr_cfg_rsp, cfg_rsp; + + logic cfg_req_valid, cfg_req_valid_q; + logic cfg_req_wready, cfg_req_ready, cfg_req_hs; + logic [31:0] cfg_rsp_data; + assign cfg_req_ready = ~cfg_req.write | cfg_req_wready; + assign cfg_req_hs = cfg_req_valid & cfg_req_ready; + `FF(cfg_req_valid_q, cfg_req_hs, 0) + `FFL(cfg_rsp.id, ssr_cfg_req.id, cfg_req_hs, 0) + `FFL(cfg_rsp.data, cfg_rsp_data, cfg_req_hs, 0) + + // SSR config decoder + always_comb begin + import snitch_riscv_instr::*; + automatic logic [11:0] addr; + automatic logic [4:0] addr_dm; + automatic logic [6:0] addr_reg; + + ssr_cfg_req.id = acc_req_i.q.id; + ssr_cfg_req.data = acc_req_i.q.data_arga[31:0]; + ssr_cfg_req.word = '0; + ssr_cfg_req.write = '0; + + addr = '0; + unique casez (acc_req_i.q.data_op) + SCFGRI, + SCFGWI: begin + addr = acc_req_i.q.data_op[31:20]; + end + SCFGR, + SCFGW: begin + addr = acc_req_i.q.data_argb[31:0]; + end + default: ; + endcase + + addr_reg = addr[11:5]; + addr_dm = addr[4:0]; + ssr_cfg_req.word = {addr_dm, addr_reg}; + + unique casez (acc_req_i.q.data_op) + SCFGRI, + SCFGR: + ssr_cfg_req.write = '0; + SCFGWI, + SCFGW: begin + ssr_cfg_req.write = '1; + ssr_cfg_req.id = '0; // prevent write-back of result + end + default: ; + endcase + end + + assign acc_rsp_o.p.id = ssr_cfg_rsp.id; + assign acc_rsp_o.p.error = 1'b0; + assign acc_rsp_o.p.data = ssr_cfg_rsp.data; + + cc_stream_to_mem #( + .mem_req_t (ssr_cfg_req_t), + .mem_resp_t(ssr_cfg_rsp_t), + .BufDepth (1) + ) i_stream_to_mem ( + .clk_i, + .rst_ni, + .clr_i (1'b0), + .req_i (ssr_cfg_req), + .req_valid_i (ssr_qvalid), + .req_ready_o (ssr_qready), + .resp_o (ssr_cfg_rsp), + .resp_valid_o (ssr_pvalid), + .resp_ready_i (ssr_pready), + .mem_req_o (cfg_req), + .mem_req_valid_o (cfg_req_valid), + .mem_req_ready_i (cfg_req_ready), + .mem_resp_i (cfg_rsp), + .mem_resp_valid_i(cfg_req_valid_q) + ); + + snitch_ssr_streamer #( + .NumSsrs (NumSsrs), + .RPorts (3), + .WPorts (1), + .SsrCfgs (SsrCfgs), + .SsrRegs (SsrRegs), + .AddrWidth (TcdmAddrWidth), + .DataWidth (DataWidth), + .UserWidth (TcdmUserWidth), + .tcdm_req_t(tcdm_req_t), + .tcdm_rsp_t(tcdm_rsp_t) + ) i_snitch_ssr_streamer ( + .clk_i, + .rst_ni (rst_ni), + .cfg_word_i (cfg_req.word), + .cfg_write_i (cfg_req.write & cfg_req_valid), + .cfg_rdata_o (cfg_rsp_data), + .cfg_wdata_i (cfg_req.data), + .cfg_wready_o (cfg_req_wready), + .ssr_raddr_i (ssr_raddr_i), + .ssr_rdata_o (ssr_rdata_o), + .ssr_rvalid_i (ssr_rvalid_i), + .ssr_rready_o (ssr_rready_o), + .ssr_rdone_i (ssr_rdone_i), + .ssr_waddr_i (ssr_waddr_i), + .ssr_wdata_i (ssr_wdata_i), + .ssr_wvalid_i (ssr_wvalid_i), + .ssr_wready_o (ssr_wready_o), + .ssr_wdone_i (ssr_wdone_i), + .mem_req_o (tcdm_req_o), + .mem_rsp_i (tcdm_rsp_i), + .streamctl_done_o (ssr_streamctl_done_o), + .streamctl_valid_o(ssr_streamctl_valid_o), + .streamctl_ready_i(ssr_streamctl_ready_i) + ); + + end else begin : gen_no_ssrs + assign acc_rsp_o.p = '0; + assign ssr_qready = '0; + assign ssr_pvalid = '0; + assign ssr_rdata_o = '0; + assign ssr_rready_o = '0; + assign ssr_wready_o = '0; + assign tcdm_req_o = '0; + assign ssr_streamctl_done_o = '0; + assign ssr_streamctl_valid_o = '0; + end + + // If Xssr is enabled, we should at least have one SSR + `ASSERT_INIT(InvalidNumSsrs, (!IsaCfg.Xssr) || (NumSsrs >= 1)); + +endmodule diff --git a/hw/snitch_cc/src/snitch_tracer.sv b/hw/snitch_cc/src/snitch_tracer.sv new file mode 100644 index 0000000000..c329751fe4 --- /dev/null +++ b/hw/snitch_cc/src/snitch_tracer.sv @@ -0,0 +1,115 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Author: Florian Zaruba +// +// Simulation-only instruction tracer for the Snitch Core Complex (CC). +// Emits one DASM trace line per retired/stalled Snitch, FPU, FPU-sequencer, +// and DCA event to `logs/trace_hart_.dasm`. + +// pragma translate_off +module snitch_tracer #( + parameter bit FpEn = 0, + parameter bit Xfrep = 0, + parameter bit EnableDca = 0 +) ( + input logic clk_i, + input logic rst_ni, + input snitch_pkg::hart_id_t hart_id_i, + input snitch_pkg::snitch_trace_t trace_port_i, + input snitch_pkg::fpss_trace_t fpss_trace_i, + input snitch_pkg::fpu_sequencer_trace_t fpu_sequencer_trace_i, + input snitch_pkg::dca_trace_t dca_trace_i +); + + int f; + string fn; + logic [63:0] cycle; + initial begin + // We need to schedule the assignment into a safe region, otherwise + // `hart_id_i` won't have a value assigned at the beginning of the first + // delta cycle. +`ifndef VERILATOR + #0; +`endif + $system("mkdir logs -p"); + $sformat(fn, "logs/trace_hart_%05x.dasm", hart_id_i); + f = $fopen(fn, "w"); + $display("[Tracer] Logging Hart %d to %s", hart_id_i, fn); + end + + // verilog_lint: waive-start always-ff-non-blocking + always_ff @(posedge clk_i or negedge rst_ni) begin + automatic string trace_entry; + + if (rst_ni) begin + cycle++; + // Trace snitch iff: + // we are not stalled <==> we have issued and processed an instruction (including offloads) + // OR we are retiring (issuing a writeback from) a load or accelerator instruction + if ( + !trace_port_i.extras.stall || trace_port_i.extras.retire_load + || trace_port_i.extras.retire_acc + ) begin + $sformat(trace_entry, "%t %1d %8d 0x%h DASM(%h) #; %s\n", + $time, cycle, trace_port_i.priv_lvl_q, trace_port_i.pc_q, trace_port_i.instr, + snitch_pkg::print_snitch_extras(trace_port_i.extras)); + $fwrite(f, trace_entry); +`ifdef DEBUG + $fflush(f); +`endif + end + if (FpEn) begin + // Trace FPU iff: + // an incoming handshake on the accelerator bus occurs <==> an instruction was issued + // OR an FPU result is ready to be written back to an FPR register or the bus + // OR an LSU result is ready to be written back to an FPR register or the bus + // OR an FPU result, LSU result or bus value is ready to be written back to an FPR register + if (fpss_trace_i.acc_q_hs || fpss_trace_i.fpu_out_hs + || fpss_trace_i.lsu_q_hs || fpss_trace_i.fpr_we) begin + $sformat(trace_entry, "%t %1d %8d 0x%h DASM(%h) #; %s\n", + $time, cycle, trace_port_i.priv_lvl_q, 32'hz, fpss_trace_i.op_in, + snitch_pkg::print_fpss_extras(fpss_trace_i)); + $fwrite(f, trace_entry); +`ifdef DEBUG + $fflush(f); +`endif + end + // sequencer instructions + if (Xfrep) begin + if (fpu_sequencer_trace_i.cbuf_push) begin + $sformat(trace_entry, "%t %1d %8d 0x%h DASM(%h) #; %s\n", + $time, cycle, trace_port_i.priv_lvl_q, 32'hz, 64'hz, + snitch_pkg::print_fpu_sequencer_extras(fpu_sequencer_trace_i)); + $fwrite(f, trace_entry); +`ifdef DEBUG + $fflush(f); +`endif + end + end + end + if (EnableDca) begin + // Trace DCA iff a request or response handshake occurs + if (dca_trace_i.req_hs || dca_trace_i.rsp_hs) begin + $sformat(trace_entry, "%t %1d %8d 0x%h DASM(%h) #; %s\n", + $time, cycle, trace_port_i.priv_lvl_q, 32'hz, dca_trace_i.op, + snitch_pkg::print_dca_extras(dca_trace_i)); + $fwrite(f, trace_entry); +`ifdef DEBUG + $fflush(f); +`endif + end + end + end else begin + cycle = '0; + end + end + + final begin + $fclose(f); + end + // verilog_lint: waive-stop always-ff-non-blocking + +endmodule +// pragma translate_on diff --git a/hw/snitch_cc/src/spatz_cfg.json.tpl b/hw/snitch_cc/src/spatz_cfg.json.tpl new file mode 100644 index 0000000000..c032e0c8d1 --- /dev/null +++ b/hw/snitch_cc/src/spatz_cfg.json.tpl @@ -0,0 +1,18 @@ +// Copyright 2026 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +<%! + import dataclasses + import json + + def _default(obj): + if dataclasses.is_dataclass(obj): + return dataclasses.asdict(obj) + return vars(obj) +%>\ +${json.dumps( + {'spatz': cfg['cluster']['hives'][0]['cores'][0]['spatz']}, + indent=4, + default=_default +)} \ No newline at end of file diff --git a/hw/snitch_cluster/src/snitch_amo_shim.sv b/hw/snitch_cluster/src/snitch_amo_shim.sv index 24a12446b9..c14000cc1e 100644 --- a/hw/snitch_cluster/src/snitch_amo_shim.sv +++ b/hw/snitch_cluster/src/snitch_amo_shim.sv @@ -15,8 +15,7 @@ /// LR/SC reservations are happening on `DataWidth` granularity. module snitch_amo_shim - import snitch_pkg::*; - import snitch_pkg::*; + import lsu_pkg::*; #( /// Address width. parameter int unsigned AddrMemWidth = 32, @@ -258,7 +257,9 @@ module snitch_amo_shim endmodule /// Simple ALU supporting atomic memory operations. -module snitch_amo_alu import snitch_pkg::*; ( +module snitch_amo_alu + import lsu_pkg::*; +( input amo_op_e amo_op_i, input logic [31:0] operand_a_i, input logic [31:0] operand_b_i, diff --git a/hw/snitch_cluster/src/snitch_cc.sv b/hw/snitch_cluster/src/snitch_cc.sv deleted file mode 100644 index 1754c3c471..0000000000 --- a/hw/snitch_cluster/src/snitch_cc.sv +++ /dev/null @@ -1,1010 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Author: Florian Zaruba - -`include "common_cells/assertions.svh" -`include "common_cells/registers.svh" -`include "snitch/typedef.svh" -`include "reqrsp_interface/typedef.svh" -`include "dca_interface/typedef.svh" - -/// Snitch Core Complex (CC) -/// Contains the Snitch Integer Core + FPU + Private Accelerators -module snitch_cc #( - /// Address width of the buses - parameter int unsigned AddrWidth = 0, - /// Data width of the buses. - parameter int unsigned DataWidth = 0, - /// User width of the TCDM bus. - parameter int unsigned TcdmUserWidth = 0, - /// Data width of the AXI DMA buses. - parameter int unsigned DMADataWidth = 0, - /// Id width of the AXI DMA bus. - parameter int unsigned DMAIdWidth = 0, - /// User width of the AXI DMA bus. - parameter int unsigned DMAUserWidth = 0, - parameter int unsigned DMANumAxInFlight = 0, - parameter int unsigned DMAReqFifoDepth = 0, - parameter int unsigned DMANumChannels = 0, - /// Data port request type. - parameter type dreq_t = logic, - /// Data port response type. - parameter type drsp_t = logic, - /// TCDM Address Width - parameter int unsigned TCDMAddrWidth = 0, - /// Data port request type. - parameter type tcdm_req_t = logic, - /// Data port response type. - parameter type tcdm_rsp_t = logic, - parameter type axi_ar_chan_t = logic, - parameter type axi_aw_chan_t = logic, - parameter type axi_req_t = logic, - parameter type axi_rsp_t = logic, - parameter type hive_req_t = logic, - parameter type hive_rsp_t = logic, - parameter type dma_events_t = logic, - // XIF parameters - parameter bit EnableXif = 1, - parameter int unsigned XifIdWidth = 4, - // XIF port types - parameter type x_issue_req_t = logic, - parameter type x_issue_resp_t = logic, - parameter type x_register_t = logic, - parameter type x_commit_t = logic, - parameter type x_result_t = logic, - parameter fpnew_pkg::fpu_implementation_t FPUImplementation = '0, - /// Boot address of core. - parameter logic [31:0] BootAddr = 32'h0000_1000, - /// Core ISA configuration. - parameter snitch_pkg::isa_cfg_t IsaCfg = '0, - /// Enable private IPU. - parameter bit PrivateIpu = 0, - /// Has virtual memory support. - parameter bit VMSupport = 1, - parameter int unsigned NumIntOutstandingLoads = 0, - parameter int unsigned NumIntOutstandingMem = 0, - parameter int unsigned NumFPOutstandingLoads = 0, - parameter int unsigned NumFPOutstandingMem = 0, - parameter int unsigned NumDTLBEntries = 0, - parameter int unsigned NumITLBEntries = 0, - parameter int unsigned NumSequencerInstr = 0, - parameter int unsigned NumSequencerLoops = 0, - parameter int unsigned NumSsrs = 0, - parameter int unsigned SsrMuxRespDepth = 0, - parameter snitch_ssr_pkg::ssr_cfg_t [cc_pkg::iomsb(NumSsrs):0] SsrCfgs = '0, - parameter logic [cc_pkg::iomsb(NumSsrs):0][4:0] SsrRegs = '0, - /// Add isochronous clock-domain crossings e.g., make it possible to operate - /// the core in a slower clock domain. - parameter bit IsoCrossing = 0, - /// Timing Parameters - /// Insert Pipeline registers into off-loading path (request) - parameter bit RegisterOffloadReq = 0, - /// Insert Pipeline registers into off-loading path (response) - parameter bit RegisterOffloadRsp = 0, - /// Insert Pipeline registers into data memory path (request) - parameter bit RegisterCoreReq = 0, - /// Insert Pipeline registers into data memory path (response) - parameter bit RegisterCoreRsp = 0, - /// Insert Pipeline register into the FPU data path (request) - parameter bit RegisterFPUReq = 0, - /// Insert Pipeline registers after sequencer - parameter bit RegisterSequencer = 0, - /// Insert Pipeline registers immediately before FPU datapath - parameter bit RegisterFPUIn = 0, - /// Insert Pipeline registers immediately after FPU datapath - parameter bit RegisterFPUOut = 0, - /// Cut DCA request to FPU - parameter bit RegisterDcaReq = 0, - /// Cut DCA response from FPU - parameter bit RegisterDcaRsp = 0, - parameter snitch_pma_pkg::snitch_pma_t SnitchPMACfg = '{default: 0}, - /// Consistency Address Queue (CAQ) parameters. - parameter int unsigned CaqDepth = 0, - parameter int unsigned CaqTagWidth = 0, - /// Enable debug support. - parameter bit DebugSupport = 1, - /// Optional fixed TCDM alias. - parameter bit TCDMAliasEnable = 1'b0, - parameter logic [AddrWidth-1:0] TCDMAliasStart = '0, - /// Width of the collective operation field - parameter int unsigned CollectiveWidth = 1, - /// Enable direct compute access (DCA). - parameter bit EnableDca = 0, - /// Derived parameter *Do not override* - localparam int unsigned TCDMPorts = (NumSsrs > 1 ? NumSsrs : 1), - localparam type addr_t = logic [AddrWidth-1:0], - localparam type data_t = logic [DataWidth-1:0], - localparam type dca_req_t = `DCA_REQ_STRUCT(DataWidth), - localparam type dca_rsp_t = `DCA_RSP_STRUCT(DataWidth) -) ( - input logic clk_i, - input logic clk_d2_i, - input logic rst_ni, - input logic rst_int_ss_ni, - input logic rst_fp_ss_ni, - input snitch_cluster_pkg::hart_id_t hart_id_i, - input snitch_pkg::interrupts_t irq_i, - output hive_req_t hive_req_o, - input hive_rsp_t hive_rsp_i, - // Core data ports - output dreq_t data_req_o, - input drsp_t data_rsp_i, - // TCDM Streamer Ports - output tcdm_req_t [TCDMPorts-1:0] tcdm_req_o, - input tcdm_rsp_t [TCDMPorts-1:0] tcdm_rsp_i, - // X Interface - Issue ports - output x_issue_req_t x_issue_req_o, - input x_issue_resp_t x_issue_resp_i, - output logic x_issue_valid_o, - input logic x_issue_ready_i, - output x_register_t x_register_o, - output logic x_register_valid_o, - input logic x_register_ready_i, - output x_commit_t x_commit_o, - output logic x_commit_valid_o, - // X Interface - Result ports - input x_result_t x_result_i, - input logic x_result_valid_i, - output logic x_result_ready_o, - // DMA ports - output axi_req_t [DMANumChannels-1:0] axi_dma_req_o, - input axi_rsp_t [DMANumChannels-1:0] axi_dma_res_i, - output logic [DMANumChannels-1:0] axi_dma_busy_o, - output dma_events_t [DMANumChannels-1:0] axi_dma_events_o, - // Core event strobes - output snitch_pkg::core_events_t core_events_o, - input addr_t tcdm_addr_base_i, - // Cluster HW barrier - output logic barrier_o, - input logic barrier_i, - // Direct Compute Access (DCA) interface - input dca_req_t dca_req_i, - output dca_rsp_t dca_rsp_o -); - - localparam bit FpEn = snitch_pkg::calculate_fp_enable(IsaCfg); - localparam bit Xpulpv2 = snitch_pkg::calculate_xpulpv2(IsaCfg); - localparam int unsigned FLEN = snitch_pkg::calculate_flen(IsaCfg); - - typedef struct packed { - logic [4:0] id; - logic [11:0] word; - logic [31:0] data; - logic write; - } ssr_cfg_req_t; - - typedef struct packed { - logic [4:0] id; - logic [31:0] data; - } ssr_cfg_rsp_t; - - // Define dca_req_chan_t and dca_rsp_chan_t - `DCA_TYPEDEF_REQRSP_CHAN_ALL(dca, DataWidth) - - `SNITCH_ACC_TYPEDEF_ALL(DataWidth, AddrWidth) - `SNITCH_INSTR_TYPEDEF_ALL(AddrWidth) - `SNITCH_VM_TYPEDEF_ALL(AddrWidth) - - // Accelerator offload interface - acc_req_t snitch_acc_req; - acc_rsp_t snitch_acc_rsp; - acc_req_t snitch_acc_req_q; - acc_rsp_t snitch_acc_rsp_q; - acc_req_t [snitch_pkg::NUM_ACC-1:0] snitch_acc_req_demuxed; - acc_rsp_t [snitch_pkg::NUM_ACC-1:0] snitch_acc_rsp_demuxed; - - logic [31:0] i2f_rdata; - logic i2f_rvalid; - logic i2f_rready; - logic [31:0] f2i_wdata; - logic f2i_wvalid; - logic f2i_wready; - logic en_copift; - - fpnew_pkg::roundmode_e fpu_rnd_mode; - fpnew_pkg::fmt_mode_t fpu_fmt_mode; - fpnew_pkg::status_t fpu_status; - - snitch_pkg::core_events_t snitch_events; - snitch_pkg::core_events_t fpss_events; - - // Snitch Integer Core - dreq_t snitch_dreq_d, snitch_dreq_q, merged_dreq; - drsp_t snitch_drsp_d, snitch_drsp_q, merged_drsp; - - // Consistency Address Queue (CAQ) interface - logic caq_pvalid, caq_pvalid_q; - - //////////// - // Snitch // - //////////// - - snitch #( - .BootAddr (BootAddr), - .IsaCfg (IsaCfg), - .AddrWidth (AddrWidth), - .DataWidth (DataWidth), - .VMSupport (VMSupport), - .DebugSupport (DebugSupport), - .EnableXif (EnableXif), - .XifIdWidth (XifIdWidth), - .NumIntOutstandingLoads (NumIntOutstandingLoads), - .NumIntOutstandingMem (NumIntOutstandingMem), - .NumDTLBEntries (NumDTLBEntries), - .NumITLBEntries (NumITLBEntries), - .SnitchPMACfg (SnitchPMACfg), - .CaqDepth (CaqDepth), - .CaqTagWidth (CaqTagWidth) - ) i_snitch ( - .clk_i ( clk_d2_i ), // if necessary operate on half the frequency - .rst_i ( ~rst_ni ), - .hart_id_i, - .irq_i, - .flush_i_valid_o (hive_req_o.flush_i_valid), - .flush_i_ready_i (hive_rsp_i.flush_i_ready), - .inst_req_o ( hive_req_o.instr_req ), - .inst_rsp_i ( hive_rsp_i.instr_rsp ), - .acc_req_o ( snitch_acc_req ), - .acc_rsp_i ( snitch_acc_rsp ), - .x_issue_req_o ( x_issue_req_o ), - .x_issue_resp_i ( x_issue_resp_i ), - .x_issue_valid_o ( x_issue_valid_o ), - .x_issue_ready_i ( x_issue_ready_i ), - .x_register_o ( x_register_o ), - .x_register_valid_o ( x_register_valid_o ), - .x_register_ready_i ( x_register_ready_i ), - .x_commit_o ( x_commit_o ), - .x_commit_valid_o ( x_commit_valid_o ), - .x_result_i ( x_result_i ), - .x_result_valid_i ( x_result_valid_i ), - .x_result_ready_o ( x_result_ready_o ), - .i2f_rdata_o ( i2f_rdata ), - .i2f_rvalid_o ( i2f_rvalid ), - .i2f_rready_i ( i2f_rready ), - .f2i_wdata_i ( f2i_wdata ), - .f2i_wvalid_i ( f2i_wvalid ), - .f2i_wready_o ( f2i_wready ), - .caq_pvalid_i ( caq_pvalid_q ), - .data_req_o ( snitch_dreq_d ), - .data_rsp_i ( snitch_drsp_d ), - .ptw_req_o ( hive_req_o.ptw_req ), - .ptw_rsp_i ( hive_rsp_i.ptw_rsp ), - .fpu_rnd_mode_o ( fpu_rnd_mode ), - .fpu_fmt_mode_o ( fpu_fmt_mode ), - .fpu_status_i ( fpu_status ), - .core_events_o ( snitch_events), - .barrier_o ( barrier_o ), - .barrier_i ( barrier_i ), - .en_copift_o ( en_copift ) - ); - - reqrsp_iso #( - .AddrWidth (AddrWidth), - .DataWidth (DataWidth), - .UserWidth (64), - .req_t (dreq_t), - .rsp_t (drsp_t), - .BypassReq (!RegisterCoreReq), - .BypassRsp (!IsoCrossing && !RegisterCoreRsp) - ) i_data_cut ( - .src_clk_i (clk_d2_i), - .src_rst_ni (rst_ni), - .src_req_i (snitch_dreq_d), - .src_rsp_o (snitch_drsp_d), - .dst_clk_i (clk_i), - .dst_rst_ni (rst_ni), - .dst_req_o (snitch_dreq_q), - .dst_rsp_i (snitch_drsp_q) - ); - - generic_reqrsp_cut #( - .req_chan_t(acc_req_chan_t), - .rsp_chan_t(acc_rsp_chan_t), - .BypassReq (!RegisterOffloadReq), - .BypassRsp (!RegisterOffloadRsp) - ) i_acc_cut ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .slv_req_i(snitch_acc_req), - .slv_rsp_o(snitch_acc_rsp), - .mst_req_o(snitch_acc_req_q), - .mst_rsp_i(snitch_acc_rsp_q) - ); - - // Cut CAQ response for proper handshake with divided clock. - cc_isochronous_spill_register #( - .data_t (logic), - .Bypass (!IsoCrossing) - ) i_spill_register_caq_pvalid ( - .src_clk_i ( clk_i ), - .src_rst_ni ( rst_ni ), - .src_valid_i ( caq_pvalid ), - .src_ready_o ( ), - .src_data_i ( '0 ), - .dst_clk_i ( clk_d2_i ), - .dst_rst_ni ( rst_ni ), - .dst_valid_o ( caq_pvalid_q ), - .dst_ready_i ( 1'b1 ), - .dst_data_o ( ) - ); - - generic_reqrsp_demux #( - .NrPorts (snitch_pkg::NUM_ACC), - .req_chan_t(acc_req_chan_t), - .rsp_chan_t(acc_rsp_chan_t) - ) i_acc_demux ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .slv_req_i(snitch_acc_req_q), - .slv_rsp_o(snitch_acc_rsp_q), - .mst_req_o(snitch_acc_req_demuxed), - .mst_rsp_i(snitch_acc_rsp_demuxed), - .idx_i (snitch_acc_req_q.q.addr[$clog2(snitch_pkg::NUM_ACC)-1:0]) - ); - - ///////// - // DMA // - ///////// - - if (IsaCfg.Xdma) begin : gen_dma - idma_inst64_top #( - .AxiAddrWidth (AddrWidth), - .AxiDataWidth (DMADataWidth), - .AxiIdWidth (DMAIdWidth), - .AxiUserWidth (DMAUserWidth), - .NumAxInFlight (DMANumAxInFlight), - .DMAReqFifoDepth (DMAReqFifoDepth), - .NumChannels (DMANumChannels), - .DMATracing (1), - .axi_ar_chan_t (axi_ar_chan_t), - .axi_aw_chan_t (axi_aw_chan_t), - .axi_req_t (axi_req_t), - .axi_res_t (axi_rsp_t), - .acc_req_t (acc_req_chan_t), - .acc_res_t (acc_rsp_chan_t), - .dma_events_t (dma_events_t) - ) i_idma_inst64_top ( - .clk_i, - .rst_ni, - .axi_req_o ( axi_dma_req_o ), - .axi_res_i ( axi_dma_res_i ), - .busy_o ( axi_dma_busy_o ), - .acc_req_i ( snitch_acc_req_demuxed[snitch_pkg::DMA_SS].q ), - .acc_req_valid_i ( snitch_acc_req_demuxed[snitch_pkg::DMA_SS].q_valid ), - .acc_req_ready_o ( snitch_acc_rsp_demuxed[snitch_pkg::DMA_SS].q_ready ), - .acc_res_o ( snitch_acc_rsp_demuxed[snitch_pkg::DMA_SS].p ), - .acc_res_valid_o ( snitch_acc_rsp_demuxed[snitch_pkg::DMA_SS].p_valid ), - .acc_res_ready_i ( snitch_acc_req_demuxed[snitch_pkg::DMA_SS].p_ready ), - .hart_id_i ( hart_id_i ), - .events_o ( axi_dma_events_o ) - ); - end else begin : gen_no_dma - // tie-off unused signals - assign axi_dma_req_o = '0; - assign axi_dma_busy_o = '0; - assign snitch_acc_rsp_demuxed[snitch_pkg::DMA_SS] = '0; - assign axi_dma_events_o = '0; - end - - ///////// - // IPU // - ///////// - - if (PrivateIpu) begin : gen_ipu - snitch_ipu #( - .IdWidth (5), - .Xpulpv2 (Xpulpv2), - .acc_rsp_t(acc_rsp_t), - .acc_req_t(acc_req_t) - ) i_snitch_ipu ( - .clk_i, - .rst_ni, - .acc_req_i(snitch_acc_req_demuxed[snitch_pkg::IPU]), - .acc_rsp_o(snitch_acc_rsp_demuxed[snitch_pkg::IPU]) - ); - assign hive_req_o.acc_req = '0; - end else begin - assign hive_req_o.acc_req = snitch_acc_req_demuxed[snitch_pkg::IPU]; - assign snitch_acc_rsp_demuxed[snitch_pkg::IPU] = hive_rsp_i.acc_rsp; - end - - ////////////////// - // FP subsystem // - ////////////////// - - // pragma translate_off - snitch_pkg::fpu_trace_port_t fpu_trace; - snitch_pkg::fpu_sequencer_trace_port_t fpu_sequencer_trace; - snitch_pkg::dca_trace_port_t dca_trace; - // pragma translate_on - - logic [2:0][4:0] ssr_raddr; - data_t [2:0] ssr_rdata; - logic [2:0] ssr_rvalid; - logic [2:0] ssr_rready; - logic [2:0] ssr_rdone; - logic [0:0][4:0] ssr_waddr; - data_t [0:0] ssr_wdata; - logic [0:0] ssr_wvalid; - logic [0:0] ssr_wready; - logic [0:0] ssr_wdone; - logic ssr_streamctl_done; - logic ssr_streamctl_valid; - logic ssr_streamctl_ready; - - if (FpEn) begin : gen_fpu - - dreq_t fpu_dreq; - drsp_t fpu_drsp; - - dca_req_t dca_req; - dca_rsp_t dca_rsp; - - generic_reqrsp_cut #( - .req_chan_t(dca_req_chan_t), - .rsp_chan_t(dca_rsp_chan_t), - .BypassReq(!EnableDca || !RegisterDcaReq), - .BypassRsp(!EnableDca || !RegisterDcaRsp) - ) i_dca_cut ( - .clk_i(clk_i), - .rst_ni(rst_ni), - .slv_req_i(dca_req_i), - .slv_rsp_o(dca_rsp_o), - .mst_req_o(dca_req), - .mst_rsp_i(dca_rsp) - ); - - snitch_fp_ss #( - .AddrWidth (AddrWidth), - .DataWidth (DataWidth), - .NumFPOutstandingLoads (NumFPOutstandingLoads), - .NumFPOutstandingMem (NumFPOutstandingMem), - .NumFPUSequencerInstr (NumSequencerInstr), - .NumFPUSequencerLoops (NumSequencerLoops), - .FpuImplementation (FPUImplementation), - .IsaCfg (IsaCfg), - .NumSsrs (NumSsrs), - .SsrRegs (SsrRegs), - .dreq_t (dreq_t), - .drsp_t (drsp_t), - .RegisterSequencer (RegisterSequencer), - .RegisterFpuReq (RegisterFPUIn), - .RegisterFpuRsp (RegisterFPUOut), - .EnableDca (EnableDca) - ) i_snitch_fp_ss ( - .clk_i, - .rst_i ( ~rst_ni | (~rst_fp_ss_ni) ), - // pragma translate_off - .trace_port_o ( fpu_trace ), - .sequencer_tracer_port_o ( fpu_sequencer_trace ), - .dca_trace_port_o ( dca_trace ), - // pragma translate_on - .hart_id_i ( hart_id_i ), - .acc_req_i ( snitch_acc_req_demuxed[snitch_pkg::FP_SS] ), - .acc_rsp_o ( snitch_acc_rsp_demuxed[snitch_pkg::FP_SS] ), - .i2f_rdata_i ( i2f_rdata ), - .i2f_rvalid_i ( i2f_rvalid ), - .i2f_rready_o ( i2f_rready ), - .f2i_wdata_o ( f2i_wdata ), - .f2i_wvalid_o ( f2i_wvalid ), - .f2i_wready_i ( f2i_wready ), - .caq_pvalid_o ( caq_pvalid ), - .data_req_o ( fpu_dreq ), - .data_rsp_i ( fpu_drsp ), - .fpu_rnd_mode_i ( fpu_rnd_mode ), - .fpu_fmt_mode_i ( fpu_fmt_mode ), - .fpu_status_o ( fpu_status ), - .ssr_raddr_o ( ssr_raddr ), - .ssr_rdata_i ( ssr_rdata ), - .ssr_rvalid_o ( ssr_rvalid ), - .ssr_rready_i ( ssr_rready ), - .ssr_rdone_o ( ssr_rdone ), - .ssr_waddr_o ( ssr_waddr ), - .ssr_wdata_o ( ssr_wdata ), - .ssr_wvalid_o ( ssr_wvalid ), - .ssr_wready_i ( ssr_wready ), - .ssr_wdone_o ( ssr_wdone ), - .streamctl_done_i ( ssr_streamctl_done ), - .streamctl_valid_i ( ssr_streamctl_valid ), - .streamctl_ready_o ( ssr_streamctl_ready ), - .core_events_o ( fpss_events ), - .en_copift_i ( en_copift ), - .dca_req_i ( dca_req ), - .dca_rsp_o ( dca_rsp ) - ); - - reqrsp_mux #( - .NrPorts (2), - .AddrWidth (AddrWidth), - .DataWidth (DataWidth), - .UserWidth (64), - .req_t (dreq_t), - .rsp_t (drsp_t), - // TODO(zarubaf): Wire-up to top-level. - .RespDepth (8), - .RegisterReq ({RegisterFPUReq, 1'b0}) - ) i_reqrsp_mux ( - .clk_i, - .rst_ni, - .slv_req_i ({fpu_dreq, snitch_dreq_q}), - .slv_rsp_o ({fpu_drsp, snitch_drsp_q}), - .mst_req_o (merged_dreq), - .mst_rsp_i (merged_drsp), - .idx_o (/*not connected*/) - ); - - end else begin : gen_no_fpu - assign fpu_status = '0; - - assign ssr_raddr = '0; - assign ssr_rvalid = '0; - assign ssr_rdone = '0; - assign ssr_waddr = '0; - assign ssr_wdata = '0; - assign ssr_wvalid = '0; - assign ssr_wdone = '0; - - assign snitch_acc_rsp_demuxed[snitch_pkg::FP_SS] = '0; - - assign caq_pvalid = '0; - - assign merged_dreq = snitch_dreq_q; - assign snitch_drsp_q = merged_drsp; - - assign fpss_events = '0; - - assign dca_rsp_o = '0; - end - - // Decide whether to go to SoC or TCDM - - localparam int unsigned SelectWidth = cc_pkg::idx_width(2); - typedef logic [SelectWidth-1:0] select_t; - typedef enum select_t {SelectTcdm = 1, SelectSoc = 0} select_e; - - dreq_t data_tcdm_req; - drsp_t data_tcdm_rsp; - - select_t slave_select, slave_select_coll_op; - - reqrsp_demux #( - .NrPorts (2), - .req_t (dreq_t), - .rsp_t (drsp_t), - // TODO(zarubaf): Make a parameter. - .RespDepth (4) - ) i_reqrsp_demux ( - .clk_i, - .rst_ni, - .slv_select_i (slave_select_coll_op), - .slv_req_i (merged_dreq), - .slv_rsp_o (merged_drsp), - .mst_req_o ({data_tcdm_req, data_req_o}), - .mst_rsp_i ({data_tcdm_rsp, data_rsp_i}) - ); - - typedef struct packed { - int unsigned idx; - logic [AddrWidth-1:0] base; - logic [AddrWidth-1:0] mask; - } reqrsp_rule_t; - - reqrsp_rule_t [TCDMAliasEnable:0] addr_map; - assign addr_map[0] = '{ - idx: SelectTcdm, - base: tcdm_addr_base_i, - mask: ({AddrWidth{1'b1}} << TCDMAddrWidth) - }; - if (TCDMAliasEnable) begin : gen_tcdm_alias_rule - assign addr_map[1] = '{ - idx: SelectTcdm, - base: TCDMAliasStart, - mask: ({AddrWidth{1'b1}} << TCDMAddrWidth) - }; - end - - cc_addr_decode_napot #( - .NoIndices (2), - .NoRules (1 + TCDMAliasEnable), - .addr_t (logic [AddrWidth-1:0]), - .rule_t (reqrsp_rule_t) - ) i_addr_decode_napot ( - .addr_i (merged_dreq.q.addr), - .addr_map_i (addr_map), - .idx_o (slave_select), - .dec_valid_o (), - .dec_error_o (), - .en_default_idx_i (1'b1), - .default_idx_i (SelectSoc) - ); - - // Collective communication operations are performed within the interconnect at the SoC - // level. However, requests destined to the TCDM never arrive at the SoC interconnect, - // as they are routed internally within the cluster. In order for collectives destined to - // the TCDM to work, we need to handle them differently, and always forward them to the - // SoC interconnect, which will reroute them back to the TCDM from outside the cluster. - // The collective mask, in the user field, is used to detect collective operations. - addr_t collective_mask; - assign collective_mask = addr_t'(merged_dreq.q.user[CollectiveWidth+:AddrWidth]); - assign slave_select_coll_op = (collective_mask != 0) ? SelectSoc : slave_select; - - tcdm_req_t core_tcdm_req; - tcdm_rsp_t core_tcdm_rsp; - - reqrsp_to_tcdm #( - .AddrWidth (AddrWidth), - .DataWidth (DataWidth), - .UserWidth (64), - // TODO(zarubaf): Make a parameter. - .BufDepth (4), - .reqrsp_req_t (dreq_t), - .reqrsp_rsp_t (drsp_t), - .tcdm_req_t (tcdm_req_t), - .tcdm_rsp_t (tcdm_rsp_t) - ) i_reqrsp_to_tcdm ( - .clk_i, - .rst_ni, - .reqrsp_req_i (data_tcdm_req), - .reqrsp_rsp_o (data_tcdm_rsp), - .tcdm_req_o (core_tcdm_req), - .tcdm_rsp_i (core_tcdm_rsp) - ); - - ////////// - // SSRs // - ////////// - - acc_req_chan_t ssr_req; - acc_rsp_chan_t ssr_resp; - logic ssr_qvalid, ssr_qready; - logic ssr_pvalid, ssr_pready; - - assign ssr_qvalid = snitch_acc_req_demuxed[snitch_pkg::SSR_CFG].q_valid; - assign ssr_req = snitch_acc_req_demuxed[snitch_pkg::SSR_CFG].q; - assign ssr_pready = snitch_acc_req_demuxed[snitch_pkg::SSR_CFG].p_ready; - assign snitch_acc_rsp_demuxed[snitch_pkg::SSR_CFG].q_ready = ssr_qready; - assign snitch_acc_rsp_demuxed[snitch_pkg::SSR_CFG].p = ssr_resp; - assign snitch_acc_rsp_demuxed[snitch_pkg::SSR_CFG].p_valid = ssr_pvalid; - - if (IsaCfg.Xssr) begin : gen_ssrs - tcdm_req_t [NumSsrs-1:0] ssr_req; - tcdm_rsp_t [NumSsrs-1:0] ssr_rsp; - tcdm_req_t tcdm_req; - tcdm_rsp_t tcdm_rsp; - - ssr_cfg_req_t ssr_cfg_req, cfg_req; - ssr_cfg_rsp_t ssr_cfg_rsp, cfg_rsp; - - logic cfg_req_valid, cfg_req_valid_q; - logic cfg_req_wready, cfg_req_ready, cfg_req_hs; - logic [31:0] cfg_rsp_data; - assign cfg_req_ready = ~cfg_req.write | cfg_req_wready; - assign cfg_req_hs = cfg_req_valid & cfg_req_ready; - `FF(cfg_req_valid_q, cfg_req_hs, 0) - `FFL(cfg_rsp.id, ssr_cfg_req.id, cfg_req_hs, 0) - `FFL(cfg_rsp.data, cfg_rsp_data, cfg_req_hs, 0) - - always_comb begin - import riscv_instr::*; - automatic logic [11:0] addr; - automatic logic [4:0] addr_dm; - automatic logic [6:0] addr_reg; - - ssr_cfg_req.id = snitch_acc_req_demuxed[snitch_pkg::SSR_CFG].q.id; - ssr_cfg_req.data = snitch_acc_req_demuxed[snitch_pkg::SSR_CFG].q.data_arga[31:0]; - ssr_cfg_req.word = '0; - ssr_cfg_req.write = '0; - - addr = '0; - unique casez (snitch_acc_req_demuxed[snitch_pkg::SSR_CFG].q.data_op) - SCFGRI, - SCFGWI: begin - addr = snitch_acc_req_demuxed[snitch_pkg::SSR_CFG].q.data_op[31:20]; - end - SCFGR, - SCFGW: begin - addr = snitch_acc_req_demuxed[snitch_pkg::SSR_CFG].q.data_argb[31:0]; - end - default: ; - endcase - - addr_reg = addr[11:5]; - addr_dm = addr[4:0]; - ssr_cfg_req.word = {addr_dm, addr_reg}; - - unique casez (snitch_acc_req_demuxed[snitch_pkg::SSR_CFG].q.data_op) - SCFGRI, - SCFGR: - ssr_cfg_req.write = '0; - SCFGWI, - SCFGW: begin - ssr_cfg_req.write = '1; - ssr_cfg_req.id = '0; // prevent write-back of result - end - default: ; - endcase - end - - assign ssr_resp.id = ssr_cfg_rsp.id; - assign ssr_resp.error = 1'b0; - assign ssr_resp.data = ssr_cfg_rsp.data; - - cc_stream_to_mem #( - .mem_req_t (ssr_cfg_req_t), - .mem_resp_t (ssr_cfg_rsp_t), - .BufDepth (1) - ) i_stream_to_mem ( - .clk_i, - .rst_ni, - .clr_i (1'b0), - .req_i (ssr_cfg_req), - .req_valid_i (ssr_qvalid), - .req_ready_o (ssr_qready), - .resp_o (ssr_cfg_rsp), - .resp_valid_o (ssr_pvalid), - .resp_ready_i (ssr_pready), - .mem_req_o (cfg_req), - .mem_req_valid_o (cfg_req_valid), - .mem_req_ready_i (cfg_req_ready), - .mem_resp_i (cfg_rsp), - .mem_resp_valid_i (cfg_req_valid_q) - ); - - // If Xssr is enabled, we should at least have one SSR - `ASSERT_INIT(CheckSsrWithXssr, NumSsrs >= 1); - - snitch_ssr_streamer #( - .NumSsrs (NumSsrs), - .RPorts (3), - .WPorts (1), - .SsrCfgs (SsrCfgs), - .SsrRegs (SsrRegs), - .AddrWidth (TCDMAddrWidth), - .DataWidth (DataWidth), - .UserWidth (TcdmUserWidth), - .tcdm_req_t (tcdm_req_t), - .tcdm_rsp_t (tcdm_rsp_t) - ) i_snitch_ssr_streamer ( - .clk_i, - .rst_ni ( rst_ni ), - .cfg_word_i ( cfg_req.word ), - .cfg_write_i ( cfg_req.write & cfg_req_valid ), - .cfg_rdata_o ( cfg_rsp_data ), - .cfg_wdata_i ( cfg_req.data ), - .cfg_wready_o ( cfg_req_wready ), - - .ssr_raddr_i ( ssr_raddr ), - .ssr_rdata_o ( ssr_rdata ), - .ssr_rvalid_i ( ssr_rvalid ), - .ssr_rready_o ( ssr_rready ), - .ssr_rdone_i ( ssr_rdone ), - .ssr_waddr_i ( ssr_waddr ), - .ssr_wdata_i ( ssr_wdata ), - .ssr_wvalid_i ( ssr_wvalid ), - .ssr_wready_o ( ssr_wready ), - .ssr_wdone_i ( ssr_wdone ), - .mem_req_o ( ssr_req ), - .mem_rsp_i ( ssr_rsp ), - .streamctl_done_o ( ssr_streamctl_done ), - .streamctl_valid_o ( ssr_streamctl_valid ), - .streamctl_ready_i ( ssr_streamctl_ready ) - ); - - if (NumSsrs > 1) begin : gen_multi_ssr - assign ssr_rsp = {tcdm_rsp_i[NumSsrs-1:1], tcdm_rsp}; - assign {tcdm_req_o[NumSsrs-1:1], tcdm_req} = ssr_req; - end else begin : gen_one_ssr - assign ssr_rsp = tcdm_rsp; - assign tcdm_req = ssr_req; - end - - tcdm_mux #( - .NrPorts (2), - .AddrWidth (TCDMAddrWidth), - .DataWidth (DataWidth), - .UserWidth (TcdmUserWidth), - .RespDepth (SsrMuxRespDepth), - .tcdm_req_t (tcdm_req_t), - .tcdm_rsp_t (tcdm_rsp_t) - ) i_tcdm_mux ( - .clk_i, - .rst_ni, - .slv_req_i({core_tcdm_req, tcdm_req}), - .slv_rsp_o({core_tcdm_rsp, tcdm_rsp}), - .mst_req_o(tcdm_req_o[0]), - .mst_rsp_i(tcdm_rsp_i[0]) - ); - - end else begin : gen_no_ssrs - // Connect single TCDM port - assign tcdm_req_o[0] = core_tcdm_req; - assign core_tcdm_rsp = tcdm_rsp_i[0]; - // Tie off SSR insruction stream - assign ssr_qready = '0; - assign ssr_resp = '0; - assign ssr_pvalid = '0; - // Tie off SSR data stream - assign ssr_rdata = '0; - assign ssr_rready = '0; - assign ssr_wready = '0; - // Tie off SSR stream control - assign ssr_streamctl_done = '0; - assign ssr_streamctl_valid = '0; - end - - ///////////////// - // Core events // - ///////////////// - - always_comb begin - core_events_o = snitch_events; - core_events_o.issue_fpu = fpss_events.issue_fpu; - core_events_o.issue_fpu_seq = fpss_events.issue_fpu_seq; - core_events_o.issue_core_to_fpu = fpss_events.issue_core_to_fpu; - end - - //////////// - // Tracer // - //////////// - - // pragma translate_off -`ifdef DEBUG - int f; - string fn; - logic [63:0] cycle; - initial begin - // We need to schedule the assignment into a safe region, otherwise - // `hart_id_i` won't have a value assigned at the beginning of the first - // delta cycle. -`ifndef VERILATOR - #0; -`endif - $system("mkdir logs -p"); - $sformat(fn, "logs/trace_hart_%05x.dasm", hart_id_i); - f = $fopen(fn, "w"); - $display("[Tracer] Logging Hart %d to %s", hart_id_i, fn); - end - - // verilog_lint: waive-start always-ff-non-blocking - always_ff @(posedge clk_i or negedge rst_ni) begin - automatic string trace_entry; - automatic string extras_str; - automatic snitch_pkg::snitch_trace_port_t extras_snitch; - automatic snitch_pkg::fpu_trace_port_t extras_fpu; - automatic snitch_pkg::fpu_sequencer_trace_port_t extras_fpu_seq_out; - automatic snitch_pkg::dca_trace_port_t extras_dca; - - if (rst_ni) begin - extras_snitch = '{ - // State - source: snitch_pkg::SrcSnitch, - stall: i_snitch.stall, - exception: i_snitch.exception, - // Decoding - rs1: i_snitch.rs1, - rs2: i_snitch.rs2, - rd: i_snitch.rd, - is_load: i_snitch.is_load, - is_store: i_snitch.is_store, - is_branch: i_snitch.is_branch, - pc_d: i_snitch.pc_d, - // Operands - opa: i_snitch.opa, - opb: i_snitch.opb, - opa_select: i_snitch.opa_select, - opb_select: i_snitch.opb_select, - opc_select: i_snitch.opc_select, - write_rd: i_snitch.write_rd, - csr_addr: i_snitch.inst_rsp_i.data[31:20], - // Pipeline writeback - writeback: i_snitch.alu_writeback, - // Load/Store - gpr_rdata_1: i_snitch.gpr_rdata[1], - ls_size: i_snitch.ls_size, - ld_result_32: i_snitch.ld_result[31:0], - lsu_rd: i_snitch.lsu_rd, - retire_load: i_snitch.retire_load, - alu_result: i_snitch.alu_result, - // Atomics - ls_amo: i_snitch.ls_amo, - // Accelerator - retire_acc: i_snitch.retire_acc, - acc_pid: i_snitch.acc_rsp_i.p.id, - acc_pdata_32: i_snitch.acc_rsp_i.p.data[31:0], - // FPU offload - fpu_offload: - (i_snitch.acc_rsp_i.q_ready && i_snitch.acc_req_o.q_valid && - i_snitch.acc_req_o.q.addr == snitch_pkg::FP_SS), - is_seq_insn: (i_snitch.inst_rsp_i.data ==? riscv_instr::FREP_O) - }; - - if (FpEn) begin - extras_fpu = fpu_trace; - if (IsaCfg.Xfrep) begin - // Addenda to FPU extras iff popping sequencer - extras_fpu_seq_out = fpu_sequencer_trace; - end - end - - cycle++; - // Trace snitch iff: - // we are not stalled <==> we have issued and processed an instruction (including offloads) - // OR we are retiring (issuing a writeback from) a load or accelerator instruction - if ( - !i_snitch.stall || i_snitch.retire_load || i_snitch.retire_acc - ) begin - $sformat(trace_entry, "%t %1d %8d 0x%h DASM(%h) #; %s\n", - $time, cycle, i_snitch.priv_lvl_q, i_snitch.pc_q, i_snitch.inst_rsp_i.data, - snitch_pkg::print_snitch_trace(extras_snitch)); - $fwrite(f, trace_entry); -`ifdef DEBUG - $fflush(f); -`endif - end - if (FpEn) begin - // Trace FPU iff: - // an incoming handshake on the accelerator bus occurs <==> an instruction was issued - // OR an FPU result is ready to be written back to an FPR register or the bus - // OR an LSU result is ready to be written back to an FPR register or the bus - // OR an FPU result, LSU result or bus value is ready to be written back to an FPR register - if (extras_fpu.acc_q_hs || extras_fpu.fpu_out_hs - || extras_fpu.lsu_q_hs || extras_fpu.fpr_we) begin - $sformat(trace_entry, "%t %1d %8d 0x%h DASM(%h) #; %s\n", - $time, cycle, i_snitch.priv_lvl_q, 32'hz, extras_fpu.op_in, - snitch_pkg::print_fpu_trace(extras_fpu)); - $fwrite(f, trace_entry); -`ifdef DEBUG - $fflush(f); -`endif - end - // sequencer instructions - if (IsaCfg.Xfrep) begin - if (extras_fpu_seq_out.cbuf_push) begin - $sformat(trace_entry, "%t %1d %8d 0x%h DASM(%h) #; %s\n", - $time, cycle, i_snitch.priv_lvl_q, 32'hz, 64'hz, - snitch_pkg::print_fpu_sequencer_trace(extras_fpu_seq_out)); - $fwrite(f, trace_entry); -`ifdef DEBUG - $fflush(f); -`endif - end - end - end - if (EnableDca) begin - extras_dca = dca_trace; - // Trace DCA iff a request or response handshake occurs - if (extras_dca.req_hs || extras_dca.rsp_hs) begin - $sformat(trace_entry, "%t %1d %8d 0x%h DASM(%h) #; %s\n", - $time, cycle, i_snitch.priv_lvl_q, 32'hz, extras_dca.op, - snitch_pkg::print_dca_trace(extras_dca)); - $fwrite(f, trace_entry); -`ifdef DEBUG - $fflush(f); -`endif - end - end - end else begin - cycle = '0; - end - end - - final begin - $fclose(f); - end - // verilog_lint: waive-stop always-ff-non-blocking -`endif - // pragma translate_on - - //////////////// - // Assertions // - //////////////// - - `ASSERT_INIT(BootAddrAligned, BootAddr[1:0] == 2'b00) - - // DCA extension currently only supports 64-bit datawidth - `ASSERT_INIT(DcaCoreConfiguration, (!EnableDca) || IsaCfg.RVD) - `ASSERT_INIT(DcaDataWidth, (!EnableDca) || (DataWidth == 64)) - -endmodule diff --git a/hw/snitch_cluster/src/snitch_cluster.sv b/hw/snitch_cluster/src/snitch_cluster.sv index 38e1233ba8..9c73391108 100644 --- a/hw/snitch_cluster/src/snitch_cluster.sv +++ b/hw/snitch_cluster/src/snitch_cluster.sv @@ -23,7 +23,6 @@ /// Snitch many-core cluster with improved TCDM interconnect. /// Snitch Cluster Top-Level. module snitch_cluster - import snitch_pkg::*; import snitch_icache_pkg::*; import snitch_cluster_pkg::*; #( @@ -114,9 +113,13 @@ module snitch_cluster /// Per-core number of SSRs. parameter int unsigned NumSsrs [NrCores] = '{default: 0}, /// Per-core depth of TCDM Mux unifying SSR 0 and Snitch requests. - parameter int unsigned SsrMuxRespDepth [NrCores] = '{default: 0}, + parameter int unsigned SsrMuxRspDepth [NrCores] = '{default: 0}, /// Per-core internal parameters for each SSR. parameter snitch_ssr_pkg::ssr_cfg_t [cc_pkg::iomsb(NumSsrsMax):0] SsrCfgs [NrCores] = '{default: '0}, + /// Number of outstanding loads in Spatz + parameter int unsigned NumSpatzOutstandingLoads [NrCores] = '{default: 0}, + /// Per-core enable of double bandwidth for Spatz. + parameter bit SpatzDoubleBw [NrCores] = '{default: 0}, /// Per-core register indices for each SSR. parameter logic [cc_pkg::iomsb(NumSsrsMax):0][4:0] SsrRegs [NrCores] = '{default: 0}, /// Per-core amount of sequencer instructions for IPU and FPU if enabled. @@ -250,7 +253,7 @@ module snitch_cluster /// First hartid of the cluster. Cores of a cluster are monotonically /// increasing without a gap, i.e., a cluster with 8 cores and a /// `hart_base_id_i` of 5 get the hartids 5 - 12. - input snitch_cluster_pkg::hart_id_t hart_base_id_i, + input snitch_pkg::hart_id_t hart_base_id_i, /// Base address of cluster. TCDM and cluster peripheral location are derived from /// it. This signal is pseudo-static. input logic [PhysicalAddrWidth-1:0] cluster_base_addr_i, @@ -327,13 +330,13 @@ module snitch_cluster // [0:0] is_core localparam int unsigned TcdmUserWidth = CoreIDWidth + 1; - function automatic int unsigned get_tcdm_ports(int unsigned core); - return (NumSsrs[core] > 1 ? NumSsrs[core] : 1); - endfunction - function automatic int unsigned get_tcdm_port_offs(int unsigned core_idx); automatic int n = 0; - for (int i = 0; i < core_idx; i++) n += get_tcdm_ports(i); + for (int i = 0; i < core_idx; i++) begin + n += snitch_cc_pkg::get_tcdm_ports( + IsaCfg[i], NumSsrs[i], spatz_pkg::N_FU, SpatzDoubleBw[i] + ); + end return n; endfunction @@ -342,7 +345,6 @@ module snitch_cluster localparam logic [PhysicalAddrWidth-1:0] TCDMMask = ~(TCDMSizeNapotRounded - 1); // User widths - localparam int unsigned CoreUserWidth = 64; localparam int unsigned NarrowUserWidth = $bits(user_narrow_t); localparam int unsigned WideUserWidth = $bits(user_dma_t); @@ -459,7 +461,6 @@ module snitch_cluster typedef logic [PhysicalAddrWidth-1:0] addr_t; typedef logic [NarrowDataWidth-1:0] data_t; typedef logic [NarrowDataWidth/8-1:0] strb_t; - typedef logic [CoreUserWidth-1:0] user_t; typedef logic [WideDataWidth-1:0] data_dma_t; typedef logic [WideDataWidth/8-1:0] strb_dma_t; typedef logic [NarrowIdWidthIn-1:0] id_mst_t; @@ -485,15 +486,16 @@ module snitch_cluster `APB_TYPEDEF_ALL(apb, addr_t, data_t, strb_t) - // Reqrsp interface of the core has a 64b user field - `REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t) - // Reqrsp interface in the cluster additionally contains the cluster ID + // LSU interface of the core has a 64b user field + `LSU_TYPEDEF_ALL(lsu, NarrowDataWidth, PhysicalAddrWidth, snitch_pkg::UserWidth) + // LSU interface in the cluster additionally contains the cluster ID // (used for atomic operations) in the user field - `REQRSP_TYPEDEF_ALL(reqrsp_amo, addr_t, data_t, strb_t, user_narrow_t) + `LSU_TYPEDEF_ALL(lsu_amo, NarrowDataWidth, PhysicalAddrWidth, NarrowUserWidth) `MEM_TYPEDEF_ALL(mem, tcdm_mem_addr_t, data_t, strb_t, tcdm_user_t) `MEM_TYPEDEF_ALL(mem_dma, tcdm_mem_addr_t, data_dma_t, strb_dma_t, logic) + `TCDM_TYPEDEF_ALL(soc_tcdm, NarrowDataWidth, PhysicalAddrWidth, NarrowUserWidth) `TCDM_TYPEDEF_ALL(tcdm, NarrowDataWidth, TCDMAddrWidth, TcdmUserWidth) // Define dca_lane_req_t and dca_lane_rsp_t @@ -620,22 +622,24 @@ module snitch_cluster tcdm_dma_rsp_t [1:0] ext_dma_rsp; // AXI Ports into TCDM (from SoC). - tcdm_req_t axi_soc_req; - tcdm_rsp_t axi_soc_rsp; + soc_tcdm_req_t soc_tcdm_req; + soc_tcdm_rsp_t soc_tcdm_rsp; + tcdm_req_t soc_tcdm_req_resized; + tcdm_rsp_t soc_tcdm_rsp_resized; tcdm_req_t [NrTCDMPortsCores-1:0] tcdm_req; tcdm_rsp_t [NrTCDMPortsCores-1:0] tcdm_rsp; - core_events_t [NrCores-1:0] core_events; + snitch_pkg::core_events_t [NrCores-1:0] core_events; tcdm_events_t tcdm_events; dma_events_t [DMANumChannels-1:0] dma_events; icache_l0_events_t [NrCores-1:0] icache_events; // 4. Memory Subsystem (Core side). - reqrsp_req_t [NrCores-1:0] core_req; - reqrsp_rsp_t [NrCores-1:0] core_rsp; - reqrsp_req_t [NrHives-1:0] ptw_req; - reqrsp_rsp_t [NrHives-1:0] ptw_rsp; + lsu_req_t [NrCores-1:0] core_req; + lsu_rsp_t [NrCores-1:0] core_rsp; + lsu_req_t [NrHives-1:0] ptw_req; + lsu_rsp_t [NrHives-1:0] ptw_rsp; // 5. Peripheral Subsystem axi_lite_req_t axi_lite_req; @@ -816,7 +820,7 @@ module snitch_cluster for (genvar i = 0; i < 2; i++) begin : gen_dma_rw_mem_ports assign ext_dma_req[i].q.addr = tcdm_addr_t'(ext_dma_req_q_addr_nontrunc[i]); - assign ext_dma_req[i].q.amo = snitch_pkg::AMONone; + assign ext_dma_req[i].q.amo = lsu_pkg::AMONone; assign ext_dma_req[i].q.user = '0; end @@ -977,8 +981,8 @@ module snitch_cluster ) i_tcdm_interconnect ( .clk_i, .rst_ni, - .req_i ({axi_soc_req, tcdm_req}), - .rsp_o ({axi_soc_rsp, tcdm_rsp}), + .req_i ({soc_tcdm_req_resized, tcdm_req}), + .rsp_o ({soc_tcdm_rsp_resized, tcdm_rsp}), .mem_req_o (ic_req), .mem_rsp_i (ic_rsp) ); @@ -1026,12 +1030,14 @@ module snitch_cluster end for (genvar i = 0; i < NrCores; i++) begin : gen_core - localparam int unsigned TcdmPorts = get_tcdm_ports(i); + localparam int unsigned TcdmPorts = snitch_cc_pkg::get_tcdm_ports( + IsaCfg[i], NumSsrs[i], spatz_pkg::N_FU, SpatzDoubleBw[i] + ); localparam int unsigned TcdmPortsOffs = get_tcdm_port_offs(i); axi_mst_dma_req_t [DMANumChannels-1:0] axi_dma_req; axi_mst_dma_resp_t [DMANumChannels-1:0] axi_dma_res; - interrupts_t irq; + snitch_pkg::interrupts_t irq; dma_events_t [DMANumChannels-1:0] dma_core_events; tc_sync #(.Stages (2)) @@ -1053,6 +1059,7 @@ module snitch_cluster snitch_cc #( .AddrWidth (PhysicalAddrWidth), .DataWidth (NarrowDataWidth), + .TcdmAddrWidth (TCDMAddrWidth), .TcdmUserWidth (TcdmUserWidth), .DMADataWidth (WideDataWidth), .DMAIdWidth (WideIdWidthIn), @@ -1061,10 +1068,6 @@ module snitch_cluster .DMANumAxInFlight (DMANumAxInFlight), .DMAReqFifoDepth (DMAReqFifoDepth), .DMANumChannels (DMANumChannels), - .dreq_t (reqrsp_req_t), - .drsp_t (reqrsp_rsp_t), - .tcdm_req_t (tcdm_req_t), - .tcdm_rsp_t (tcdm_rsp_t), .axi_ar_chan_t (axi_mst_dma_ar_chan_t), .axi_aw_chan_t (axi_mst_dma_aw_chan_t), .axi_req_t (axi_mst_dma_req_t), @@ -1093,9 +1096,11 @@ module snitch_cluster .NumSequencerInstr (NumSequencerInstr[i]), .NumSequencerLoops (NumSequencerLoops[i]), .NumSsrs (NumSsrs[i]), - .SsrMuxRespDepth (SsrMuxRespDepth[i]), + .SsrMuxRspDepth (SsrMuxRspDepth[i]), .SsrCfgs (SsrCfgs[i][cc_pkg::iomsb(NumSsrs[i]):0]), .SsrRegs (SsrRegs[i][cc_pkg::iomsb(NumSsrs[i]):0]), + .NumSpatzOutstandingLoads (NumSpatzOutstandingLoads[i]), + .SpatzDoubleBw (SpatzDoubleBw[i]), .RegisterOffloadReq (RegisterOffloadReq), .RegisterOffloadRsp (RegisterOffloadRsp), .RegisterCoreReq (RegisterCoreReq), @@ -1106,7 +1111,6 @@ module snitch_cluster .RegisterFPUOut (RegisterFPUOut), .RegisterDcaReq (RegisterDcaReq), .RegisterDcaRsp (RegisterDcaRsp), - .TCDMAddrWidth (TCDMAddrWidth), .CaqDepth (CaqDepth), .CaqTagWidth (CaqTagWidth), .DebugSupport (DebugSupport), @@ -1124,8 +1128,8 @@ module snitch_cluster .hive_req_o (hive_req[i]), .hive_rsp_i (hive_rsp[i]), .irq_i (irq), - .data_req_o (core_req[i]), - .data_rsp_i (core_rsp[i]), + .soc_req_o (core_req[i]), + .soc_rsp_i (core_rsp[i]), .tcdm_req_o (tcdm_req_wo_user), .tcdm_rsp_i (tcdm_rsp[TcdmPortsOffs+:TcdmPorts]), .x_issue_req_o (x_issue_req_o[i]), @@ -1194,8 +1198,7 @@ module snitch_cluster .VMSupport (VMSupport), .SharedIpu (SharedIpu), .Xpulpv2 (Xpulpv2), - .dreq_t (reqrsp_req_t), - .drsp_t (reqrsp_rsp_t), + .UserWidth (snitch_pkg::UserWidth), .hive_req_t (hive_req_t), .hive_rsp_t (hive_rsp_t), .CoreCount (HiveSize), @@ -1228,17 +1231,16 @@ module snitch_cluster // -------- // PTW Demux // -------- - reqrsp_req_t ptw_to_axi_req; - reqrsp_rsp_t ptw_to_axi_rsp; + lsu_req_t ptw_to_axi_req; + lsu_rsp_t ptw_to_axi_rsp; + lsu_amo_req_t ptw_to_axi_amo_req; + lsu_amo_rsp_t ptw_to_axi_amo_rsp; reqrsp_mux #( .NrPorts (NrHives), - .AddrWidth (PhysicalAddrWidth), - .DataWidth (NarrowDataWidth), - .UserWidth (CoreUserWidth), - .req_t (reqrsp_req_t), - .rsp_t (reqrsp_rsp_t), - .RespDepth (2) + .req_chan_t (lsu_req_chan_t), + .rsp_chan_t (lsu_rsp_chan_t), + .RspDepth (2) ) i_reqrsp_mux_ptw ( .clk_i, .rst_ni, @@ -1246,20 +1248,34 @@ module snitch_cluster .slv_rsp_o (ptw_rsp), .mst_req_o (ptw_to_axi_req), .mst_rsp_i (ptw_to_axi_rsp), + .rsp_route_i ('0), .idx_o (/*not connected*/) ); - reqrsp_to_axi #( + lsu_width_converter #( + .InAddrWidth (PhysicalAddrWidth), + .InDataWidth (NarrowDataWidth), + .InUserWidth (snitch_pkg::UserWidth), + .OutAddrWidth (PhysicalAddrWidth), + .OutDataWidth (NarrowDataWidth), + .OutUserWidth (NarrowUserWidth) + ) i_lsu_width_converter_ptw_to_axi ( + .lsu_req_i (ptw_to_axi_req), + .lsu_rsp_o (ptw_to_axi_rsp), + .lsu_req_o (ptw_to_axi_amo_req), + .lsu_rsp_i (ptw_to_axi_amo_rsp) + ); + + lsu_to_axi #( + .AddrWidth (PhysicalAddrWidth), .DataWidth (NarrowDataWidth), - .reqrsp_req_t (reqrsp_req_t), - .reqrsp_rsp_t (reqrsp_rsp_t), - .axi_req_t (axi_mst_req_t), - .axi_rsp_t (axi_mst_resp_t) - ) i_reqrsp_to_axi_ptw ( + .IdWidth (NarrowIdWidthIn), + .UserWidth (NarrowUserWidth) + ) i_lsu_to_axi_ptw ( .clk_i, .rst_ni, - .reqrsp_req_i (ptw_to_axi_req), - .reqrsp_rsp_o (ptw_to_axi_rsp), + .lsu_req_i (ptw_to_axi_amo_req), + .lsu_rsp_o (ptw_to_axi_amo_rsp), .axi_req_o (narrow_axi_mst_req[PTW]), .axi_rsp_i (narrow_axi_mst_rsp[PTW]) ); @@ -1277,17 +1293,14 @@ module snitch_cluster .barrier_o(barrier_out) ); - reqrsp_req_t core_to_axi_req; - reqrsp_rsp_t core_to_axi_rsp; + lsu_req_t core_to_axi_req; + lsu_rsp_t core_to_axi_rsp; reqrsp_mux #( .NrPorts (NrCores), - .AddrWidth (PhysicalAddrWidth), - .DataWidth (NarrowDataWidth), - .UserWidth (CoreUserWidth), - .req_t (reqrsp_req_t), - .rsp_t (reqrsp_rsp_t), - .RespDepth (2) + .req_chan_t (lsu_req_chan_t), + .rsp_chan_t (lsu_rsp_chan_t), + .RspDepth (2) ) i_reqrsp_mux_core ( .clk_i, .rst_ni, @@ -1295,6 +1308,7 @@ module snitch_cluster .slv_rsp_o (core_rsp), .mst_req_o (core_to_axi_req), .mst_rsp_i (core_to_axi_rsp), + .rsp_route_i ('0), .idx_o (/*unused*/) ); @@ -1321,8 +1335,8 @@ module snitch_cluster }; end - reqrsp_amo_req_t core_to_axi_amo_req; - reqrsp_amo_rsp_t core_to_axi_amo_rsp; + lsu_amo_req_t core_to_axi_amo_req; + lsu_amo_rsp_t core_to_axi_amo_rsp; always_comb begin core_to_axi_amo_req.q.addr = core_to_axi_req.q.addr; @@ -1337,17 +1351,16 @@ module snitch_cluster core_to_axi_rsp = core_to_axi_amo_rsp; end - reqrsp_to_axi #( + lsu_to_axi #( + .AddrWidth (PhysicalAddrWidth), .DataWidth (NarrowDataWidth), - .reqrsp_req_t (reqrsp_amo_req_t), - .reqrsp_rsp_t (reqrsp_amo_rsp_t), - .axi_req_t (axi_mst_req_t), - .axi_rsp_t (axi_mst_resp_t) - ) i_reqrsp_to_axi_core ( + .IdWidth (NarrowIdWidthIn), + .UserWidth (NarrowUserWidth) + ) i_lsu_to_axi_core ( .clk_i, .rst_ni, - .reqrsp_req_i (core_to_axi_amo_req), - .reqrsp_rsp_o (core_to_axi_amo_rsp), + .lsu_req_i (core_to_axi_amo_req), + .lsu_rsp_o (core_to_axi_amo_rsp), .axi_req_o (narrow_axi_mst_req[CoreReq]), .axi_rsp_i (narrow_axi_mst_rsp[CoreReq]) ); @@ -1471,22 +1484,32 @@ module snitch_cluster // 1. TCDM // Add an adapter that allows access from AXI to the TCDM. axi_to_tcdm #( - .axi_req_t (axi_slv_req_t), - .axi_rsp_t (axi_slv_resp_t), - .tcdm_req_t (tcdm_req_t), - .tcdm_rsp_t (tcdm_rsp_t), .AddrWidth (PhysicalAddrWidth), .DataWidth (NarrowDataWidth), .IdWidth (NarrowIdWidthOut), - .UserWidth (TcdmUserWidth), + .UserWidth (NarrowUserWidth), .BufDepth (MemoryMacroLatency + 1) ) i_axi_to_tcdm ( .clk_i, .rst_ni, .axi_req_i (narrow_axi_slv_req[TCDM]), .axi_rsp_o (narrow_axi_slv_rsp[TCDM]), - .tcdm_req_o (axi_soc_req), - .tcdm_rsp_i (axi_soc_rsp) + .tcdm_req_o (soc_tcdm_req), + .tcdm_rsp_i (soc_tcdm_rsp) + ); + + tcdm_width_converter #( + .InAddrWidth (PhysicalAddrWidth), + .InDataWidth (NarrowDataWidth), + .InUserWidth (NarrowUserWidth), + .OutAddrWidth (TCDMAddrWidth), + .OutDataWidth (NarrowDataWidth), + .OutUserWidth (TcdmUserWidth) + ) i_tcdm_width_converter_axi_soc ( + .tcdm_req_i (soc_tcdm_req), + .tcdm_rsp_o (soc_tcdm_rsp), + .tcdm_req_o (soc_tcdm_req_resized), + .tcdm_rsp_i (soc_tcdm_rsp_resized) ); // 2. Peripherals diff --git a/hw/snitch_cluster/src/snitch_cluster_pkg.sv b/hw/snitch_cluster/src/snitch_cluster_pkg.sv index 19c6e201af..baf1264702 100644 --- a/hw/snitch_cluster/src/snitch_cluster_pkg.sv +++ b/hw/snitch_cluster/src/snitch_cluster_pkg.sv @@ -6,9 +6,6 @@ package snitch_cluster_pkg; /// Fixed bootrom size in kB (always 4 kB). localparam int unsigned BootromSize = 4; - /// RISC-V hart ID width (32 bits per spec). - localparam int unsigned HartIdWidth = 32; - typedef logic [HartIdWidth-1:0] hart_id_t; // Slaves on Cluster AXI Bus typedef enum integer { diff --git a/hw/snitch_cluster/src/snitch_cluster_wrapper.sv b/hw/snitch_cluster/src/snitch_cluster_wrapper.sv index 5808fd0c16..5df46c93bd 100644 --- a/hw/snitch_cluster/src/snitch_cluster_wrapper.sv +++ b/hw/snitch_cluster/src/snitch_cluster_wrapper.sv @@ -12,7 +12,7 @@ module snitch_cluster_wrapper input logic [NrCores-1:0] mtip_i, input logic [NrCores-1:0] msip_i, input logic [NrCores-1:0] mxip_i, - input snitch_cluster_pkg::hart_id_t hart_base_id_i, + input snitch_pkg::hart_id_t hart_base_id_i, input logic [AddrWidth-1:0] cluster_base_addr_i, input logic [AddrWidth-1:0] cluster_base_offset_i, input logic clk_d2_bypass_i, @@ -64,16 +64,16 @@ module snitch_cluster_wrapper end // hart_base_id / cluster_base_addr / cluster_base_offset - snitch_cluster_pkg::hart_id_t hart_base_id_int; - logic [AddrWidth-1:0] cluster_base_addr_int; - logic [AddrWidth-1:0] cluster_base_offset_int; + snitch_pkg::hart_id_t hart_base_id_int; + logic [AddrWidth-1:0] cluster_base_addr_int; + logic [AddrWidth-1:0] cluster_base_offset_int; if (ClusterBaseExpose) begin : gen_base_fwd - assign hart_base_id_int = hart_base_id_i; - assign cluster_base_addr_int = cluster_base_addr_i; + assign hart_base_id_int = hart_base_id_i; + assign cluster_base_addr_int = cluster_base_addr_i; assign cluster_base_offset_int = cluster_base_offset_i; end else begin : gen_base_tie - assign hart_base_id_int = CfgBaseHartId; - assign cluster_base_addr_int = CfgClusterBaseAddr; + assign hart_base_id_int = CfgBaseHartId; + assign cluster_base_addr_int = CfgClusterBaseAddr; assign cluster_base_offset_int = CfgClusterBaseOffset; end @@ -127,7 +127,7 @@ module snitch_cluster_wrapper assign x_result_ready_o = x_result_ready_int; end else begin : gen_xif_tie assign x_issue_resp_int = '{NrCores{x_issue_resp_t'('0)}}; - assign x_issue_ready_int = '0; + assign x_issue_ready_int = '1; assign x_register_ready_int = '0; assign x_result_int = '{NrCores{x_result_t'('0)}}; assign x_result_valid_int = '0; @@ -231,9 +231,11 @@ module snitch_cluster_wrapper .NumITLBEntries (NumITLBEntries), .NumSsrsMax (NumSsrsMax), .NumSsrs (NumSsrs), - .SsrMuxRespDepth (SsrMuxRespDepth), + .SsrMuxRspDepth (SsrMuxRspDepth), .SsrRegs (SsrRegs), .SsrCfgs (SsrCfgs), + .SpatzDoubleBw (SpatzDoubleBw), + .NumSpatzOutstandingLoads (NumSpatzOutstandingLoads), .NumSequencerInstr (NumSequencerInstr), .NumSequencerLoops (NumSequencerLoops), .Hive (Hive), diff --git a/hw/snitch_cluster/src/snitch_cluster_wrapper_pkg.sv.tpl b/hw/snitch_cluster/src/snitch_cluster_wrapper_pkg.sv.tpl index d4a62c458d..0cb752d193 100644 --- a/hw/snitch_cluster/src/snitch_cluster_wrapper_pkg.sv.tpl +++ b/hw/snitch_cluster/src/snitch_cluster_wrapper_pkg.sv.tpl @@ -20,6 +20,12 @@ ${c[prop]}${', ' if not loop.last else ''}\ % endfor \ +<%def name="core_cfg_lambda(f)">\ + % for c in cfg['cluster']['cores']: +${f(c)}${', ' if not loop.last else ''}\ + % endfor +\ + <%def name="core_cfg_flat(prop)">\ ${cfg['cluster']['nr_cores']}'b\ % for c in cfg['cluster']['cores'][::-1]: @@ -297,11 +303,12 @@ package snitch_cluster_wrapper_pkg; RVE: ${int(getattr(c['isa_parsed'], 'e'))}, RVF: ${int(getattr(c['isa_parsed'], 'f'))}, RVD: ${int(getattr(c['isa_parsed'], 'd'))}, + RVV: ${int(getattr(c['isa_parsed'], 'v'))}, Xdma: ${int(c['xdma'])}, Xssr: ${int(c['xssr'])}, Xfrep: ${int(c['xfrep'])}, Xcopift: ${int(c['xcopift'])}, - XF16: ${int(c['xf16'])}, + Zfh: ${int(c['zfh'])}, XF16ALT: ${int(c['xf16alt'])}, XF8: ${int(c['xf8'])}, XF8ALT: ${int(c['xf8alt'])}, @@ -336,7 +343,7 @@ ${ssr_cfg(core, '{reg_idx}', '/*None*/ 0', ',')}\ }; // Forward potentially optional configuration parameters - localparam snitch_cluster_pkg::hart_id_t CfgBaseHartId = (${to_sv_hex(cfg['cluster']['cluster_base_hartid'], 32)}); + localparam snitch_pkg::hart_id_t CfgBaseHartId = (${to_sv_hex(cfg['cluster']['cluster_base_hartid'], 32)}); localparam addr_t CfgClusterBaseAddr = (${to_sv_hex(cfg['cluster']['cluster_base_addr'], cfg['cluster']['addr_width'])}); localparam addr_t CfgClusterBaseOffset = (${to_sv_hex(cfg['cluster']['cluster_base_offset'], cfg['cluster']['addr_width'])}); @@ -395,16 +402,18 @@ ${ssr_cfg(core, '{reg_idx}', '/*None*/ 0', ',')}\ localparam bit NarrowAxiPortExpose = ${int(cfg['cluster']['narrow_axi_port_expose'])}; // Per-core localparam arrays - localparam int unsigned NumIntOutstandingLoads [NrCores] = '{${core_cfg('num_int_outstanding_loads')}}; - localparam int unsigned NumIntOutstandingMem [NrCores] = '{${core_cfg('num_int_outstanding_mem')}}; - localparam int unsigned NumFPOutstandingLoads [NrCores] = '{${core_cfg('num_fp_outstanding_loads')}}; - localparam int unsigned NumFPOutstandingMem [NrCores] = '{${core_cfg('num_fp_outstanding_mem')}}; - localparam int unsigned NumDTLBEntries [NrCores] = '{${core_cfg('num_dtlb_entries')}}; - localparam int unsigned NumITLBEntries [NrCores] = '{${core_cfg('num_itlb_entries')}}; - localparam int unsigned NumSequencerInstr [NrCores] = '{${core_cfg('num_sequencer_instructions')}}; - localparam int unsigned NumSequencerLoops [NrCores] = '{${core_cfg('num_sequencer_loops')}}; - localparam int unsigned NumSsrs [NrCores] = '{${core_cfg('num_ssrs')}}; - localparam int unsigned SsrMuxRespDepth [NrCores] = '{${core_cfg('ssr_mux_resp_depth')}}; + localparam int unsigned NumIntOutstandingLoads [NrCores] = '{${core_cfg('num_int_outstanding_loads')}}; + localparam int unsigned NumIntOutstandingMem [NrCores] = '{${core_cfg('num_int_outstanding_mem')}}; + localparam int unsigned NumFPOutstandingLoads [NrCores] = '{${core_cfg('num_fp_outstanding_loads')}}; + localparam int unsigned NumFPOutstandingMem [NrCores] = '{${core_cfg('num_fp_outstanding_mem')}}; + localparam int unsigned NumDTLBEntries [NrCores] = '{${core_cfg('num_dtlb_entries')}}; + localparam int unsigned NumITLBEntries [NrCores] = '{${core_cfg('num_itlb_entries')}}; + localparam int unsigned NumSequencerInstr [NrCores] = '{${core_cfg('num_sequencer_instructions')}}; + localparam int unsigned NumSequencerLoops [NrCores] = '{${core_cfg('num_sequencer_loops')}}; + localparam int unsigned NumSsrs [NrCores] = '{${core_cfg('num_ssrs')}}; + localparam int unsigned SsrMuxRspDepth [NrCores] = '{${core_cfg('ssr_mux_rsp_depth')}}; + localparam bit SpatzDoubleBw [NrCores] = '{${core_cfg_lambda(lambda x: int(x['spatz']['double_bw']))}}; + localparam int unsigned NumSpatzOutstandingLoads [NrCores] = '{${core_cfg_lambda(lambda x: int(x['spatz']['num_outstanding_loads']))}}; endpackage // verilog_lint: waive-stop package-filename diff --git a/hw/snitch_cluster/src/snitch_hive.sv b/hw/snitch_cluster/src/snitch_hive.sv index 0c2fde7e43..0670e1167b 100644 --- a/hw/snitch_cluster/src/snitch_hive.sv +++ b/hw/snitch_cluster/src/snitch_hive.sv @@ -20,17 +20,15 @@ module snitch_hive import snitch_icache_pkg::*; #( parameter bit ICacheL1TagScm = 1'b0, parameter bit ICacheL1DataScm = 1'b0, parameter bit IsoCrossing = 1, - /// Address width of the buses + /// Widths of the buses. parameter int unsigned AddrWidth = 0, - /// Data width of the Narrow bus. parameter int unsigned NarrowDataWidth = 0, parameter int unsigned WideDataWidth = 0, + parameter int unsigned UserWidth = 0, /// Enable virtual memory support. parameter bit VMSupport = 1, parameter bit SharedIpu = 1, parameter bit Xpulpv2 = 0, - parameter type dreq_t = logic, - parameter type drsp_t = logic, parameter type axi_req_t = logic, parameter type axi_rsp_t = logic, parameter type hive_req_t = logic, @@ -38,8 +36,8 @@ module snitch_hive import snitch_icache_pkg::*; #( /// Configuration input types for memory cuts used in implementation. parameter type sram_cfg_t = logic, /// Derived parameter *Do not override* - parameter type addr_t = logic [AddrWidth-1:0], - parameter type data_t = logic [NarrowDataWidth-1:0] + localparam type lsu_req_t = `LSU_REQ_STRUCT(NarrowDataWidth, AddrWidth, UserWidth), + localparam type lsu_rsp_t = `LSU_RSP_STRUCT(NarrowDataWidth) ) ( input logic clk_i, input logic clk_d2_i, // divide-by-two clock @@ -48,8 +46,8 @@ module snitch_hive import snitch_icache_pkg::*; #( input hive_req_t [CoreCount-1:0] hive_req_i, output hive_rsp_t [CoreCount-1:0] hive_rsp_o, - output dreq_t ptw_data_req_o, - input drsp_t ptw_data_rsp_i, + output lsu_req_t ptw_data_req_o, + input lsu_rsp_t ptw_data_rsp_i, output axi_req_t axi_req_o, input axi_rsp_t axi_rsp_i, @@ -60,6 +58,9 @@ module snitch_hive import snitch_icache_pkg::*; #( output icache_l0_events_t [CoreCount-1:0] icache_events_o ); + typedef logic [AddrWidth-1:0] addr_t; + typedef logic [NarrowDataWidth-1:0] data_t; + // Extend the ID to route back results to the appropriate core. localparam int unsigned IdWidth = 5; localparam int unsigned LogCoreCount = cc_pkg::idx_width(CoreCount); @@ -189,17 +190,16 @@ module snitch_hive import snitch_icache_pkg::*; #( .oup_ready_i ( ptw_ready_out ) ); - dreq_t ptw_req; - drsp_t ptw_rsp; + lsu_req_t ptw_req; + lsu_rsp_t ptw_rsp; snitch_ptw #( .AddrWidth (AddrWidth), .DataWidth (NarrowDataWidth), + .UserWidth (UserWidth), .pa_t (pa_t), .l0_pte_t (l0_pte_t), - .pte_sv32_t (pte_sv32_t), - .dreq_t (dreq_t), - .drsp_t (drsp_t) + .pte_sv32_t (pte_sv32_t) ) i_snitch_ptw ( .clk_i ( clk_d2_i ), .rst_ni ( rst_ni ), @@ -213,11 +213,11 @@ module snitch_hive import snitch_icache_pkg::*; #( .data_rsp_i ( ptw_rsp ) ); + `LSU_TYPEDEF_REQRSP_CHAN_ALL(lsu, NarrowDataWidth, AddrWidth, UserWidth) + reqrsp_iso #( - .AddrWidth (AddrWidth), - .DataWidth (NarrowDataWidth), - .req_t (dreq_t), - .rsp_t (drsp_t), + .req_chan_t (lsu_req_chan_t), + .rsp_chan_t (lsu_rsp_chan_t), .BypassReq (1'b0), .BypassRsp (1'b0) ) i_reqrsp_iso ( @@ -261,7 +261,7 @@ module snitch_hive import snitch_icache_pkg::*; #( data_t data; } acc_rsp_chan_t; - `GENERIC_REQRSP_TYPEDEF_ALL(acc, acc_req_chan_t, acc_rsp_chan_t) + `REQRSP_TYPEDEF_ALL(acc, acc_req_chan_t, acc_rsp_chan_t) acc_req_chan_t acc_req_sfu; // to shared functional unit logic acc_req_sfu_valid; diff --git a/hw/snitch_cluster/src/snitch_tcdm_fc_interconnect.sv b/hw/snitch_cluster/src/snitch_tcdm_fc_interconnect.sv index 6c0080860c..26c53a55b1 100644 --- a/hw/snitch_cluster/src/snitch_tcdm_fc_interconnect.sv +++ b/hw/snitch_cluster/src/snitch_tcdm_fc_interconnect.sv @@ -79,7 +79,7 @@ module snitch_tcdm_fc_interconnect // as write data may freely change on (non-atomic) reads. We properly assert // conditional write data stability below. localparam mem_req_chan_t MemReqAsrtMask = - '{data: '0, strb: '0, amo: snitch_pkg::amo_op_e'('1), default: '1}; + '{data: '0, strb: '0, amo: lsu_pkg::amo_op_e'('1), default: '1}; // Width of the bank select signal. localparam int unsigned SelWidth = cc_pkg::idx_width(NumOut); @@ -121,7 +121,7 @@ module snitch_tcdm_fc_interconnect // Write data must also be stable during AMOs, so include this case in assertions. logic in_req_alters_mem; - assign in_req_alters_mem = in_req[i].write | (in_req[i].amo != snitch_pkg::AMONone); + assign in_req_alters_mem = in_req[i].write | (in_req[i].amo != lsu_pkg::AMONone); // TODO: we could clean this up with an additional common_cells assertion macro. `ifndef VERILATOR diff --git a/hw/snitch_cluster/test/snitch_tcdm_interconnect_tb.sv b/hw/snitch_cluster/test/snitch_tcdm_interconnect_tb.sv index af4fb40f63..2025482240 100644 --- a/hw/snitch_cluster/test/snitch_tcdm_interconnect_tb.sv +++ b/hw/snitch_cluster/test/snitch_tcdm_interconnect_tb.sv @@ -76,12 +76,12 @@ module snitch_tcdm_interconnect_tb #( for (genvar i = 0; i < NrInput; i++) begin : gen_input_assign `TCDM_ASSIGN_TO_REQ(tcdm_req[i], master_dv[i]); - `TCDM_ASSIGN_FROM_RESP(master_dv[i], tcdm_rsp[i]); + `TCDM_ASSIGN_FROM_RSP(master_dv[i], tcdm_rsp[i]); end for (genvar i = 0; i < NrOutput; i++) begin : gen_output_assign `MEM_ASSIGN_FROM_REQ(slave_dv[i], mem_req[i]); - `MEM_ASSIGN_TO_RESP(mem_rsp[i], slave_dv[i]); + `MEM_ASSIGN_TO_RSP(mem_rsp[i], slave_dv[i]); end // ---------------- diff --git a/hw/snitch_fp_ss/include/fpu_interface/assign.svh b/hw/snitch_fp_ss/include/fpu_interface/assign.svh deleted file mode 100644 index 66cba1d8dc..0000000000 --- a/hw/snitch_fp_ss/include/fpu_interface/assign.svh +++ /dev/null @@ -1,29 +0,0 @@ -// Copyright 2025 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Author: Luca Colagrande - -`ifndef FPU_INTERFACE_ASSIGN_SVH_ -`define FPU_INTERFACE_ASSIGN_SVH_ - -`define FPU_REQRSP_ASSIGN_REQ(__opt_as, dst, src) \ - __opt_as dst.q_valid = src.q_valid; \ - __opt_as dst.p_ready = src.p_ready; \ - __opt_as dst.q.operands = src.q.operands; \ - __opt_as dst.q.rnd_mode = src.q.rnd_mode; \ - __opt_as dst.q.op = src.q.op; \ - __opt_as dst.q.op_mod = src.q.op_mod; \ - __opt_as dst.q.src_fmt = src.q.src_fmt; \ - __opt_as dst.q.dst_fmt = src.q.dst_fmt; \ - __opt_as dst.q.int_fmt = src.q.int_fmt; \ - __opt_as dst.q.vectorial_op = src.q.vectorial_op; \ - __opt_as dst.q.tag = src.q.tag; -`define FPU_REQRSP_ASSIGN_RSP(__opt_as, dst, src) \ - __opt_as dst.p_valid = src.p_valid; \ - __opt_as dst.q_ready = src.q_ready; \ - __opt_as dst.p.status = src.p.status; \ - __opt_as dst.p.result = src.p.result; \ - __opt_as dst.p.tag = src.p.tag; - -`endif diff --git a/hw/snitch_fp_ss/include/fpu_interface/typedef.svh b/hw/snitch_fp_ss/include/fpu_interface/typedef.svh index 7a0e2134cc..b3e0158a30 100644 --- a/hw/snitch_fp_ss/include/fpu_interface/typedef.svh +++ b/hw/snitch_fp_ss/include/fpu_interface/typedef.svh @@ -30,10 +30,10 @@ } `define FPU_REQ_STRUCT(__data_width, __tag_t) \ - `GENERIC_REQRSP_REQ_STRUCT(`FPU_REQ_CHAN_STRUCT(__data_width, __tag_t)) + `REQRSP_REQ_STRUCT(`FPU_REQ_CHAN_STRUCT(__data_width, __tag_t)) `define FPU_RSP_STRUCT(__data_width, __tag_t) \ - `GENERIC_REQRSP_RSP_STRUCT(`FPU_RSP_CHAN_STRUCT(__data_width, __tag_t)) + `REQRSP_RSP_STRUCT(`FPU_RSP_CHAN_STRUCT(__data_width, __tag_t)) `define FPU_TYPEDEF_REQ_CHAN_T(__name, __data_width, __tag_t) \ typedef `FPU_REQ_CHAN_STRUCT(__data_width, __tag_t) __name``_req_chan_t; @@ -47,6 +47,6 @@ `define FPU_TYPEDEF_REQRSP_ALL(__name, __data_width, __tag_t) \ `FPU_TYPEDEF_REQRSP_CHAN_ALL(__name, __data_width, __tag_t) \ - `GENERIC_REQRSP_TYPEDEF_ALL(__name, __name``_req_chan_t, __name``_rsp_chan_t) + `REQRSP_TYPEDEF_ALL(__name, __name``_req_chan_t, __name``_rsp_chan_t) `endif // FPU_INTERFACE_TYPEDEF_SVH_ diff --git a/hw/snitch_fp_ss/src/snitch_fp_ss.sv b/hw/snitch_fp_ss/src/snitch_fp_ss.sv index 8392c191fa..672f38992e 100644 --- a/hw/snitch_fp_ss/src/snitch_fp_ss.sv +++ b/hw/snitch_fp_ss/src/snitch_fp_ss.sv @@ -5,22 +5,20 @@ `include "common_cells/registers.svh" `include "common_cells/assertions.svh" `include "reqrsp_interface/assign.svh" -`include "fpu_interface/assign.svh" `include "fpu_interface/typedef.svh" -`include "dca_interface/assign.svh" `include "dca_interface/typedef.svh" `include "snitch/typedef.svh" // Floating Point Subsystem -module snitch_fp_ss import snitch_pkg::*; #( +module snitch_fp_ss + import snitch_pkg::*; +#( parameter int unsigned AddrWidth = 32, parameter int unsigned DataWidth = 32, parameter int unsigned NumFPOutstandingLoads = 0, parameter int unsigned NumFPOutstandingMem = 0, parameter int unsigned NumFPUSequencerInstr = 0, parameter int unsigned NumFPUSequencerLoops = 0, - parameter type dreq_t = logic, - parameter type drsp_t = logic, parameter bit RegisterSequencer = 0, parameter bit RegisterFpuReq = 0, parameter bit RegisterFpuRsp = 0, @@ -30,8 +28,9 @@ module snitch_fp_ss import snitch_pkg::*; #( parameter logic [NumSsrs-1:0][4:0] SsrRegs = '0, parameter bit EnableDca = 0, /// Derived parameter *Do not override* - localparam type addr_t = logic [AddrWidth-1:0], localparam type data_t = logic [DataWidth-1:0], + localparam type lsu_req_t = `LSU_REQ_STRUCT(DataWidth, AddrWidth, UserWidth), + localparam type lsu_rsp_t = `LSU_RSP_STRUCT(DataWidth), localparam type dca_req_t = `DCA_REQ_STRUCT(DataWidth), localparam type dca_rsp_t = `DCA_RSP_STRUCT(DataWidth), localparam type acc_req_t = `SNITCH_ACC_REQ_STRUCT(DataWidth, AddrWidth), @@ -40,9 +39,9 @@ module snitch_fp_ss import snitch_pkg::*; #( input logic clk_i, input logic rst_i, // pragma translate_off - output fpu_trace_port_t trace_port_o, - output fpu_sequencer_trace_port_t sequencer_tracer_port_o, - output dca_trace_port_t dca_trace_port_o, + output fpss_trace_t trace_o, + output fpu_sequencer_trace_t sequencer_trace_o, + output dca_trace_t dca_trace_o, // pragma translate_on input logic [31:0] hart_id_i, // Accelerator Interface - Slave @@ -57,8 +56,8 @@ module snitch_fp_ss import snitch_pkg::*; #( output logic f2i_wvalid_o, input logic f2i_wready_i, // TCDM Data Interface for regular FP load/stores. - output dreq_t data_req_o, - input drsp_t data_rsp_i, + output lsu_req_t data_req_o, + input lsu_rsp_t data_rsp_i, // Register Interface // FPU **un-timed** Side-channel input fpnew_pkg::roundmode_e fpu_rnd_mode_i, @@ -220,7 +219,7 @@ module snitch_fp_ss import snitch_pkg::*; #( .clk_i, .rst_i, // pragma translate_off - .trace_port_o ( sequencer_tracer_port_o ), + .trace_o ( sequencer_trace_o ), // pragma translate_on .inp_qaddr_i ( acc_req_i.q.addr ), .inp_qid_i ( acc_req_i.q.id ), @@ -245,7 +244,7 @@ module snitch_fp_ss import snitch_pkg::*; #( ); end else begin : gen_no_fpu_sequencer // pragma translate_off - assign sequencer_tracer_port_o = 0; + assign sequencer_trace_o = 0; // pragma translate_on assign acc_rsp_o.q_ready = acc_req_ready; assign acc_req_valid = acc_req_i.q_valid; @@ -392,65 +391,65 @@ module snitch_fp_ss import snitch_pkg::*; #( unique casez (acc_req_q.data_op) // FP - FP Operations // Single Precision - riscv_instr::FADD_S: begin + snitch_riscv_instr::FADD_S: begin fpu_op = fpnew_pkg::ADD; op_select[1] = RegA; op_select[2] = RegB; end - riscv_instr::FSUB_S: begin + snitch_riscv_instr::FSUB_S: begin fpu_op = fpnew_pkg::ADD; op_select[1] = RegA; op_select[2] = RegB; op_mode = 1'b1; end - riscv_instr::FMUL_S: begin + snitch_riscv_instr::FMUL_S: begin fpu_op = fpnew_pkg::MUL; op_select[0] = RegA; op_select[1] = RegB; end - riscv_instr::FDIV_S: begin // currently illegal + snitch_riscv_instr::FDIV_S: begin // currently illegal fpu_op = fpnew_pkg::DIV; op_select[0] = RegA; op_select[1] = RegB; end - riscv_instr::FSGNJ_S, - riscv_instr::FSGNJN_S, - riscv_instr::FSGNJX_S: begin + snitch_riscv_instr::FSGNJ_S, + snitch_riscv_instr::FSGNJN_S, + snitch_riscv_instr::FSGNJX_S: begin fpu_op = fpnew_pkg::SGNJ; op_select[0] = RegA; op_select[1] = RegB; end - riscv_instr::FMIN_S, - riscv_instr::FMAX_S: begin + snitch_riscv_instr::FMIN_S, + snitch_riscv_instr::FMAX_S: begin fpu_op = fpnew_pkg::MINMAX; op_select[0] = RegA; op_select[1] = RegB; end - riscv_instr::FSQRT_S: begin // currently illegal + snitch_riscv_instr::FSQRT_S: begin // currently illegal fpu_op = fpnew_pkg::SQRT; op_select[0] = RegA; op_select[1] = RegA; end - riscv_instr::FMADD_S: begin + snitch_riscv_instr::FMADD_S: begin fpu_op = fpnew_pkg::FMADD; op_select[0] = RegA; op_select[1] = RegB; op_select[2] = RegC; end - riscv_instr::FMSUB_S: begin + snitch_riscv_instr::FMSUB_S: begin fpu_op = fpnew_pkg::FMADD; op_select[0] = RegA; op_select[1] = RegB; op_select[2] = RegC; op_mode = 1'b1; end - riscv_instr::FNMSUB_S: begin + snitch_riscv_instr::FNMSUB_S: begin fpu_op = fpnew_pkg::FNMSUB; op_select[0] = RegA; op_select[1] = RegB; op_select[2] = RegC; end - riscv_instr::FNMADD_S: begin + snitch_riscv_instr::FNMADD_S: begin fpu_op = fpnew_pkg::FNMSUB; op_select[0] = RegA; op_select[1] = RegB; @@ -458,117 +457,117 @@ module snitch_fp_ss import snitch_pkg::*; #( op_mode = 1'b1; end // Vectorial Single Precision - riscv_instr::VFADD_S, - riscv_instr::VFADD_R_S: begin + snitch_riscv_instr::VFADD_S, + snitch_riscv_instr::VFADD_R_S: begin fpu_op = fpnew_pkg::ADD; op_select[1] = RegA; op_select[2] = RegB; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFADD_R_S}) op_select[2] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFADD_R_S}) op_select[2] = RegBRep; end - riscv_instr::VFSUB_S, - riscv_instr::VFSUB_R_S: begin + snitch_riscv_instr::VFSUB_S, + snitch_riscv_instr::VFSUB_R_S: begin fpu_op = fpnew_pkg::ADD; op_select[1] = RegA; op_select[2] = RegB; op_mode = 1'b1; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSUB_R_S}) op_select[2] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFSUB_R_S}) op_select[2] = RegBRep; end - riscv_instr::VFMUL_S, - riscv_instr::VFMUL_R_S: begin + snitch_riscv_instr::VFMUL_S, + snitch_riscv_instr::VFMUL_R_S: begin fpu_op = fpnew_pkg::MUL; op_select[0] = RegA; op_select[1] = RegB; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMUL_R_S}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFMUL_R_S}) op_select[1] = RegBRep; end - riscv_instr::VFDIV_S, - riscv_instr::VFDIV_R_S: begin // currently illegal + snitch_riscv_instr::VFDIV_S, + snitch_riscv_instr::VFDIV_R_S: begin // currently illegal fpu_op = fpnew_pkg::DIV; op_select[0] = RegA; op_select[1] = RegB; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFDIV_R_S}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFDIV_R_S}) op_select[1] = RegBRep; end - riscv_instr::VFMIN_S, - riscv_instr::VFMIN_R_S: begin + snitch_riscv_instr::VFMIN_S, + snitch_riscv_instr::VFMIN_R_S: begin fpu_op = fpnew_pkg::MINMAX; op_select[0] = RegA; op_select[1] = RegB; fpu_rnd_mode = fpnew_pkg::RNE; vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMIN_R_S}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFMIN_R_S}) op_select[1] = RegBRep; end - riscv_instr::VFMAX_S, - riscv_instr::VFMAX_R_S: begin + snitch_riscv_instr::VFMAX_S, + snitch_riscv_instr::VFMAX_R_S: begin fpu_op = fpnew_pkg::MINMAX; op_select[0] = RegA; op_select[1] = RegB; fpu_rnd_mode = fpnew_pkg::RTZ; vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMAX_R_S}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFMAX_R_S}) op_select[1] = RegBRep; end - riscv_instr::VFSQRT_S: begin // currently illegal + snitch_riscv_instr::VFSQRT_S: begin // currently illegal fpu_op = fpnew_pkg::SQRT; op_select[0] = RegA; op_select[1] = RegA; vectorial_op = 1'b1; set_dyn_rm = 1'b1; end - riscv_instr::VFMAC_S, - riscv_instr::VFMAC_R_S: begin + snitch_riscv_instr::VFMAC_S, + snitch_riscv_instr::VFMAC_R_S: begin fpu_op = fpnew_pkg::FMADD; op_select[0] = RegA; op_select[1] = RegB; op_select[2] = RegDest; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMAC_R_S}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFMAC_R_S}) op_select[1] = RegBRep; end - riscv_instr::VFMRE_S, - riscv_instr::VFMRE_R_S: begin + snitch_riscv_instr::VFMRE_S, + snitch_riscv_instr::VFMRE_R_S: begin fpu_op = fpnew_pkg::FNMSUB; op_select[0] = RegA; op_select[1] = RegB; op_select[2] = RegDest; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMRE_R_S}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFMRE_R_S}) op_select[1] = RegBRep; end - riscv_instr::VFSGNJ_S, - riscv_instr::VFSGNJ_R_S: begin + snitch_riscv_instr::VFSGNJ_S, + snitch_riscv_instr::VFSGNJ_R_S: begin fpu_op = fpnew_pkg::SGNJ; op_select[0] = RegA; op_select[1] = RegB; fpu_rnd_mode = fpnew_pkg::RNE; vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSGNJ_R_S}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFSGNJ_R_S}) op_select[1] = RegBRep; end - riscv_instr::VFSGNJN_S, - riscv_instr::VFSGNJN_R_S: begin + snitch_riscv_instr::VFSGNJN_S, + snitch_riscv_instr::VFSGNJN_R_S: begin fpu_op = fpnew_pkg::SGNJ; op_select[0] = RegA; op_select[1] = RegB; fpu_rnd_mode = fpnew_pkg::RTZ; vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSGNJN_R_S}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFSGNJN_R_S}) op_select[1] = RegBRep; end - riscv_instr::VFSGNJX_S, - riscv_instr::VFSGNJX_R_S: begin + snitch_riscv_instr::VFSGNJX_S, + snitch_riscv_instr::VFSGNJX_R_S: begin fpu_op = fpnew_pkg::SGNJ; op_select[0] = RegA; op_select[1] = RegB; fpu_rnd_mode = fpnew_pkg::RDN; vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSGNJX_R_S}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFSGNJX_R_S}) op_select[1] = RegBRep; end - riscv_instr::VFSUM_S, - riscv_instr::VFNSUM_S: begin + snitch_riscv_instr::VFSUM_S, + snitch_riscv_instr::VFNSUM_S: begin fpu_op = fpnew_pkg::VSUM; op_select[0] = RegA; op_select[2] = RegDest; @@ -576,16 +575,16 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP32; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFNSUM_S}) op_mode = 1'b1; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFNSUM_S}) op_mode = 1'b1; end - riscv_instr::VFCPKA_S_S: begin + snitch_riscv_instr::VFCPKA_S_S: begin fpu_op = fpnew_pkg::CPKAB; op_select[0] = RegA; op_select[1] = RegB; vectorial_op = 1'b1; set_dyn_rm = 1'b1; end - riscv_instr::VFCPKA_S_D: begin + snitch_riscv_instr::VFCPKA_S_D: begin fpu_op = fpnew_pkg::CPKAB; op_select[0] = RegA; op_select[1] = RegB; @@ -593,25 +592,25 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; set_dyn_rm = 1'b1; end - riscv_instr::VFCVT_D_S, - riscv_instr::VFCVTU_D_S: begin + snitch_riscv_instr::VFCVT_D_S, + snitch_riscv_instr::VFCVTU_D_S: begin fpu_op = fpnew_pkg::F2F; op_select[0] = RegA; src_fmt = fpnew_pkg::FP32; dst_fmt = fpnew_pkg::FP64; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVTU_D_S}) op_mode = 1'b1; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFCVTU_D_S}) op_mode = 1'b1; end // Double Precision - riscv_instr::FADD_D: begin + snitch_riscv_instr::FADD_D: begin fpu_op = fpnew_pkg::ADD; op_select[1] = RegA; op_select[2] = RegB; src_fmt = fpnew_pkg::FP64; dst_fmt = fpnew_pkg::FP64; end - riscv_instr::FSUB_D: begin + snitch_riscv_instr::FSUB_D: begin fpu_op = fpnew_pkg::ADD; op_select[1] = RegA; op_select[2] = RegB; @@ -619,45 +618,45 @@ module snitch_fp_ss import snitch_pkg::*; #( src_fmt = fpnew_pkg::FP64; dst_fmt = fpnew_pkg::FP64; end - riscv_instr::FMUL_D: begin + snitch_riscv_instr::FMUL_D: begin fpu_op = fpnew_pkg::MUL; op_select[0] = RegA; op_select[1] = RegB; src_fmt = fpnew_pkg::FP64; dst_fmt = fpnew_pkg::FP64; end - riscv_instr::FDIV_D: begin + snitch_riscv_instr::FDIV_D: begin fpu_op = fpnew_pkg::DIV; op_select[0] = RegA; op_select[1] = RegB; src_fmt = fpnew_pkg::FP64; dst_fmt = fpnew_pkg::FP64; end - riscv_instr::FSGNJ_D, - riscv_instr::FSGNJN_D, - riscv_instr::FSGNJX_D: begin + snitch_riscv_instr::FSGNJ_D, + snitch_riscv_instr::FSGNJN_D, + snitch_riscv_instr::FSGNJX_D: begin fpu_op = fpnew_pkg::SGNJ; op_select[0] = RegA; op_select[1] = RegB; src_fmt = fpnew_pkg::FP64; dst_fmt = fpnew_pkg::FP64; end - riscv_instr::FMIN_D, - riscv_instr::FMAX_D: begin + snitch_riscv_instr::FMIN_D, + snitch_riscv_instr::FMAX_D: begin fpu_op = fpnew_pkg::MINMAX; op_select[0] = RegA; op_select[1] = RegB; src_fmt = fpnew_pkg::FP64; dst_fmt = fpnew_pkg::FP64; end - riscv_instr::FSQRT_D: begin + snitch_riscv_instr::FSQRT_D: begin fpu_op = fpnew_pkg::SQRT; op_select[0] = RegA; op_select[1] = RegA; src_fmt = fpnew_pkg::FP64; dst_fmt = fpnew_pkg::FP64; end - riscv_instr::FMADD_D: begin + snitch_riscv_instr::FMADD_D: begin fpu_op = fpnew_pkg::FMADD; op_select[0] = RegA; op_select[1] = RegB; @@ -665,7 +664,7 @@ module snitch_fp_ss import snitch_pkg::*; #( src_fmt = fpnew_pkg::FP64; dst_fmt = fpnew_pkg::FP64; end - riscv_instr::FMSUB_D: begin + snitch_riscv_instr::FMSUB_D: begin fpu_op = fpnew_pkg::FMADD; op_select[0] = RegA; op_select[1] = RegB; @@ -674,7 +673,7 @@ module snitch_fp_ss import snitch_pkg::*; #( src_fmt = fpnew_pkg::FP64; dst_fmt = fpnew_pkg::FP64; end - riscv_instr::FNMSUB_D: begin + snitch_riscv_instr::FNMSUB_D: begin fpu_op = fpnew_pkg::FNMSUB; op_select[0] = RegA; op_select[1] = RegB; @@ -682,7 +681,7 @@ module snitch_fp_ss import snitch_pkg::*; #( src_fmt = fpnew_pkg::FP64; dst_fmt = fpnew_pkg::FP64; end - riscv_instr::FNMADD_D: begin + snitch_riscv_instr::FNMADD_D: begin fpu_op = fpnew_pkg::FNMSUB; op_select[0] = RegA; op_select[1] = RegB; @@ -691,20 +690,20 @@ module snitch_fp_ss import snitch_pkg::*; #( src_fmt = fpnew_pkg::FP64; dst_fmt = fpnew_pkg::FP64; end - riscv_instr::FCVT_S_D: begin + snitch_riscv_instr::FCVT_S_D: begin fpu_op = fpnew_pkg::F2F; op_select[0] = RegA; src_fmt = fpnew_pkg::FP64; dst_fmt = fpnew_pkg::FP32; end - riscv_instr::FCVT_D_S: begin + snitch_riscv_instr::FCVT_D_S: begin fpu_op = fpnew_pkg::F2F; op_select[0] = RegA; src_fmt = fpnew_pkg::FP32; dst_fmt = fpnew_pkg::FP64; end // [Alternate] Half Precision - riscv_instr::FADD_H: begin + snitch_riscv_instr::FADD_H: begin fpu_op = fpnew_pkg::ADD; op_select[1] = RegA; op_select[2] = RegB; @@ -715,7 +714,7 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP16ALT; end end - riscv_instr::FSUB_H: begin + snitch_riscv_instr::FSUB_H: begin fpu_op = fpnew_pkg::ADD; op_select[1] = RegA; op_select[2] = RegB; @@ -727,7 +726,7 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP16ALT; end end - riscv_instr::FMUL_H: begin + snitch_riscv_instr::FMUL_H: begin fpu_op = fpnew_pkg::MUL; op_select[0] = RegA; op_select[1] = RegB; @@ -738,7 +737,7 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP16ALT; end end - riscv_instr::FDIV_H: begin + snitch_riscv_instr::FDIV_H: begin fpu_op = fpnew_pkg::DIV; op_select[0] = RegA; op_select[1] = RegB; @@ -749,9 +748,9 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP16ALT; end end - riscv_instr::FSGNJ_H, - riscv_instr::FSGNJN_H, - riscv_instr::FSGNJX_H: begin + snitch_riscv_instr::FSGNJ_H, + snitch_riscv_instr::FSGNJN_H, + snitch_riscv_instr::FSGNJX_H: begin fpu_op = fpnew_pkg::SGNJ; op_select[0] = RegA; op_select[1] = RegB; @@ -762,8 +761,8 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP16ALT; end end - riscv_instr::FMIN_H, - riscv_instr::FMAX_H: begin + snitch_riscv_instr::FMIN_H, + snitch_riscv_instr::FMAX_H: begin fpu_op = fpnew_pkg::MINMAX; op_select[0] = RegA; op_select[1] = RegB; @@ -774,7 +773,7 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP16ALT; end end - riscv_instr::FSQRT_H: begin + snitch_riscv_instr::FSQRT_H: begin fpu_op = fpnew_pkg::SQRT; op_select[0] = RegA; op_select[1] = RegA; @@ -785,7 +784,7 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP16ALT; end end - riscv_instr::FMADD_H: begin + snitch_riscv_instr::FMADD_H: begin fpu_op = fpnew_pkg::FMADD; op_select[0] = RegA; op_select[1] = RegB; @@ -797,7 +796,7 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP16ALT; end end - riscv_instr::FMSUB_H: begin + snitch_riscv_instr::FMSUB_H: begin fpu_op = fpnew_pkg::FMADD; op_select[0] = RegA; op_select[1] = RegB; @@ -810,7 +809,7 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP16ALT; end end - riscv_instr::FNMSUB_H: begin + snitch_riscv_instr::FNMSUB_H: begin fpu_op = fpnew_pkg::FNMSUB; op_select[0] = RegA; op_select[1] = RegB; @@ -822,7 +821,7 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP16ALT; end end - riscv_instr::FNMADD_H: begin + snitch_riscv_instr::FNMADD_H: begin fpu_op = fpnew_pkg::FNMSUB; op_select[0] = RegA; op_select[1] = RegB; @@ -835,8 +834,8 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP16ALT; end end - riscv_instr::VFSUM_H, - riscv_instr::VFNSUM_H: begin + snitch_riscv_instr::VFSUM_H, + snitch_riscv_instr::VFNSUM_H: begin fpu_op = fpnew_pkg::VSUM; op_select[0] = RegA; op_select[2] = RegDest; @@ -844,16 +843,16 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP16; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFNSUM_H}) op_mode = 1'b1; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFNSUM_H}) op_mode = 1'b1; end - riscv_instr::FMULEX_S_H: begin + snitch_riscv_instr::FMULEX_S_H: begin fpu_op = fpnew_pkg::MUL; op_select[0] = RegA; op_select[1] = RegB; src_fmt = fpnew_pkg::FP16; dst_fmt = fpnew_pkg::FP32; end - riscv_instr::FMACEX_S_H: begin + snitch_riscv_instr::FMACEX_S_H: begin fpu_op = fpnew_pkg::FMADD; op_select[0] = RegA; op_select[1] = RegB; @@ -861,33 +860,33 @@ module snitch_fp_ss import snitch_pkg::*; #( src_fmt = fpnew_pkg::FP16; dst_fmt = fpnew_pkg::FP32; end - riscv_instr::FCVT_S_H: begin + snitch_riscv_instr::FCVT_S_H: begin fpu_op = fpnew_pkg::F2F; op_select[0] = RegA; src_fmt = fpnew_pkg::FP16; dst_fmt = fpnew_pkg::FP32; end - riscv_instr::FCVT_H_S: begin + snitch_riscv_instr::FCVT_H_S: begin fpu_op = fpnew_pkg::F2F; op_select[0] = RegA; src_fmt = fpnew_pkg::FP32; dst_fmt = fpnew_pkg::FP16; end - riscv_instr::FCVT_D_H: begin + snitch_riscv_instr::FCVT_D_H: begin fpu_op = fpnew_pkg::F2F; op_select[0] = RegA; src_fmt = fpnew_pkg::FP16; dst_fmt = fpnew_pkg::FP64; end - riscv_instr::FCVT_H_D: begin + snitch_riscv_instr::FCVT_H_D: begin fpu_op = fpnew_pkg::F2F; op_select[0] = RegA; src_fmt = fpnew_pkg::FP64; dst_fmt = fpnew_pkg::FP16; end // Vectorial [alternate] Half Precision - riscv_instr::VFADD_H, - riscv_instr::VFADD_R_H: begin + snitch_riscv_instr::VFADD_H, + snitch_riscv_instr::VFADD_R_H: begin fpu_op = fpnew_pkg::ADD; op_select[1] = RegA; op_select[2] = RegB; @@ -899,10 +898,10 @@ module snitch_fp_ss import snitch_pkg::*; #( end vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFADD_R_H}) op_select[2] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFADD_R_H}) op_select[2] = RegBRep; end - riscv_instr::VFSUB_H, - riscv_instr::VFSUB_R_H: begin + snitch_riscv_instr::VFSUB_H, + snitch_riscv_instr::VFSUB_R_H: begin fpu_op = fpnew_pkg::ADD; op_select[1] = RegA; op_select[2] = RegB; @@ -915,10 +914,10 @@ module snitch_fp_ss import snitch_pkg::*; #( end vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSUB_R_H}) op_select[2] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFSUB_R_H}) op_select[2] = RegBRep; end - riscv_instr::VFMUL_H, - riscv_instr::VFMUL_R_H: begin + snitch_riscv_instr::VFMUL_H, + snitch_riscv_instr::VFMUL_R_H: begin fpu_op = fpnew_pkg::MUL; op_select[0] = RegA; op_select[1] = RegB; @@ -930,10 +929,10 @@ module snitch_fp_ss import snitch_pkg::*; #( end vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMUL_R_H}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFMUL_R_H}) op_select[1] = RegBRep; end - riscv_instr::VFDIV_H, - riscv_instr::VFDIV_R_H: begin + snitch_riscv_instr::VFDIV_H, + snitch_riscv_instr::VFDIV_R_H: begin fpu_op = fpnew_pkg::DIV; op_select[0] = RegA; op_select[1] = RegB; @@ -945,10 +944,10 @@ module snitch_fp_ss import snitch_pkg::*; #( end vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFDIV_R_H}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFDIV_R_H}) op_select[1] = RegBRep; end - riscv_instr::VFMIN_H, - riscv_instr::VFMIN_R_H: begin + snitch_riscv_instr::VFMIN_H, + snitch_riscv_instr::VFMIN_R_H: begin fpu_op = fpnew_pkg::MINMAX; op_select[0] = RegA; op_select[1] = RegB; @@ -960,10 +959,10 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP16ALT; end vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMIN_R_H}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFMIN_R_H}) op_select[1] = RegBRep; end - riscv_instr::VFMAX_H, - riscv_instr::VFMAX_R_H: begin + snitch_riscv_instr::VFMAX_H, + snitch_riscv_instr::VFMAX_R_H: begin fpu_op = fpnew_pkg::MINMAX; op_select[0] = RegA; op_select[1] = RegB; @@ -975,9 +974,9 @@ module snitch_fp_ss import snitch_pkg::*; #( end fpu_rnd_mode = fpnew_pkg::RTZ; vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMAX_R_H}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFMAX_R_H}) op_select[1] = RegBRep; end - riscv_instr::VFSQRT_H: begin + snitch_riscv_instr::VFSQRT_H: begin fpu_op = fpnew_pkg::SQRT; op_select[0] = RegA; op_select[1] = RegA; @@ -990,8 +989,8 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; set_dyn_rm = 1'b1; end - riscv_instr::VFMAC_H, - riscv_instr::VFMAC_R_H: begin + snitch_riscv_instr::VFMAC_H, + snitch_riscv_instr::VFMAC_R_H: begin fpu_op = fpnew_pkg::FMADD; op_select[0] = RegA; op_select[1] = RegB; @@ -1004,10 +1003,10 @@ module snitch_fp_ss import snitch_pkg::*; #( end vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMAC_R_H}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFMAC_R_H}) op_select[1] = RegBRep; end - riscv_instr::VFMRE_H, - riscv_instr::VFMRE_R_H: begin + snitch_riscv_instr::VFMRE_H, + snitch_riscv_instr::VFMRE_R_H: begin fpu_op = fpnew_pkg::FNMSUB; op_select[0] = RegA; op_select[1] = RegB; @@ -1020,10 +1019,10 @@ module snitch_fp_ss import snitch_pkg::*; #( end vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMRE_R_H}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFMRE_R_H}) op_select[1] = RegBRep; end - riscv_instr::VFSGNJ_H, - riscv_instr::VFSGNJ_R_H: begin + snitch_riscv_instr::VFSGNJ_H, + snitch_riscv_instr::VFSGNJ_R_H: begin fpu_op = fpnew_pkg::SGNJ; op_select[0] = RegA; op_select[1] = RegB; @@ -1035,10 +1034,10 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP16ALT; end vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSGNJ_R_H}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFSGNJ_R_H}) op_select[1] = RegBRep; end - riscv_instr::VFSGNJN_H, - riscv_instr::VFSGNJN_R_H: begin + snitch_riscv_instr::VFSGNJN_H, + snitch_riscv_instr::VFSGNJN_R_H: begin fpu_op = fpnew_pkg::SGNJ; op_select[0] = RegA; op_select[1] = RegB; @@ -1050,10 +1049,10 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP16ALT; end vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSGNJN_R_H}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFSGNJN_R_H}) op_select[1] = RegBRep; end - riscv_instr::VFSGNJX_H, - riscv_instr::VFSGNJX_R_H: begin + snitch_riscv_instr::VFSGNJX_H, + snitch_riscv_instr::VFSGNJX_R_H: begin fpu_op = fpnew_pkg::SGNJ; op_select[0] = RegA; op_select[1] = RegB; @@ -1065,9 +1064,9 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP16ALT; end vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSGNJX_R_H}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFSGNJX_R_H}) op_select[1] = RegBRep; end - riscv_instr::VFCPKA_H_S: begin + snitch_riscv_instr::VFCPKA_H_S: begin fpu_op = fpnew_pkg::CPKAB; op_select[0] = RegA; op_select[1] = RegB; @@ -1077,7 +1076,7 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; set_dyn_rm = 1'b1; end - riscv_instr::VFCPKB_H_S: begin + snitch_riscv_instr::VFCPKB_H_S: begin fpu_op = fpnew_pkg::CPKAB; op_select[0] = RegA; op_select[1] = RegB; @@ -1088,27 +1087,27 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; set_dyn_rm = 1'b1; end - riscv_instr::VFCVT_S_H, - riscv_instr::VFCVTU_S_H: begin + snitch_riscv_instr::VFCVT_S_H, + snitch_riscv_instr::VFCVTU_S_H: begin fpu_op = fpnew_pkg::F2F; op_select[0] = RegA; src_fmt = fpnew_pkg::FP16; dst_fmt = fpnew_pkg::FP32; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVTU_S_H}) op_mode = 1'b1; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFCVTU_S_H}) op_mode = 1'b1; end - riscv_instr::VFCVT_H_S, - riscv_instr::VFCVTU_H_S: begin + snitch_riscv_instr::VFCVT_H_S, + snitch_riscv_instr::VFCVTU_H_S: begin fpu_op = fpnew_pkg::F2F; op_select[0] = RegA; src_fmt = fpnew_pkg::FP32; dst_fmt = fpnew_pkg::FP16; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVTU_H_S}) op_mode = 1'b1; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFCVTU_H_S}) op_mode = 1'b1; end - riscv_instr::VFCPKA_H_D: begin + snitch_riscv_instr::VFCPKA_H_D: begin fpu_op = fpnew_pkg::CPKAB; op_select[0] = RegA; op_select[1] = RegB; @@ -1118,7 +1117,7 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; set_dyn_rm = 1'b1; end - riscv_instr::VFCPKB_H_D: begin + snitch_riscv_instr::VFCPKB_H_D: begin fpu_op = fpnew_pkg::CPKAB; op_select[0] = RegA; op_select[1] = RegB; @@ -1129,8 +1128,8 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; set_dyn_rm = 1'b1; end - riscv_instr::VFDOTPEX_S_H, - riscv_instr::VFDOTPEX_S_R_H: begin + snitch_riscv_instr::VFDOTPEX_S_H, + snitch_riscv_instr::VFDOTPEX_S_R_H: begin fpu_op = fpnew_pkg::SDOTP; op_select[0] = RegA; op_select[1] = RegB; @@ -1139,10 +1138,10 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP32; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFDOTPEX_S_R_H}) op_select[2] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFDOTPEX_S_R_H}) op_select[2] = RegBRep; end - riscv_instr::VFNDOTPEX_S_H, - riscv_instr::VFNDOTPEX_S_R_H: begin + snitch_riscv_instr::VFNDOTPEX_S_H, + snitch_riscv_instr::VFNDOTPEX_S_R_H: begin fpu_op = fpnew_pkg::SDOTP; op_select[0] = RegA; op_select[1] = RegB; @@ -1152,10 +1151,10 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP32; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFNDOTPEX_S_R_H}) op_select[2] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFNDOTPEX_S_R_H}) op_select[2] = RegBRep; end - riscv_instr::VFSUMEX_S_H, - riscv_instr::VFNSUMEX_S_H: begin + snitch_riscv_instr::VFSUMEX_S_H, + snitch_riscv_instr::VFNSUMEX_S_H: begin fpu_op = fpnew_pkg::EXVSUM; op_select[0] = RegA; op_select[2] = RegDest; @@ -1163,10 +1162,10 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP32; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFNSUMEX_S_H}) op_mode = 1'b1; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFNSUMEX_S_H}) op_mode = 1'b1; end // [Alternate] Quarter Precision - riscv_instr::FADD_B: begin + snitch_riscv_instr::FADD_B: begin fpu_op = fpnew_pkg::ADD; op_select[1] = RegA; op_select[2] = RegB; @@ -1177,7 +1176,7 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP8ALT; end end - riscv_instr::FSUB_B: begin + snitch_riscv_instr::FSUB_B: begin fpu_op = fpnew_pkg::ADD; op_select[1] = RegA; op_select[2] = RegB; @@ -1189,7 +1188,7 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP8ALT; end end - riscv_instr::FMUL_B: begin + snitch_riscv_instr::FMUL_B: begin fpu_op = fpnew_pkg::MUL; op_select[0] = RegA; op_select[1] = RegB; @@ -1200,7 +1199,7 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP8ALT; end end - riscv_instr::FDIV_B: begin + snitch_riscv_instr::FDIV_B: begin fpu_op = fpnew_pkg::DIV; op_select[0] = RegA; op_select[1] = RegB; @@ -1211,9 +1210,9 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP8ALT; end end - riscv_instr::FSGNJ_B, - riscv_instr::FSGNJN_B, - riscv_instr::FSGNJX_B: begin + snitch_riscv_instr::FSGNJ_B, + snitch_riscv_instr::FSGNJN_B, + snitch_riscv_instr::FSGNJX_B: begin fpu_op = fpnew_pkg::SGNJ; op_select[0] = RegA; op_select[1] = RegB; @@ -1224,8 +1223,8 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP8ALT; end end - riscv_instr::FMIN_B, - riscv_instr::FMAX_B: begin + snitch_riscv_instr::FMIN_B, + snitch_riscv_instr::FMAX_B: begin fpu_op = fpnew_pkg::MINMAX; op_select[0] = RegA; op_select[1] = RegB; @@ -1236,7 +1235,7 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP8ALT; end end - riscv_instr::FSQRT_B: begin + snitch_riscv_instr::FSQRT_B: begin fpu_op = fpnew_pkg::SQRT; op_select[0] = RegA; op_select[1] = RegA; @@ -1247,7 +1246,7 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP8ALT; end end - riscv_instr::FMADD_B: begin + snitch_riscv_instr::FMADD_B: begin fpu_op = fpnew_pkg::FMADD; op_select[0] = RegA; op_select[1] = RegB; @@ -1259,7 +1258,7 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP8ALT; end end - riscv_instr::FMSUB_B: begin + snitch_riscv_instr::FMSUB_B: begin fpu_op = fpnew_pkg::FMADD; op_select[0] = RegA; op_select[1] = RegB; @@ -1272,7 +1271,7 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP8ALT; end end - riscv_instr::FNMSUB_B: begin + snitch_riscv_instr::FNMSUB_B: begin fpu_op = fpnew_pkg::FNMSUB; op_select[0] = RegA; op_select[1] = RegB; @@ -1284,7 +1283,7 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP8ALT; end end - riscv_instr::FNMADD_B: begin + snitch_riscv_instr::FNMADD_B: begin fpu_op = fpnew_pkg::FNMSUB; op_select[0] = RegA; op_select[1] = RegB; @@ -1297,8 +1296,8 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP8ALT; end end - riscv_instr::VFSUM_B, - riscv_instr::VFNSUM_B: begin + snitch_riscv_instr::VFSUM_B, + snitch_riscv_instr::VFNSUM_B: begin fpu_op = fpnew_pkg::VSUM; op_select[0] = RegA; op_select[2] = RegDest; @@ -1306,16 +1305,16 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP8; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFNSUM_B}) op_mode = 1'b1; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFNSUM_B}) op_mode = 1'b1; end - riscv_instr::FMULEX_S_B: begin + snitch_riscv_instr::FMULEX_S_B: begin fpu_op = fpnew_pkg::MUL; op_select[0] = RegA; op_select[1] = RegB; src_fmt = fpnew_pkg::FP8; dst_fmt = fpnew_pkg::FP32; end - riscv_instr::FMACEX_S_B: begin + snitch_riscv_instr::FMACEX_S_B: begin fpu_op = fpnew_pkg::FMADD; op_select[0] = RegA; op_select[1] = RegB; @@ -1323,45 +1322,45 @@ module snitch_fp_ss import snitch_pkg::*; #( src_fmt = fpnew_pkg::FP8; dst_fmt = fpnew_pkg::FP32; end - riscv_instr::FCVT_S_B: begin + snitch_riscv_instr::FCVT_S_B: begin fpu_op = fpnew_pkg::F2F; op_select[0] = RegA; src_fmt = fpnew_pkg::FP8; dst_fmt = fpnew_pkg::FP32; end - riscv_instr::FCVT_B_S: begin + snitch_riscv_instr::FCVT_B_S: begin fpu_op = fpnew_pkg::F2F; op_select[0] = RegA; src_fmt = fpnew_pkg::FP32; dst_fmt = fpnew_pkg::FP8; end - riscv_instr::FCVT_D_B: begin + snitch_riscv_instr::FCVT_D_B: begin fpu_op = fpnew_pkg::F2F; op_select[0] = RegA; src_fmt = fpnew_pkg::FP8; dst_fmt = fpnew_pkg::FP64; end - riscv_instr::FCVT_B_D: begin + snitch_riscv_instr::FCVT_B_D: begin fpu_op = fpnew_pkg::F2F; op_select[0] = RegA; src_fmt = fpnew_pkg::FP64; dst_fmt = fpnew_pkg::FP8; end - riscv_instr::FCVT_H_B: begin + snitch_riscv_instr::FCVT_H_B: begin fpu_op = fpnew_pkg::F2F; op_select[0] = RegA; src_fmt = fpnew_pkg::FP8; dst_fmt = fpnew_pkg::FP16; end - riscv_instr::FCVT_B_H: begin + snitch_riscv_instr::FCVT_B_H: begin fpu_op = fpnew_pkg::F2F; op_select[0] = RegA; src_fmt = fpnew_pkg::FP16; dst_fmt = fpnew_pkg::FP8; end // Vectorial [alternate] Quarter Precision - riscv_instr::VFADD_B, - riscv_instr::VFADD_R_B: begin + snitch_riscv_instr::VFADD_B, + snitch_riscv_instr::VFADD_R_B: begin fpu_op = fpnew_pkg::ADD; op_select[1] = RegA; op_select[2] = RegB; @@ -1373,10 +1372,10 @@ module snitch_fp_ss import snitch_pkg::*; #( end vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFADD_R_B}) op_select[2] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFADD_R_B}) op_select[2] = RegBRep; end - riscv_instr::VFSUB_B, - riscv_instr::VFSUB_R_B: begin + snitch_riscv_instr::VFSUB_B, + snitch_riscv_instr::VFSUB_R_B: begin fpu_op = fpnew_pkg::ADD; op_select[1] = RegA; op_select[2] = RegB; @@ -1389,10 +1388,10 @@ module snitch_fp_ss import snitch_pkg::*; #( end vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSUB_R_B}) op_select[2] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFSUB_R_B}) op_select[2] = RegBRep; end - riscv_instr::VFMUL_B, - riscv_instr::VFMUL_R_B: begin + snitch_riscv_instr::VFMUL_B, + snitch_riscv_instr::VFMUL_R_B: begin fpu_op = fpnew_pkg::MUL; op_select[0] = RegA; op_select[1] = RegB; @@ -1404,10 +1403,10 @@ module snitch_fp_ss import snitch_pkg::*; #( end vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMUL_R_B}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFMUL_R_B}) op_select[1] = RegBRep; end - riscv_instr::VFDIV_B, - riscv_instr::VFDIV_R_B: begin + snitch_riscv_instr::VFDIV_B, + snitch_riscv_instr::VFDIV_R_B: begin fpu_op = fpnew_pkg::DIV; op_select[0] = RegA; op_select[1] = RegB; @@ -1419,10 +1418,10 @@ module snitch_fp_ss import snitch_pkg::*; #( end vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFDIV_R_B}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFDIV_R_B}) op_select[1] = RegBRep; end - riscv_instr::VFMIN_B, - riscv_instr::VFMIN_R_B: begin + snitch_riscv_instr::VFMIN_B, + snitch_riscv_instr::VFMIN_R_B: begin fpu_op = fpnew_pkg::MINMAX; op_select[0] = RegA; op_select[1] = RegB; @@ -1434,10 +1433,10 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP8ALT; end vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMIN_R_B}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFMIN_R_B}) op_select[1] = RegBRep; end - riscv_instr::VFMAX_B, - riscv_instr::VFMAX_R_B: begin + snitch_riscv_instr::VFMAX_B, + snitch_riscv_instr::VFMAX_R_B: begin fpu_op = fpnew_pkg::MINMAX; op_select[0] = RegA; op_select[1] = RegB; @@ -1449,9 +1448,9 @@ module snitch_fp_ss import snitch_pkg::*; #( end fpu_rnd_mode = fpnew_pkg::RTZ; vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMAX_R_B}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFMAX_R_B}) op_select[1] = RegBRep; end - riscv_instr::VFSQRT_B: begin + snitch_riscv_instr::VFSQRT_B: begin fpu_op = fpnew_pkg::SQRT; op_select[0] = RegA; op_select[1] = RegA; @@ -1464,8 +1463,8 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; set_dyn_rm = 1'b1; end - riscv_instr::VFMAC_B, - riscv_instr::VFMAC_R_B: begin + snitch_riscv_instr::VFMAC_B, + snitch_riscv_instr::VFMAC_R_B: begin fpu_op = fpnew_pkg::FMADD; op_select[0] = RegA; op_select[1] = RegB; @@ -1478,10 +1477,10 @@ module snitch_fp_ss import snitch_pkg::*; #( end vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMAC_R_B}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFMAC_R_B}) op_select[1] = RegBRep; end - riscv_instr::VFMRE_B, - riscv_instr::VFMRE_R_B: begin + snitch_riscv_instr::VFMRE_B, + snitch_riscv_instr::VFMRE_R_B: begin fpu_op = fpnew_pkg::FNMSUB; op_select[0] = RegA; op_select[1] = RegB; @@ -1494,10 +1493,10 @@ module snitch_fp_ss import snitch_pkg::*; #( end vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFMRE_R_B}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFMRE_R_B}) op_select[1] = RegBRep; end - riscv_instr::VFSGNJ_B, - riscv_instr::VFSGNJ_R_B: begin + snitch_riscv_instr::VFSGNJ_B, + snitch_riscv_instr::VFSGNJ_R_B: begin fpu_op = fpnew_pkg::SGNJ; op_select[0] = RegA; op_select[1] = RegB; @@ -1509,10 +1508,10 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP8ALT; end vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSGNJ_R_B}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFSGNJ_R_B}) op_select[1] = RegBRep; end - riscv_instr::VFSGNJN_B, - riscv_instr::VFSGNJN_R_B: begin + snitch_riscv_instr::VFSGNJN_B, + snitch_riscv_instr::VFSGNJN_R_B: begin fpu_op = fpnew_pkg::SGNJ; op_select[0] = RegA; op_select[1] = RegB; @@ -1524,10 +1523,10 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP8ALT; end vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSGNJN_R_B}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFSGNJN_R_B}) op_select[1] = RegBRep; end - riscv_instr::VFSGNJX_B, - riscv_instr::VFSGNJX_R_B: begin + snitch_riscv_instr::VFSGNJX_B, + snitch_riscv_instr::VFSGNJX_R_B: begin fpu_op = fpnew_pkg::SGNJ; op_select[0] = RegA; op_select[1] = RegB; @@ -1539,10 +1538,10 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP8ALT; end vectorial_op = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFSGNJX_R_B}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFSGNJX_R_B}) op_select[1] = RegBRep; end - riscv_instr::VFCPKA_B_S, - riscv_instr::VFCPKB_B_S: begin + snitch_riscv_instr::VFCPKA_B_S, + snitch_riscv_instr::VFCPKB_B_S: begin fpu_op = fpnew_pkg::CPKAB; op_select[0] = RegA; op_select[1] = RegB; @@ -1551,10 +1550,10 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP8; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCPKB_B_S}) op_mode = 1; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFCPKB_B_S}) op_mode = 1; end - riscv_instr::VFCPKC_B_S, - riscv_instr::VFCPKD_B_S: begin + snitch_riscv_instr::VFCPKC_B_S, + snitch_riscv_instr::VFCPKD_B_S: begin fpu_op = fpnew_pkg::CPKCD; op_select[0] = RegA; op_select[1] = RegB; @@ -1563,10 +1562,10 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP8; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCPKD_B_S}) op_mode = 1; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFCPKD_B_S}) op_mode = 1; end - riscv_instr::VFCPKA_B_D, - riscv_instr::VFCPKB_B_D: begin + snitch_riscv_instr::VFCPKA_B_D, + snitch_riscv_instr::VFCPKB_B_D: begin fpu_op = fpnew_pkg::CPKAB; op_select[0] = RegA; op_select[1] = RegB; @@ -1575,10 +1574,10 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP8; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCPKB_B_D}) op_mode = 1; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFCPKB_B_D}) op_mode = 1; end - riscv_instr::VFCPKC_B_D, - riscv_instr::VFCPKD_B_D: begin + snitch_riscv_instr::VFCPKC_B_D, + snitch_riscv_instr::VFCPKD_B_D: begin fpu_op = fpnew_pkg::CPKCD; op_select[0] = RegA; op_select[1] = RegB; @@ -1587,70 +1586,70 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP8; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCPKD_B_D}) op_mode = 1; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFCPKD_B_D}) op_mode = 1; end - riscv_instr::VFCVT_S_B, - riscv_instr::VFCVTU_S_B: begin + snitch_riscv_instr::VFCVT_S_B, + snitch_riscv_instr::VFCVTU_S_B: begin fpu_op = fpnew_pkg::F2F; op_select[0] = RegA; src_fmt = fpnew_pkg::FP8; dst_fmt = fpnew_pkg::FP32; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVTU_S_B}) op_mode = 1'b1; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFCVTU_S_B}) op_mode = 1'b1; end - riscv_instr::VFCVT_B_S, - riscv_instr::VFCVTU_B_S: begin + snitch_riscv_instr::VFCVT_B_S, + snitch_riscv_instr::VFCVTU_B_S: begin fpu_op = fpnew_pkg::F2F; op_select[0] = RegA; src_fmt = fpnew_pkg::FP32; dst_fmt = fpnew_pkg::FP8; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVTU_B_S}) op_mode = 1'b1; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFCVTU_B_S}) op_mode = 1'b1; end - riscv_instr::VFCVT_H_H, - riscv_instr::VFCVTU_H_H: begin + snitch_riscv_instr::VFCVT_H_H, + snitch_riscv_instr::VFCVTU_H_H: begin fpu_op = fpnew_pkg::F2F; op_select[0] = RegA; src_fmt = fpnew_pkg::FP16; dst_fmt = fpnew_pkg::FP16; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVTU_H_H}) op_mode = 1'b1; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFCVTU_H_H}) op_mode = 1'b1; end - riscv_instr::VFCVT_H_B, - riscv_instr::VFCVTU_H_B: begin + snitch_riscv_instr::VFCVT_H_B, + snitch_riscv_instr::VFCVTU_H_B: begin fpu_op = fpnew_pkg::F2F; op_select[0] = RegA; src_fmt = fpnew_pkg::FP8; dst_fmt = fpnew_pkg::FP16; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVTU_H_B}) op_mode = 1'b1; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFCVTU_H_B}) op_mode = 1'b1; end - riscv_instr::VFCVT_B_H, - riscv_instr::VFCVTU_B_H: begin + snitch_riscv_instr::VFCVT_B_H, + snitch_riscv_instr::VFCVTU_B_H: begin fpu_op = fpnew_pkg::F2F; op_select[0] = RegA; src_fmt = fpnew_pkg::FP16; dst_fmt = fpnew_pkg::FP8; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVTU_B_H}) op_mode = 1'b1; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFCVTU_B_H}) op_mode = 1'b1; end - riscv_instr::VFCVT_B_B, - riscv_instr::VFCVTU_B_B: begin + snitch_riscv_instr::VFCVT_B_B, + snitch_riscv_instr::VFCVTU_B_B: begin fpu_op = fpnew_pkg::F2F; op_select[0] = RegA; src_fmt = fpnew_pkg::FP8; dst_fmt = fpnew_pkg::FP8; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVTU_B_B}) op_mode = 1'b1; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFCVTU_B_B}) op_mode = 1'b1; end - riscv_instr::VFDOTPEX_H_B, - riscv_instr::VFDOTPEX_H_R_B: begin + snitch_riscv_instr::VFDOTPEX_H_B, + snitch_riscv_instr::VFDOTPEX_H_R_B: begin fpu_op = fpnew_pkg::SDOTP; op_select[0] = RegA; op_select[1] = RegB; @@ -1659,10 +1658,10 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP16; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFDOTPEX_H_R_B}) op_select[2] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFDOTPEX_H_R_B}) op_select[2] = RegBRep; end - riscv_instr::VFNDOTPEX_H_B, - riscv_instr::VFNDOTPEX_H_R_B: begin + snitch_riscv_instr::VFNDOTPEX_H_B, + snitch_riscv_instr::VFNDOTPEX_H_R_B: begin fpu_op = fpnew_pkg::SDOTP; op_select[0] = RegA; op_select[1] = RegB; @@ -1672,10 +1671,10 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP16; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFNDOTPEX_H_R_B}) op_select[2] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFNDOTPEX_H_R_B}) op_select[2] = RegBRep; end - riscv_instr::VFSUMEX_H_B, - riscv_instr::VFNSUMEX_H_B: begin + snitch_riscv_instr::VFSUMEX_H_B, + snitch_riscv_instr::VFNSUMEX_H_B: begin fpu_op = fpnew_pkg::EXVSUM; op_select[0] = RegA; op_select[2] = RegDest; @@ -1683,15 +1682,15 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP16; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFNSUMEX_H_B}) op_mode = 1'b1; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFNSUMEX_H_B}) op_mode = 1'b1; end // ------------------- // From float to int // ------------------- // Single Precision Floating-Point - riscv_instr::FLE_S, - riscv_instr::FLT_S, - riscv_instr::FEQ_S: begin + snitch_riscv_instr::FLE_S, + snitch_riscv_instr::FLT_S, + snitch_riscv_instr::FEQ_S: begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; op_select[1] = RegB; @@ -1700,7 +1699,7 @@ module snitch_fp_ss import snitch_pkg::*; #( fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; end - riscv_instr::FCLASS_S: begin + snitch_riscv_instr::FCLASS_S: begin fpu_op = fpnew_pkg::CLASSIFY; op_select[0] = RegA; fpu_rnd_mode = fpnew_pkg::RNE; @@ -1709,17 +1708,17 @@ module snitch_fp_ss import snitch_pkg::*; #( fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; end - riscv_instr::FCVT_W_S, - riscv_instr::FCVT_WU_S: begin + snitch_riscv_instr::FCVT_W_S, + snitch_riscv_instr::FCVT_WU_S: begin fpu_op = fpnew_pkg::F2I; op_select[0] = RegA; src_fmt = fpnew_pkg::FP32; dst_fmt = fpnew_pkg::FP32; fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::FCVT_WU_S}) op_mode = 1'b1; // unsigned + if (acc_req_q.data_op inside {snitch_riscv_instr::FCVT_WU_S}) op_mode = 1'b1; // unsigned end - riscv_instr::FMV_X_W: begin + snitch_riscv_instr::FMV_X_W: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box src_fmt = fpnew_pkg::FP32; @@ -1730,8 +1729,8 @@ module snitch_fp_ss import snitch_pkg::*; #( rd_is_fp = 1'b0; end // Vectorial Single Precision - riscv_instr::VFEQ_S, - riscv_instr::VFEQ_R_S: begin + snitch_riscv_instr::VFEQ_S, + snitch_riscv_instr::VFEQ_R_S: begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; op_select[1] = RegB; @@ -1741,10 +1740,10 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFEQ_R_S}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFEQ_R_S}) op_select[1] = RegBRep; end - riscv_instr::VFNE_S, - riscv_instr::VFNE_R_S: begin + snitch_riscv_instr::VFNE_S, + snitch_riscv_instr::VFNE_R_S: begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; op_select[1] = RegB; @@ -1755,10 +1754,10 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFNE_R_S}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFNE_R_S}) op_select[1] = RegBRep; end - riscv_instr::VFLT_S, - riscv_instr::VFLT_R_S: begin + snitch_riscv_instr::VFLT_S, + snitch_riscv_instr::VFLT_R_S: begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; op_select[1] = RegB; @@ -1768,10 +1767,10 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFLT_R_S}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFLT_R_S}) op_select[1] = RegBRep; end - riscv_instr::VFGE_S, - riscv_instr::VFGE_R_S: begin + snitch_riscv_instr::VFGE_S, + snitch_riscv_instr::VFGE_R_S: begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; op_select[1] = RegB; @@ -1782,10 +1781,10 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFGE_R_S}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFGE_R_S}) op_select[1] = RegBRep; end - riscv_instr::VFLE_S, - riscv_instr::VFLE_R_S: begin + snitch_riscv_instr::VFLE_S, + snitch_riscv_instr::VFLE_R_S: begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; op_select[1] = RegB; @@ -1795,10 +1794,10 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFLE_R_S}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFLE_R_S}) op_select[1] = RegBRep; end - riscv_instr::VFGT_S, - riscv_instr::VFGT_R_S: begin + snitch_riscv_instr::VFGT_S, + snitch_riscv_instr::VFGT_R_S: begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; op_select[1] = RegB; @@ -1809,9 +1808,9 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFGT_R_S}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFGT_R_S}) op_select[1] = RegBRep; end - riscv_instr::VFCLASS_S: begin + snitch_riscv_instr::VFCLASS_S: begin fpu_op = fpnew_pkg::CLASSIFY; op_select[0] = RegA; fpu_rnd_mode = fpnew_pkg::RNE; @@ -1822,9 +1821,9 @@ module snitch_fp_ss import snitch_pkg::*; #( rd_is_fp = 1'b0; end // Double Precision Floating-Point - riscv_instr::FLE_D, - riscv_instr::FLT_D, - riscv_instr::FEQ_D: begin + snitch_riscv_instr::FLE_D, + snitch_riscv_instr::FLT_D, + snitch_riscv_instr::FEQ_D: begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; op_select[1] = RegB; @@ -1834,7 +1833,7 @@ module snitch_fp_ss import snitch_pkg::*; #( rd_is_fp = 1'b0; end // Double Precision Floating-Point, MC extension - riscv_instr::FLT_D_COPIFT: begin + snitch_riscv_instr::FLT_D_COPIFT: begin if (IsaCfg.Xcopift) begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; @@ -1843,7 +1842,7 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP64; end end - riscv_instr::FCLASS_D: begin + snitch_riscv_instr::FCLASS_D: begin fpu_op = fpnew_pkg::CLASSIFY; op_select[0] = RegA; fpu_rnd_mode = fpnew_pkg::RNE; @@ -1852,17 +1851,17 @@ module snitch_fp_ss import snitch_pkg::*; #( fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; end - riscv_instr::FCVT_W_D, - riscv_instr::FCVT_WU_D: begin + snitch_riscv_instr::FCVT_W_D, + snitch_riscv_instr::FCVT_WU_D: begin fpu_op = fpnew_pkg::F2I; op_select[0] = RegA; src_fmt = fpnew_pkg::FP64; dst_fmt = fpnew_pkg::FP64; fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::FCVT_WU_D}) op_mode = 1'b1; // unsigned + if (acc_req_q.data_op inside {snitch_riscv_instr::FCVT_WU_D}) op_mode = 1'b1; // unsigned end - riscv_instr::FMV_X_D: begin + snitch_riscv_instr::FMV_X_D: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box src_fmt = fpnew_pkg::FP64; @@ -1873,9 +1872,9 @@ module snitch_fp_ss import snitch_pkg::*; #( rd_is_fp = 1'b0; end // [Alternate] Half Precision Floating-Point - riscv_instr::FLE_H, - riscv_instr::FLT_H, - riscv_instr::FEQ_H: begin + snitch_riscv_instr::FLE_H, + snitch_riscv_instr::FLT_H, + snitch_riscv_instr::FEQ_H: begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; op_select[1] = RegB; @@ -1888,7 +1887,7 @@ module snitch_fp_ss import snitch_pkg::*; #( fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; end - riscv_instr::FCLASS_H: begin + snitch_riscv_instr::FCLASS_H: begin fpu_op = fpnew_pkg::CLASSIFY; op_select[0] = RegA; fpu_rnd_mode = fpnew_pkg::RNE; @@ -1901,17 +1900,17 @@ module snitch_fp_ss import snitch_pkg::*; #( fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; end - riscv_instr::FCVT_W_H, - riscv_instr::FCVT_WU_H: begin + snitch_riscv_instr::FCVT_W_H, + snitch_riscv_instr::FCVT_WU_H: begin fpu_op = fpnew_pkg::F2I; op_select[0] = RegA; src_fmt = fpnew_pkg::FP16; dst_fmt = fpnew_pkg::FP16; fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::FCVT_WU_H}) op_mode = 1'b1; // unsigned + if (acc_req_q.data_op inside {snitch_riscv_instr::FCVT_WU_H}) op_mode = 1'b1; // unsigned end - riscv_instr::FMV_X_H: begin + snitch_riscv_instr::FMV_X_H: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box src_fmt = fpnew_pkg::FP16; @@ -1926,8 +1925,8 @@ module snitch_fp_ss import snitch_pkg::*; #( rd_is_fp = 1'b0; end // Vectorial [alternate] Half Precision - riscv_instr::VFEQ_H, - riscv_instr::VFEQ_R_H: begin + snitch_riscv_instr::VFEQ_H, + snitch_riscv_instr::VFEQ_R_H: begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; op_select[1] = RegB; @@ -1941,10 +1940,10 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFEQ_R_H}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFEQ_R_H}) op_select[1] = RegBRep; end - riscv_instr::VFNE_H, - riscv_instr::VFNE_R_H: begin + snitch_riscv_instr::VFNE_H, + snitch_riscv_instr::VFNE_R_H: begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; op_select[1] = RegB; @@ -1959,10 +1958,10 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFNE_R_H}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFNE_R_H}) op_select[1] = RegBRep; end - riscv_instr::VFLT_H, - riscv_instr::VFLT_R_H: begin + snitch_riscv_instr::VFLT_H, + snitch_riscv_instr::VFLT_R_H: begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; op_select[1] = RegB; @@ -1976,10 +1975,10 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFLT_R_H}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFLT_R_H}) op_select[1] = RegBRep; end - riscv_instr::VFGE_H, - riscv_instr::VFGE_R_H: begin + snitch_riscv_instr::VFGE_H, + snitch_riscv_instr::VFGE_R_H: begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; op_select[1] = RegB; @@ -1994,10 +1993,10 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFGE_R_H}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFGE_R_H}) op_select[1] = RegBRep; end - riscv_instr::VFLE_H, - riscv_instr::VFLE_R_H: begin + snitch_riscv_instr::VFLE_H, + snitch_riscv_instr::VFLE_R_H: begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; op_select[1] = RegB; @@ -2011,10 +2010,10 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFLE_R_H}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFLE_R_H}) op_select[1] = RegBRep; end - riscv_instr::VFGT_H, - riscv_instr::VFGT_R_H: begin + snitch_riscv_instr::VFGT_H, + snitch_riscv_instr::VFGT_R_H: begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; op_select[1] = RegB; @@ -2029,9 +2028,9 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFGT_R_H}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFGT_R_H}) op_select[1] = RegBRep; end - riscv_instr::VFCLASS_H: begin + snitch_riscv_instr::VFCLASS_H: begin fpu_op = fpnew_pkg::CLASSIFY; op_select[0] = RegA; fpu_rnd_mode = fpnew_pkg::RNE; @@ -2045,7 +2044,7 @@ module snitch_fp_ss import snitch_pkg::*; #( fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; end - riscv_instr::VFMV_X_H: begin + snitch_riscv_instr::VFMV_X_H: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box src_fmt = fpnew_pkg::FP16; @@ -2060,8 +2059,8 @@ module snitch_fp_ss import snitch_pkg::*; #( fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; end - riscv_instr::VFCVT_X_H, - riscv_instr::VFCVT_XU_H: begin + snitch_riscv_instr::VFCVT_X_H, + snitch_riscv_instr::VFCVT_XU_H: begin fpu_op = fpnew_pkg::F2I; op_select[0] = RegA; src_fmt = fpnew_pkg::FP16; @@ -2075,12 +2074,12 @@ module snitch_fp_ss import snitch_pkg::*; #( fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVT_XU_H}) op_mode = 1'b1; // upper + if (acc_req_q.data_op inside {snitch_riscv_instr::VFCVT_XU_H}) op_mode = 1'b1; // upper end // [Alternate] Quarter Precision Floating-Point - riscv_instr::FLE_B, - riscv_instr::FLT_B, - riscv_instr::FEQ_B: begin + snitch_riscv_instr::FLE_B, + snitch_riscv_instr::FLT_B, + snitch_riscv_instr::FEQ_B: begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; op_select[1] = RegB; @@ -2093,7 +2092,7 @@ module snitch_fp_ss import snitch_pkg::*; #( fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; end - riscv_instr::FCLASS_B: begin + snitch_riscv_instr::FCLASS_B: begin fpu_op = fpnew_pkg::CLASSIFY; op_select[0] = RegA; fpu_rnd_mode = fpnew_pkg::RNE; @@ -2106,8 +2105,8 @@ module snitch_fp_ss import snitch_pkg::*; #( fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; end - riscv_instr::FCVT_W_B, - riscv_instr::FCVT_WU_B: begin + snitch_riscv_instr::FCVT_W_B, + snitch_riscv_instr::FCVT_WU_B: begin fpu_op = fpnew_pkg::F2I; op_select[0] = RegA; src_fmt = fpnew_pkg::FP8; @@ -2118,9 +2117,9 @@ module snitch_fp_ss import snitch_pkg::*; #( end fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::FCVT_WU_B}) op_mode = 1'b1; // unsigned + if (acc_req_q.data_op inside {snitch_riscv_instr::FCVT_WU_B}) op_mode = 1'b1; // unsigned end - riscv_instr::FMV_X_B: begin + snitch_riscv_instr::FMV_X_B: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box src_fmt = fpnew_pkg::FP8; @@ -2135,8 +2134,8 @@ module snitch_fp_ss import snitch_pkg::*; #( rd_is_fp = 1'b0; end // Vectorial Quarter Precision - riscv_instr::VFEQ_B, - riscv_instr::VFEQ_R_B: begin + snitch_riscv_instr::VFEQ_B, + snitch_riscv_instr::VFEQ_R_B: begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; op_select[1] = RegB; @@ -2150,10 +2149,10 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFEQ_R_B}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFEQ_R_B}) op_select[1] = RegBRep; end - riscv_instr::VFNE_B, - riscv_instr::VFNE_R_B: begin + snitch_riscv_instr::VFNE_B, + snitch_riscv_instr::VFNE_R_B: begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; op_select[1] = RegB; @@ -2168,10 +2167,10 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFNE_R_B}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFNE_R_B}) op_select[1] = RegBRep; end - riscv_instr::VFLT_B, - riscv_instr::VFLT_R_B: begin + snitch_riscv_instr::VFLT_B, + snitch_riscv_instr::VFLT_R_B: begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; op_select[1] = RegB; @@ -2185,10 +2184,10 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFLT_R_B}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFLT_R_B}) op_select[1] = RegBRep; end - riscv_instr::VFGE_B, - riscv_instr::VFGE_R_B: begin + snitch_riscv_instr::VFGE_B, + snitch_riscv_instr::VFGE_R_B: begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; op_select[1] = RegB; @@ -2203,10 +2202,10 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFGE_R_B}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFGE_R_B}) op_select[1] = RegBRep; end - riscv_instr::VFLE_B, - riscv_instr::VFLE_R_B: begin + snitch_riscv_instr::VFLE_B, + snitch_riscv_instr::VFLE_R_B: begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; op_select[1] = RegB; @@ -2220,10 +2219,10 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFLE_R_B}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFLE_R_B}) op_select[1] = RegBRep; end - riscv_instr::VFGT_B, - riscv_instr::VFGT_R_B: begin + snitch_riscv_instr::VFGT_B, + snitch_riscv_instr::VFGT_R_B: begin fpu_op = fpnew_pkg::CMP; op_select[0] = RegA; op_select[1] = RegB; @@ -2238,9 +2237,9 @@ module snitch_fp_ss import snitch_pkg::*; #( vectorial_op = 1'b1; fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; - if (acc_req_q.data_op inside {riscv_instr::VFGT_R_B}) op_select[1] = RegBRep; + if (acc_req_q.data_op inside {snitch_riscv_instr::VFGT_R_B}) op_select[1] = RegBRep; end - riscv_instr::VFCLASS_B: begin + snitch_riscv_instr::VFCLASS_B: begin fpu_op = fpnew_pkg::CLASSIFY; op_select[0] = RegA; fpu_rnd_mode = fpnew_pkg::RNE; @@ -2254,7 +2253,7 @@ module snitch_fp_ss import snitch_pkg::*; #( fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; end - riscv_instr::VFMV_X_B: begin + snitch_riscv_instr::VFMV_X_B: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box src_fmt = fpnew_pkg::FP8; @@ -2269,8 +2268,8 @@ module snitch_fp_ss import snitch_pkg::*; #( fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; end - riscv_instr::VFCVT_X_B, - riscv_instr::VFCVT_XU_B: begin + snitch_riscv_instr::VFCVT_X_B, + snitch_riscv_instr::VFCVT_XU_B: begin fpu_op = fpnew_pkg::F2I; op_select[0] = RegA; src_fmt = fpnew_pkg::FP8; @@ -2284,48 +2283,48 @@ module snitch_fp_ss import snitch_pkg::*; #( fpu_tag_in.acc = 1'b1; rd_is_fp = 1'b0; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVT_XU_B}) op_mode = 1'b1; // upper + if (acc_req_q.data_op inside {snitch_riscv_instr::VFCVT_XU_B}) op_mode = 1'b1; // upper end // ------------------- // From int to float // ------------------- // Single Precision Floating-Point - riscv_instr::FMV_W_X: begin + snitch_riscv_instr::FMV_W_X: begin fpu_op = fpnew_pkg::SGNJ; op_select[0] = AccBus; fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box src_fmt = fpnew_pkg::FP32; dst_fmt = fpnew_pkg::FP32; end - riscv_instr::FCVT_S_W, - riscv_instr::FCVT_S_WU: begin + snitch_riscv_instr::FCVT_S_W, + snitch_riscv_instr::FCVT_S_WU: begin fpu_op = fpnew_pkg::I2F; op_select[0] = AccBus; dst_fmt = fpnew_pkg::FP32; - if (acc_req_q.data_op inside {riscv_instr::FCVT_S_WU}) op_mode = 1'b1; // unsigned + if (acc_req_q.data_op inside {snitch_riscv_instr::FCVT_S_WU}) op_mode = 1'b1; // unsigned end // Double Precision Floating-Point - riscv_instr::FCVT_D_W, - riscv_instr::FCVT_D_WU: begin + snitch_riscv_instr::FCVT_D_W, + snitch_riscv_instr::FCVT_D_WU: begin fpu_op = fpnew_pkg::I2F; op_select[0] = AccBus; src_fmt = fpnew_pkg::FP64; dst_fmt = fpnew_pkg::FP64; - if (acc_req_q.data_op inside {riscv_instr::FCVT_D_WU}) op_mode = 1'b1; // unsigned + if (acc_req_q.data_op inside {snitch_riscv_instr::FCVT_D_WU}) op_mode = 1'b1; // unsigned end // Double Precision Floating-Point - riscv_instr::FCVT_D_W_COPIFT, - riscv_instr::FCVT_D_WU_COPIFT: begin + snitch_riscv_instr::FCVT_D_W_COPIFT, + snitch_riscv_instr::FCVT_D_WU_COPIFT: begin if (IsaCfg.Xcopift) begin fpu_op = fpnew_pkg::I2F; op_select[0] = RegA; src_fmt = fpnew_pkg::FP64; dst_fmt = fpnew_pkg::FP64; - if (acc_req_q.data_op inside {riscv_instr::FCVT_D_WU_COPIFT}) op_mode = 1'b1; // unsigned + if (acc_req_q.data_op inside {snitch_riscv_instr::FCVT_D_WU_COPIFT}) op_mode = 1'b1; // unsigned end end // [Alternate] Half Precision Floating-Point - riscv_instr::FMV_H_X: begin + snitch_riscv_instr::FMV_H_X: begin fpu_op = fpnew_pkg::SGNJ; op_select[0] = AccBus; fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box @@ -2336,8 +2335,8 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP16ALT; end end - riscv_instr::FCVT_H_W, - riscv_instr::FCVT_H_WU: begin + snitch_riscv_instr::FCVT_H_W, + snitch_riscv_instr::FCVT_H_WU: begin fpu_op = fpnew_pkg::I2F; op_select[0] = AccBus; src_fmt = fpnew_pkg::FP16; @@ -2346,10 +2345,10 @@ module snitch_fp_ss import snitch_pkg::*; #( src_fmt = fpnew_pkg::FP16ALT; dst_fmt = fpnew_pkg::FP16ALT; end - if (acc_req_q.data_op inside {riscv_instr::FCVT_H_WU}) op_mode = 1'b1; // unsigned + if (acc_req_q.data_op inside {snitch_riscv_instr::FCVT_H_WU}) op_mode = 1'b1; // unsigned end // Vectorial Half Precision Floating-Point - riscv_instr::VFMV_H_X: begin + snitch_riscv_instr::VFMV_H_X: begin fpu_op = fpnew_pkg::SGNJ; op_select[0] = AccBus; fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box @@ -2361,8 +2360,8 @@ module snitch_fp_ss import snitch_pkg::*; #( end vectorial_op = 1'b1; end - riscv_instr::VFCVT_H_X, - riscv_instr::VFCVT_H_XU: begin + snitch_riscv_instr::VFCVT_H_X, + snitch_riscv_instr::VFCVT_H_XU: begin fpu_op = fpnew_pkg::I2F; op_select[0] = AccBus; src_fmt = fpnew_pkg::FP16; @@ -2374,10 +2373,10 @@ module snitch_fp_ss import snitch_pkg::*; #( int_fmt = fpnew_pkg::INT16; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVT_H_XU}) op_mode = 1'b1; // upper + if (acc_req_q.data_op inside {snitch_riscv_instr::VFCVT_H_XU}) op_mode = 1'b1; // upper end // [Alternate] Quarter Precision Floating-Point - riscv_instr::FMV_B_X: begin + snitch_riscv_instr::FMV_B_X: begin fpu_op = fpnew_pkg::SGNJ; op_select[0] = AccBus; fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box @@ -2388,16 +2387,16 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP8ALT; end end - riscv_instr::FCVT_B_W, - riscv_instr::FCVT_B_WU: begin + snitch_riscv_instr::FCVT_B_W, + snitch_riscv_instr::FCVT_B_WU: begin fpu_op = fpnew_pkg::I2F; op_select[0] = AccBus; src_fmt = fpnew_pkg::FP8; dst_fmt = fpnew_pkg::FP8; - if (acc_req_q.data_op inside {riscv_instr::FCVT_B_WU}) op_mode = 1'b1; // unsigned + if (acc_req_q.data_op inside {snitch_riscv_instr::FCVT_B_WU}) op_mode = 1'b1; // unsigned end // Vectorial Quarter Precision Floating-Point - riscv_instr::VFMV_B_X: begin + snitch_riscv_instr::VFMV_B_X: begin fpu_op = fpnew_pkg::SGNJ; op_select[0] = AccBus; fpu_rnd_mode = fpnew_pkg::RUP; // passthrough without checking nan-box @@ -2405,8 +2404,8 @@ module snitch_fp_ss import snitch_pkg::*; #( dst_fmt = fpnew_pkg::FP8; vectorial_op = 1'b1; end - riscv_instr::VFCVT_B_X, - riscv_instr::VFCVT_B_XU: begin + snitch_riscv_instr::VFCVT_B_X, + snitch_riscv_instr::VFCVT_B_XU: begin fpu_op = fpnew_pkg::I2F; op_select[0] = AccBus; src_fmt = fpnew_pkg::FP8; @@ -2414,18 +2413,18 @@ module snitch_fp_ss import snitch_pkg::*; #( int_fmt = fpnew_pkg::INT8; vectorial_op = 1'b1; set_dyn_rm = 1'b1; - if (acc_req_q.data_op inside {riscv_instr::VFCVT_B_XU}) op_mode = 1'b1; // upper + if (acc_req_q.data_op inside {snitch_riscv_instr::VFCVT_B_XU}) op_mode = 1'b1; // upper end // ------------- // Load / Store // ------------- // Single Precision Floating-Point - riscv_instr::FLW: begin + snitch_riscv_instr::FLW: begin is_load = 1'b1; op_select[2] = AccBus; use_fpu = 1'b0; end - riscv_instr::FSW: begin + snitch_riscv_instr::FSW: begin is_store = 1'b1; op_select[1] = RegB; op_select[2] = AccBus; @@ -2433,13 +2432,13 @@ module snitch_fp_ss import snitch_pkg::*; #( rd_is_fp = 1'b0; end // Double Precision Floating-Point - riscv_instr::FLD: begin + snitch_riscv_instr::FLD: begin is_load = 1'b1; op_select[2] = AccBus; ls_size = DoubleWord; use_fpu = 1'b0; end - riscv_instr::FSD: begin + snitch_riscv_instr::FSD: begin is_store = 1'b1; op_select[1] = RegB; op_select[2] = AccBus; @@ -2448,13 +2447,13 @@ module snitch_fp_ss import snitch_pkg::*; #( rd_is_fp = 1'b0; end // [Alternate] Half Precision Floating-Point - riscv_instr::FLH: begin + snitch_riscv_instr::FLH: begin is_load = 1'b1; op_select[2] = AccBus; ls_size = HalfWord; use_fpu = 1'b0; end - riscv_instr::FSH: begin + snitch_riscv_instr::FSH: begin is_store = 1'b1; op_select[1] = RegB; op_select[2] = AccBus; @@ -2463,13 +2462,13 @@ module snitch_fp_ss import snitch_pkg::*; #( rd_is_fp = 1'b0; end // [Alternate] Quarter Precision Floating-Point - riscv_instr::FLB: begin + snitch_riscv_instr::FLB: begin is_load = 1'b1; op_select[2] = AccBus; ls_size = Byte; use_fpu = 1'b0; end - riscv_instr::FSB: begin + snitch_riscv_instr::FSB: begin is_store = 1'b1; op_select[1] = RegB; op_select[2] = AccBus; @@ -2481,25 +2480,25 @@ module snitch_fp_ss import snitch_pkg::*; #( // CSR Handling // ------------- // Set or clear corresponding CSR - riscv_instr::CSRRSI: begin + snitch_riscv_instr::CSRRSI: begin use_fpu = 1'b0; rd_is_fp = 1'b0; csr_instr = 1'b1; ssr_active_d |= rs1[0]; end - riscv_instr::CSRRCI: begin + snitch_riscv_instr::CSRRCI: begin use_fpu = 1'b0; rd_is_fp = 1'b0; csr_instr = 1'b1; ssr_active_d &= ~rs1[0]; end - riscv_instr::CSRRS: begin + snitch_riscv_instr::CSRRS: begin use_fpu = 1'b0; rd_is_fp = 1'b0; csr_instr = 1'b1; sc_mask_d |= acc_req_q.data_arga[31:0]; end - riscv_instr::CSRRC: begin + snitch_riscv_instr::CSRRC: begin use_fpu = 1'b0; rd_is_fp = 1'b0; csr_instr = 1'b1; @@ -2634,8 +2633,8 @@ module snitch_fp_ss import snitch_pkg::*; #( // Tag DCA request always_comb begin - `DCA_REQRSP_ASSIGN_REQ(, dca_req, dca_req_i) - `DCA_REQRSP_ASSIGN_RSP(, dca_rsp_o, dca_rsp) + dca_req = dca_req_i; + dca_rsp_o = dca_rsp; dca_req.q.tag = '0; dca_req.q.tag.dca = 1'b1; end @@ -2662,7 +2661,7 @@ module snitch_fp_ss import snitch_pkg::*; #( if (EnableDca) begin : gen_dca_mux // Uses rotating priority. Could be changed but the problem is rr_arb_tree // doesn't really support lock-in and priority at the same time. - generic_reqrsp_mux #( + reqrsp_mux #( .NrPorts (2), .req_chan_t (fpu_req_chan_t), .rsp_chan_t (fpu_rsp_chan_t), @@ -2680,8 +2679,8 @@ module snitch_fp_ss import snitch_pkg::*; #( .idx_o () ); end else begin : gen_no_dca_mux - `FPU_REQRSP_ASSIGN_REQ(assign, fpu_req, snitch_req) - `FPU_REQRSP_ASSIGN_RSP(assign, snitch_rsp, fpu_rsp) + assign fpu_req = snitch_req; + assign snitch_rsp = fpu_rsp; `REQRSP_TIE_OFF_RSP(dca_rsp) end @@ -2691,7 +2690,7 @@ module snitch_fp_ss import snitch_pkg::*; #( snitch_fpu #( .RVF (IsaCfg.RVF), .RVD (IsaCfg.RVD), - .XF16 (IsaCfg.XF16), + .Zfh (IsaCfg.Zfh), .XF16ALT (IsaCfg.XF16ALT), .XF8 (IsaCfg.XF8), .XF8ALT (IsaCfg.XF8ALT), @@ -2770,11 +2769,10 @@ module snitch_fp_ss import snitch_pkg::*; #( // ---------------------- assign lsu_qvalid = acc_req_valid_q & (&op_ready) & (is_load | is_store) & dst_ready; - snitch_lsu #( + lsu #( .AddrWidth (AddrWidth), .DataWidth (DataWidth), - .dreq_t (dreq_t), - .drsp_t (drsp_t), + .UserWidth (UserWidth), .tag_t (logic [4:0]), .NumOutstandingMem (NumFPOutstandingMem), .NumOutstandingLoads (NumFPOutstandingLoads), @@ -2790,7 +2788,7 @@ module snitch_fp_ss import snitch_pkg::*; #( .lsu_qaddr_i (op[2][AddrWidth-1:0]), .lsu_qdata_i (op[1]), .lsu_qsize_i (ls_size), - .lsu_qamo_i (snitch_pkg::AMONone), + .lsu_qamo_i (lsu_pkg::AMONone), .lsu_qrepd_i (acc_req_repd_q), .lsu_quser_i ('0), .lsu_qvalid_i (lsu_qvalid), @@ -2836,56 +2834,56 @@ module snitch_fp_ss import snitch_pkg::*; #( // pragma translate_off // Assign the FPU trace - assign trace_port_o.source = snitch_pkg::SrcFpu; - assign trace_port_o.acc_q_hs = (acc_req_valid_q && acc_req_ready_q ); - assign trace_port_o.fpu_out_hs = (fpu_out_valid && fpu_out_ready ); - assign trace_port_o.lsu_q_hs = (lsu_qvalid && lsu_qready ); - assign trace_port_o.op_in = acc_req_q.data_op; - assign trace_port_o.rs1 = rs1; - assign trace_port_o.rs2 = rs2; - assign trace_port_o.rs3 = rs3; - assign trace_port_o.rd = rd; - assign trace_port_o.op_sel_0 = op_select[0]; - assign trace_port_o.op_sel_1 = op_select[1]; - assign trace_port_o.op_sel_2 = op_select[2]; - assign trace_port_o.src_fmt = src_fmt; - assign trace_port_o.dst_fmt = dst_fmt; - assign trace_port_o.int_fmt = int_fmt; - assign trace_port_o.acc_qdata_0 = acc_qdata[0]; - assign trace_port_o.acc_qdata_1 = acc_qdata[1]; - assign trace_port_o.acc_qdata_2 = acc_qdata[2]; - assign trace_port_o.op_0 = op[0]; - assign trace_port_o.op_1 = op[1]; - assign trace_port_o.op_2 = op[2]; - assign trace_port_o.use_fpu = use_fpu; - assign trace_port_o.fpu_in_rd = fpu_tag_in.rd; - assign trace_port_o.fpu_in_acc = fpu_tag_in.acc; - assign trace_port_o.ls_size = ls_size; - assign trace_port_o.is_load = is_load; - assign trace_port_o.is_store = is_store; - assign trace_port_o.lsu_qaddr = i_snitch_lsu.lsu_qaddr_i; - assign trace_port_o.lsu_rd = lsu_rd; - assign trace_port_o.fpu_out_acc = fpu_tag_out.acc; - assign trace_port_o.fpr_waddr = fpr_waddr[0]; - assign trace_port_o.fpr_wdata = fpr_wdata[0]; - assign trace_port_o.fpr_we = fpr_we[0]; + assign trace_o.source = snitch_pkg::SrcFpu; + assign trace_o.acc_q_hs = (acc_req_valid_q && acc_req_ready_q ); + assign trace_o.fpu_out_hs = (fpu_out_valid && fpu_out_ready ); + assign trace_o.lsu_q_hs = (lsu_qvalid && lsu_qready ); + assign trace_o.op_in = acc_req_q.data_op; + assign trace_o.rs1 = rs1; + assign trace_o.rs2 = rs2; + assign trace_o.rs3 = rs3; + assign trace_o.rd = rd; + assign trace_o.op_sel_0 = op_select[0]; + assign trace_o.op_sel_1 = op_select[1]; + assign trace_o.op_sel_2 = op_select[2]; + assign trace_o.src_fmt = src_fmt; + assign trace_o.dst_fmt = dst_fmt; + assign trace_o.int_fmt = int_fmt; + assign trace_o.acc_qdata_0 = acc_qdata[0]; + assign trace_o.acc_qdata_1 = acc_qdata[1]; + assign trace_o.acc_qdata_2 = acc_qdata[2]; + assign trace_o.op_0 = op[0]; + assign trace_o.op_1 = op[1]; + assign trace_o.op_2 = op[2]; + assign trace_o.use_fpu = use_fpu; + assign trace_o.fpu_in_rd = fpu_tag_in.rd; + assign trace_o.fpu_in_acc = fpu_tag_in.acc; + assign trace_o.ls_size = ls_size; + assign trace_o.is_load = is_load; + assign trace_o.is_store = is_store; + assign trace_o.lsu_qaddr = i_snitch_lsu.lsu_qaddr_i; + assign trace_o.lsu_rd = lsu_rd; + assign trace_o.fpu_out_acc = fpu_tag_out.acc; + assign trace_o.fpr_waddr = fpr_waddr[0]; + assign trace_o.fpr_wdata = fpr_wdata[0]; + assign trace_o.fpr_we = fpr_we[0]; // Assign the DCA tracer - assign dca_trace_port_o.source = snitch_pkg::SrcDca; - assign dca_trace_port_o.req_hs = (dca_req_i.q_valid && dca_rsp_o.q_ready); - assign dca_trace_port_o.rsp_hs = (dca_rsp_o.p_valid && dca_req_i.p_ready); - assign dca_trace_port_o.operand0 = dca_req_i.q.operands[0]; - assign dca_trace_port_o.operand1 = dca_req_i.q.operands[1]; - assign dca_trace_port_o.operand2 = dca_req_i.q.operands[2]; - assign dca_trace_port_o.rnd_mode = dca_req_i.q.rnd_mode; - assign dca_trace_port_o.op = dca_req_i.q.op; - assign dca_trace_port_o.op_mod = dca_req_i.q.op_mod; - assign dca_trace_port_o.src_fmt = dca_req_i.q.src_fmt; - assign dca_trace_port_o.dst_fmt = dca_req_i.q.dst_fmt; - assign dca_trace_port_o.int_fmt = dca_req_i.q.int_fmt; - assign dca_trace_port_o.vectorial_op = dca_req_i.q.vectorial_op; - assign dca_trace_port_o.status = dca_rsp_o.p.status; - assign dca_trace_port_o.result = dca_rsp_o.p.result; + assign dca_trace_o.source = snitch_pkg::SrcDca; + assign dca_trace_o.req_hs = (dca_req_i.q_valid && dca_rsp_o.q_ready); + assign dca_trace_o.rsp_hs = (dca_rsp_o.p_valid && dca_req_i.p_ready); + assign dca_trace_o.operand0 = dca_req_i.q.operands[0]; + assign dca_trace_o.operand1 = dca_req_i.q.operands[1]; + assign dca_trace_o.operand2 = dca_req_i.q.operands[2]; + assign dca_trace_o.rnd_mode = dca_req_i.q.rnd_mode; + assign dca_trace_o.op = dca_req_i.q.op; + assign dca_trace_o.op_mod = dca_req_i.q.op_mod; + assign dca_trace_o.src_fmt = dca_req_i.q.src_fmt; + assign dca_trace_o.dst_fmt = dca_req_i.q.dst_fmt; + assign dca_trace_o.int_fmt = dca_req_i.q.int_fmt; + assign dca_trace_o.vectorial_op = dca_req_i.q.vectorial_op; + assign dca_trace_o.status = dca_rsp_o.p.status; + assign dca_trace_o.result = dca_rsp_o.p.result; // pragma translate_on // ---------- diff --git a/hw/snitch_fp_ss/src/snitch_fpu.sv b/hw/snitch_fp_ss/src/snitch_fpu.sv index 70d9eef323..b0c1b26325 100644 --- a/hw/snitch_fp_ss/src/snitch_fpu.sv +++ b/hw/snitch_fp_ss/src/snitch_fpu.sv @@ -9,7 +9,7 @@ module snitch_fpu import snitch_pkg::*; #( parameter fpnew_pkg::fpu_implementation_t FpuImplementation = '0, parameter bit RVF = 1, parameter bit RVD = 1, - parameter bit XF16 = 0, + parameter bit Zfh = 0, parameter bit XF16ALT = 0, parameter bit XF8 = 0, parameter bit XF8ALT = 0, @@ -35,7 +35,7 @@ module snitch_fpu import snitch_pkg::*; #( fpu_req_t fpu_req; fpu_rsp_t fpu_rsp; - generic_reqrsp_cut #( + reqrsp_cut #( .req_chan_t(fpu_req_chan_t), .rsp_chan_t(fpu_rsp_chan_t), .BypassReq (!RegisterFpuReq), @@ -54,8 +54,8 @@ module snitch_fpu import snitch_pkg::*; #( Width: fpnew_pkg::maximum(FLEN, 32), EnableVectors: XFVEC, EnableNanBox: 1'b1, - FpFmtMask: {RVF, RVD, XF16, XF8, XF16ALT, XF8ALT, 1'b0, 1'b0, 1'b0}, - IntFmtMask: {XFVEC && (XF8 || XF8ALT), XFVEC && (XF16 || XF16ALT), 1'b1, 1'b0}, + FpFmtMask: {RVF, RVD, Zfh, XF8, XF16ALT, XF8ALT, 1'b0, 1'b0, 1'b0}, + IntFmtMask: {XFVEC && (XF8 || XF8ALT), XFVEC && (Zfh || XF16ALT), 1'b1, 1'b0}, MxFpFmtMask: '0, MxIntFmtMask: '0 }; diff --git a/hw/snitch_fp_ss/src/snitch_sequencer.sv b/hw/snitch_fp_ss/src/snitch_sequencer.sv index 8265812aab..a88b410860 100644 --- a/hw/snitch_fp_ss/src/snitch_sequencer.sv +++ b/hw/snitch_fp_ss/src/snitch_sequencer.sv @@ -19,7 +19,7 @@ module snitch_sequencer import snitch_pkg::*; #( input logic clk_i, input logic rst_i, // pragma translate_off - output fpu_sequencer_trace_port_t trace_port_o, + output fpu_sequencer_trace_t trace_o, // pragma translate_on input acc_addr_e inp_qaddr_i, input logic [ 4:0] inp_qid_i, @@ -131,8 +131,8 @@ module snitch_sequencer import snitch_pkg::*; #( inst_path_sel = Buffer; unique casez (inp_qdata_op_i) - riscv_instr::FREP_O, - riscv_instr::IREP: begin + snitch_riscv_instr::FREP_O, + snitch_riscv_instr::IREP: begin inst_path_sel = Frep; end @@ -141,108 +141,108 @@ module snitch_sequencer import snitch_pkg::*; #( // bypass the ring buffer. // float to int - riscv_instr::FLE_S, - riscv_instr::FLT_S, - riscv_instr::FEQ_S, - riscv_instr::FCLASS_S, - riscv_instr::FCVT_W_S, - riscv_instr::FCVT_WU_S, - // riscv_instr::FMV_X_W, - riscv_instr::VFEQ_S, - riscv_instr::VFEQ_R_S, - riscv_instr::VFNE_S, - riscv_instr::VFNE_R_S, - riscv_instr::VFLT_S, - riscv_instr::VFLT_R_S, - riscv_instr::VFGE_S, - riscv_instr::VFGE_R_S, - riscv_instr::VFLE_S, - riscv_instr::VFLE_R_S, - riscv_instr::VFGT_S, - riscv_instr::VFGT_R_S, - riscv_instr::VFCLASS_S, - riscv_instr::FLE_D, - // riscv_instr::FLT_D, - riscv_instr::FEQ_D, - riscv_instr::FCLASS_D, - // riscv_instr::FCVT_W_D, - // riscv_instr::FCVT_WU_D, - riscv_instr::FMV_X_D, - riscv_instr::FLE_H, - riscv_instr::FLT_H, - riscv_instr::FEQ_H, - riscv_instr::FCLASS_H, - riscv_instr::FCVT_W_H, - riscv_instr::FCVT_WU_H, - riscv_instr::FMV_X_H, - riscv_instr::VFEQ_H, - riscv_instr::VFEQ_R_H, - riscv_instr::VFNE_H, - riscv_instr::VFNE_R_H, - riscv_instr::VFLT_H, - riscv_instr::VFLT_R_H, - riscv_instr::VFGE_H, - riscv_instr::VFGE_R_H, - riscv_instr::VFLE_H, - riscv_instr::VFLE_R_H, - riscv_instr::VFGT_H, - riscv_instr::VFGT_R_H, - riscv_instr::VFCLASS_H, - riscv_instr::VFMV_X_H, - riscv_instr::VFCVT_X_H, - riscv_instr::VFCVT_XU_H, - riscv_instr::FLE_B, - riscv_instr::FLT_B, - riscv_instr::FEQ_B, - riscv_instr::FCLASS_B, - riscv_instr::FCVT_W_B, - riscv_instr::FCVT_WU_B, - riscv_instr::FMV_X_B, - riscv_instr::VFEQ_B, - riscv_instr::VFEQ_R_B, - riscv_instr::VFNE_B, - riscv_instr::VFNE_R_B, - riscv_instr::VFLT_B, - riscv_instr::VFLT_R_B, - riscv_instr::VFGE_B, - riscv_instr::VFGE_R_B, - riscv_instr::VFLE_B, - riscv_instr::VFLE_R_B, - riscv_instr::VFGT_B, - riscv_instr::VFGT_R_B, - riscv_instr::VFCLASS_B, - riscv_instr::VFMV_X_B, - riscv_instr::VFCVT_X_B, - riscv_instr::VFCVT_XU_B, + snitch_riscv_instr::FLE_S, + snitch_riscv_instr::FLT_S, + snitch_riscv_instr::FEQ_S, + snitch_riscv_instr::FCLASS_S, + snitch_riscv_instr::FCVT_W_S, + snitch_riscv_instr::FCVT_WU_S, + // snitch_riscv_instr::FMV_X_W, + snitch_riscv_instr::VFEQ_S, + snitch_riscv_instr::VFEQ_R_S, + snitch_riscv_instr::VFNE_S, + snitch_riscv_instr::VFNE_R_S, + snitch_riscv_instr::VFLT_S, + snitch_riscv_instr::VFLT_R_S, + snitch_riscv_instr::VFGE_S, + snitch_riscv_instr::VFGE_R_S, + snitch_riscv_instr::VFLE_S, + snitch_riscv_instr::VFLE_R_S, + snitch_riscv_instr::VFGT_S, + snitch_riscv_instr::VFGT_R_S, + snitch_riscv_instr::VFCLASS_S, + snitch_riscv_instr::FLE_D, + // snitch_riscv_instr::FLT_D, + snitch_riscv_instr::FEQ_D, + snitch_riscv_instr::FCLASS_D, + // snitch_riscv_instr::FCVT_W_D, + // snitch_riscv_instr::FCVT_WU_D, + snitch_riscv_instr::FMV_X_D, + snitch_riscv_instr::FLE_H, + snitch_riscv_instr::FLT_H, + snitch_riscv_instr::FEQ_H, + snitch_riscv_instr::FCLASS_H, + snitch_riscv_instr::FCVT_W_H, + snitch_riscv_instr::FCVT_WU_H, + snitch_riscv_instr::FMV_X_H, + snitch_riscv_instr::VFEQ_H, + snitch_riscv_instr::VFEQ_R_H, + snitch_riscv_instr::VFNE_H, + snitch_riscv_instr::VFNE_R_H, + snitch_riscv_instr::VFLT_H, + snitch_riscv_instr::VFLT_R_H, + snitch_riscv_instr::VFGE_H, + snitch_riscv_instr::VFGE_R_H, + snitch_riscv_instr::VFLE_H, + snitch_riscv_instr::VFLE_R_H, + snitch_riscv_instr::VFGT_H, + snitch_riscv_instr::VFGT_R_H, + snitch_riscv_instr::VFCLASS_H, + snitch_riscv_instr::VFMV_X_H, + snitch_riscv_instr::VFCVT_X_H, + snitch_riscv_instr::VFCVT_XU_H, + snitch_riscv_instr::FLE_B, + snitch_riscv_instr::FLT_B, + snitch_riscv_instr::FEQ_B, + snitch_riscv_instr::FCLASS_B, + snitch_riscv_instr::FCVT_W_B, + snitch_riscv_instr::FCVT_WU_B, + snitch_riscv_instr::FMV_X_B, + snitch_riscv_instr::VFEQ_B, + snitch_riscv_instr::VFEQ_R_B, + snitch_riscv_instr::VFNE_B, + snitch_riscv_instr::VFNE_R_B, + snitch_riscv_instr::VFLT_B, + snitch_riscv_instr::VFLT_R_B, + snitch_riscv_instr::VFGE_B, + snitch_riscv_instr::VFGE_R_B, + snitch_riscv_instr::VFLE_B, + snitch_riscv_instr::VFLE_R_B, + snitch_riscv_instr::VFGT_B, + snitch_riscv_instr::VFGT_R_B, + snitch_riscv_instr::VFCLASS_B, + snitch_riscv_instr::VFMV_X_B, + snitch_riscv_instr::VFCVT_X_B, + snitch_riscv_instr::VFCVT_XU_B, // int to float - // riscv_instr::FMV_W_X, - riscv_instr::FCVT_S_W, - riscv_instr::FCVT_S_WU, - // riscv_instr::FCVT_D_W, - // riscv_instr::FCVT_D_WU, - riscv_instr::FMV_H_X, - riscv_instr::FCVT_H_W, - riscv_instr::FCVT_H_WU, - riscv_instr::VFMV_H_X, - riscv_instr::VFCVT_H_X, - riscv_instr::VFCVT_H_XU, - riscv_instr::FMV_B_X, - riscv_instr::FCVT_B_W, - riscv_instr::FCVT_B_WU, - riscv_instr::VFMV_B_X, - riscv_instr::VFCVT_B_X, - riscv_instr::VFCVT_B_XU, - riscv_instr::IMV_X_W, - riscv_instr::IMV_W_X, + // snitch_riscv_instr::FMV_W_X, + snitch_riscv_instr::FCVT_S_W, + snitch_riscv_instr::FCVT_S_WU, + // snitch_riscv_instr::FCVT_D_W, + // snitch_riscv_instr::FCVT_D_WU, + snitch_riscv_instr::FMV_H_X, + snitch_riscv_instr::FCVT_H_W, + snitch_riscv_instr::FCVT_H_WU, + snitch_riscv_instr::VFMV_H_X, + snitch_riscv_instr::VFCVT_H_X, + snitch_riscv_instr::VFCVT_H_XU, + snitch_riscv_instr::FMV_B_X, + snitch_riscv_instr::FCVT_B_W, + snitch_riscv_instr::FCVT_B_WU, + snitch_riscv_instr::VFMV_B_X, + snitch_riscv_instr::VFCVT_B_X, + snitch_riscv_instr::VFCVT_B_XU, + snitch_riscv_instr::IMV_X_W, + snitch_riscv_instr::IMV_W_X, // CSR accesses - riscv_instr::CSRRW, - riscv_instr::CSRRS, - riscv_instr::CSRRC, - riscv_instr::CSRRWI, - riscv_instr::CSRRSI, - riscv_instr::CSRRCI: begin + snitch_riscv_instr::CSRRW, + snitch_riscv_instr::CSRRS, + snitch_riscv_instr::CSRRC, + snitch_riscv_instr::CSRRWI, + snitch_riscv_instr::CSRRSI, + snitch_riscv_instr::CSRRCI: begin inst_path_sel = Direct; end @@ -692,12 +692,12 @@ module snitch_sequencer import snitch_pkg::*; #( //////////// // pragma translate_off - assign trace_port_o.source = snitch_pkg::SrcFpuSeq; - assign trace_port_o.cbuf_push = core_frep_valid && core_frep_ready; - assign trace_port_o.max_inst = inp_qdata_op_i[20+:DepthBits] - 1; - assign trace_port_o.max_iter = inp_qdata_arga_i[LoopIterBits-1:0]; - assign trace_port_o.stg_max = inp_qdata_op_i[14:12]; - assign trace_port_o.stg_mask = inp_qdata_op_i[11:8]; + assign trace_o.source = snitch_pkg::SrcFpuSeq; + assign trace_o.cbuf_push = core_frep_valid && core_frep_ready; + assign trace_o.max_inst = inp_qdata_op_i[20+:DepthBits] - 1; + assign trace_o.max_iter = inp_qdata_arga_i[LoopIterBits-1:0]; + assign trace_o.stg_max = inp_qdata_op_i[14:12]; + assign trace_o.stg_mask = inp_qdata_op_i[11:8]; // pragma translate_on //////////////// diff --git a/hw/snitch_ipu/src/snitch_ipu.sv b/hw/snitch_ipu/src/snitch_ipu.sv index add78e98f5..2db129865d 100644 --- a/hw/snitch_ipu/src/snitch_ipu.sv +++ b/hw/snitch_ipu/src/snitch_ipu.sv @@ -45,10 +45,10 @@ module snitch_ipu import snitch_pkg::*; #( acc_rsp_o.p.error = 1'b0; illegal_instruction = 1'b0; unique casez (acc_req_i.q.data_op) - riscv_instr::MUL, - riscv_instr::MULH, - riscv_instr::MULHSU, - riscv_instr::MULHU: begin + snitch_riscv_instr::MUL, + snitch_riscv_instr::MULH, + snitch_riscv_instr::MULHSU, + snitch_riscv_instr::MULHU: begin if (Xpulpv2) begin dsp_valid_op = acc_req_i.q_valid; acc_rsp_o.q_ready = dsp_ready_op; @@ -57,162 +57,162 @@ module snitch_ipu import snitch_pkg::*; #( acc_rsp_o.q_ready = mul_ready_op; end end - riscv_instr::DIV, - riscv_instr::DIVU, - riscv_instr::REM, - riscv_instr::REMU: begin + snitch_riscv_instr::DIV, + snitch_riscv_instr::DIVU, + snitch_riscv_instr::REM, + snitch_riscv_instr::REMU: begin div_valid_op = acc_req_i.q_valid; acc_rsp_o.q_ready = div_ready_op; end - riscv_instr::P_ABS, // Xpulpv2: p.abs - riscv_instr::P_SLET, // Xpulpv2: p.slet - riscv_instr::P_SLETU, // Xpulpv2: p.sletu - riscv_instr::P_MIN, // Xpulpv2: p.min - riscv_instr::P_MINU, // Xpulpv2: p.minu - riscv_instr::P_MAX, // Xpulpv2: p.max - riscv_instr::P_MAXU, // Xpulpv2: p.maxu - riscv_instr::P_EXTHS, // Xpulpv2: p.exths - riscv_instr::P_EXTHZ, // Xpulpv2: p.exthz - riscv_instr::P_EXTBS, // Xpulpv2: p.extbs - riscv_instr::P_EXTBZ, // Xpulpv2: p.extbz - riscv_instr::P_CLIP, // Xpulpv2: p.clip - riscv_instr::P_CLIPU, // Xpulpv2: p.clipu - riscv_instr::P_CLIPR, // Xpulpv2: p.clipr - riscv_instr::P_CLIPUR, // Xpulpv2: p.clipur - riscv_instr::P_MAC, // Xpulpv2: p.mac - riscv_instr::P_MSU, // Xpulpv2: p.msu - riscv_instr::PV_ADD_H, // Xpulpv2: pv.add.h - riscv_instr::PV_ADD_SC_H, // Xpulpv2: pv.add.sc.h - riscv_instr::PV_ADD_SCI_H, // Xpulpv2: pv.add.sci.h - riscv_instr::PV_ADD_B, // Xpulpv2: pv.add.b - riscv_instr::PV_ADD_SC_B, // Xpulpv2: pv.add.sc.b - riscv_instr::PV_ADD_SCI_B, // Xpulpv2: pv.add.sci.b - riscv_instr::PV_SUB_H, // Xpulpv2: pv.sub.h - riscv_instr::PV_SUB_SC_H, // Xpulpv2: pv.sub.sc.h - riscv_instr::PV_SUB_SCI_H, // Xpulpv2: pv.sub.sci.h - riscv_instr::PV_SUB_B, // Xpulpv2: pv.sub.b - riscv_instr::PV_SUB_SC_B, // Xpulpv2: pv.sub.sc.b - riscv_instr::PV_SUB_SCI_B, // Xpulpv2: pv.sub.sci.b - riscv_instr::PV_AVG_H, // Xpulpv2: pv.avg.h - riscv_instr::PV_AVG_SC_H, // Xpulpv2: pv.avg.sc.h - riscv_instr::PV_AVG_SCI_H, // Xpulpv2: pv.avg.sci.h - riscv_instr::PV_AVG_B, // Xpulpv2: pv.avg.b - riscv_instr::PV_AVG_SC_B, // Xpulpv2: pv.avg.sc.b - riscv_instr::PV_AVG_SCI_B, // Xpulpv2: pv.avg.sci.b - riscv_instr::PV_AVGU_H, // Xpulpv2: pv.avgu.h - riscv_instr::PV_AVGU_SC_H, // Xpulpv2: pv.avgu.sc.h - riscv_instr::PV_AVGU_SCI_H, // Xpulpv2: pv.avgu.sci.h - riscv_instr::PV_AVGU_B, // Xpulpv2: pv.avgu.b - riscv_instr::PV_AVGU_SC_B, // Xpulpv2: pv.avgu.sc.b - riscv_instr::PV_AVGU_SCI_B, // Xpulpv2: pv.avgu.sci.b - riscv_instr::PV_MIN_H, // Xpulpv2: pv.min.h - riscv_instr::PV_MIN_SC_H, // Xpulpv2: pv.min.sc.h - riscv_instr::PV_MIN_SCI_H, // Xpulpv2: pv.min.sci.h - riscv_instr::PV_MIN_B, // Xpulpv2: pv.min.b - riscv_instr::PV_MIN_SC_B, // Xpulpv2: pv.min.sc.b - riscv_instr::PV_MIN_SCI_B, // Xpulpv2: pv.min.sci.b - riscv_instr::PV_MINU_H, // Xpulpv2: pv.minu.h - riscv_instr::PV_MINU_SC_H, // Xpulpv2: pv.minu.sc.h - riscv_instr::PV_MINU_SCI_H, // Xpulpv2: pv.minu.sci.h - riscv_instr::PV_MINU_B, // Xpulpv2: pv.minu.b - riscv_instr::PV_MINU_SC_B, // Xpulpv2: pv.minu.sc.b - riscv_instr::PV_MINU_SCI_B, // Xpulpv2: pv.minu.sci.b - riscv_instr::PV_MAX_H, // Xpulpv2: pv.max.h - riscv_instr::PV_MAX_SC_H, // Xpulpv2: pv.max.sc.h - riscv_instr::PV_MAX_SCI_H, // Xpulpv2: pv.max.sci.h - riscv_instr::PV_MAX_B, // Xpulpv2: pv.max.b - riscv_instr::PV_MAX_SC_B, // Xpulpv2: pv.max.sc.b - riscv_instr::PV_MAX_SCI_B, // Xpulpv2: pv.max.sci.b - riscv_instr::PV_MAXU_H, // Xpulpv2: pv.maxu.h - riscv_instr::PV_MAXU_SC_H, // Xpulpv2: pv.maxu.sc.h - riscv_instr::PV_MAXU_SCI_H, // Xpulpv2: pv.maxu.sci.h - riscv_instr::PV_MAXU_B, // Xpulpv2: pv.maxu.b - riscv_instr::PV_MAXU_SC_B, // Xpulpv2: pv.maxu.sc.b - riscv_instr::PV_MAXU_SCI_B, // Xpulpv2: pv.maxu.sci.b - riscv_instr::PV_SRL_H, // Xpulpv2: pv.srl.h - riscv_instr::PV_SRL_SC_H, // Xpulpv2: pv.srl.sc.h - riscv_instr::PV_SRL_SCI_H, // Xpulpv2: pv.srl.sci.h - riscv_instr::PV_SRL_B, // Xpulpv2: pv.srl.b - riscv_instr::PV_SRL_SC_B, // Xpulpv2: pv.srl.sc.b - riscv_instr::PV_SRL_SCI_B, // Xpulpv2: pv.srl.sci.b - riscv_instr::PV_SRA_H, // Xpulpv2: pv.sra.h - riscv_instr::PV_SRA_SC_H, // Xpulpv2: pv.sra.sc.h - riscv_instr::PV_SRA_SCI_H, // Xpulpv2: pv.sra.sci.h - riscv_instr::PV_SRA_B, // Xpulpv2: pv.sra.b - riscv_instr::PV_SRA_SC_B, // Xpulpv2: pv.sra.sc.b - riscv_instr::PV_SRA_SCI_B, // Xpulpv2: pv.sra.sci.b - riscv_instr::PV_SLL_H, // Xpulpv2: pv.sll.h - riscv_instr::PV_SLL_SC_H, // Xpulpv2: pv.sll.sc.h - riscv_instr::PV_SLL_SCI_H, // Xpulpv2: pv.sll.sci.h - riscv_instr::PV_SLL_B, // Xpulpv2: pv.sll.b - riscv_instr::PV_SLL_SC_B, // Xpulpv2: pv.sll.sc.b - riscv_instr::PV_SLL_SCI_B, // Xpulpv2: pv.sll.sci.b - riscv_instr::PV_OR_H, // Xpulpv2: pv.or.h - riscv_instr::PV_OR_SC_H, // Xpulpv2: pv.or.sc.h - riscv_instr::PV_OR_SCI_H, // Xpulpv2: pv.or.sci.h - riscv_instr::PV_OR_B, // Xpulpv2: pv.or.b - riscv_instr::PV_OR_SC_B, // Xpulpv2: pv.or.sc.b - riscv_instr::PV_OR_SCI_B, // Xpulpv2: pv.or.sci.b - riscv_instr::PV_XOR_H, // Xpulpv2: pv.xor.h - riscv_instr::PV_XOR_SC_H, // Xpulpv2: pv.xor.sc.h - riscv_instr::PV_XOR_SCI_H, // Xpulpv2: pv.xor.sci.h - riscv_instr::PV_XOR_B, // Xpulpv2: pv.xor.b - riscv_instr::PV_XOR_SC_B, // Xpulpv2: pv.xor.sc.b - riscv_instr::PV_XOR_SCI_B, // Xpulpv2: pv.xor.sci.b - riscv_instr::PV_AND_H, // Xpulpv2: pv.and.h - riscv_instr::PV_AND_SC_H, // Xpulpv2: pv.and.sc.h - riscv_instr::PV_AND_SCI_H, // Xpulpv2: pv.and.sci.h - riscv_instr::PV_AND_B, // Xpulpv2: pv.and.b - riscv_instr::PV_AND_SC_B, // Xpulpv2: pv.and.sc.b - riscv_instr::PV_AND_SCI_B, // Xpulpv2: pv.and.sci.b - riscv_instr::PV_ABS_H, // Xpulpv2: pv.abs.h - riscv_instr::PV_ABS_B, // Xpulpv2: pv.abs.b - riscv_instr::PV_EXTRACT_H, // Xpulpv2: pv.extract.h - riscv_instr::PV_EXTRACT_B, // Xpulpv2: pv.extract.b - riscv_instr::PV_EXTRACTU_H, // Xpulpv2: pv.extractu.h - riscv_instr::PV_EXTRACTU_B, // Xpulpv2: pv.extractu.b - riscv_instr::PV_INSERT_H, // Xpulpv2: pv.insert.h - riscv_instr::PV_INSERT_B, // Xpulpv2: pv.insert.b - riscv_instr::PV_DOTUP_H, // Xpulpv2: pv.dotup.h - riscv_instr::PV_DOTUP_SC_H, // Xpulpv2: pv.dotup.sc.h - riscv_instr::PV_DOTUP_SCI_H, // Xpulpv2: pv.dotup.sci.h - riscv_instr::PV_DOTUP_B, // Xpulpv2: pv.dotup.b - riscv_instr::PV_DOTUP_SC_B, // Xpulpv2: pv.dotup.sc.b - riscv_instr::PV_DOTUP_SCI_B, // Xpulpv2: pv.dotup.sci.b - riscv_instr::PV_DOTUSP_H, // Xpulpv2: pv.dotusp.h - riscv_instr::PV_DOTUSP_SC_H, // Xpulpv2: pv.dotusp.sc.h - riscv_instr::PV_DOTUSP_SCI_H, // Xpulpv2: pv.dotusp.sci.h - riscv_instr::PV_DOTUSP_B, // Xpulpv2: pv.dotusp.b - riscv_instr::PV_DOTUSP_SC_B, // Xpulpv2: pv.dotusp.sc.b - riscv_instr::PV_DOTUSP_SCI_B, // Xpulpv2: pv.dotusp.sci.b - riscv_instr::PV_DOTSP_H, // Xpulpv2: pv.dotsp.h - riscv_instr::PV_DOTSP_SC_H, // Xpulpv2: pv.dotsp.sc.h - riscv_instr::PV_DOTSP_SCI_H, // Xpulpv2: pv.dotsp.sci.h - riscv_instr::PV_DOTSP_B, // Xpulpv2: pv.dotsp.b - riscv_instr::PV_DOTSP_SC_B, // Xpulpv2: pv.dotsp.sc.b - riscv_instr::PV_DOTSP_SCI_B, // Xpulpv2: pv.dotsp.sci.b - riscv_instr::PV_SDOTUP_H, // Xpulpv2: pv.sdotup.h - riscv_instr::PV_SDOTUP_SC_H, // Xpulpv2: pv.sdotup.sc.h - riscv_instr::PV_SDOTUP_SCI_H, // Xpulpv2: pv.sdotup.sci.h - riscv_instr::PV_SDOTUP_B, // Xpulpv2: pv.sdotup.b - riscv_instr::PV_SDOTUP_SC_B, // Xpulpv2: pv.sdotup.sc.b - riscv_instr::PV_SDOTUP_SCI_B, // Xpulpv2: pv.sdotup.sci.b - riscv_instr::PV_SDOTUSP_H, // Xpulpv2: pv.sdotusp.h - riscv_instr::PV_SDOTUSP_SC_H, // Xpulpv2: pv.sdotusp.sc.h - riscv_instr::PV_SDOTUSP_SCI_H, // Xpulpv2: pv.sdotusp.sci.h - riscv_instr::PV_SDOTUSP_B, // Xpulpv2: pv.sdotusp.b - riscv_instr::PV_SDOTUSP_SC_B, // Xpulpv2: pv.sdotusp.sc.b - riscv_instr::PV_SDOTUSP_SCI_B, // Xpulpv2: pv.sdotusp.sci.b - riscv_instr::PV_SDOTSP_H, // Xpulpv2: pv.sdotsp.h - riscv_instr::PV_SDOTSP_SC_H, // Xpulpv2: pv.sdotsp.sc.h - riscv_instr::PV_SDOTSP_SCI_H, // Xpulpv2: pv.sdotsp.sci.h - riscv_instr::PV_SDOTSP_B, // Xpulpv2: pv.sdotsp.b - riscv_instr::PV_SDOTSP_SC_B, // Xpulpv2: pv.sdotsp.sc.b - riscv_instr::PV_SDOTSP_SCI_B, // Xpulpv2: pv.sdotsp.sci.b - riscv_instr::PV_SHUFFLE2_H, // Xpulpv2: pv.shuffle2.h - riscv_instr::PV_SHUFFLE2_B, // Xpulpv2: pv.shuffle2.b - riscv_instr::PV_PACK, // Xpulpv2: pv.pack - riscv_instr::PV_PACK_H: begin // Xpulpv2: pv.pack.h + snitch_riscv_instr::P_ABS, // Xpulpv2: p.abs + snitch_riscv_instr::P_SLET, // Xpulpv2: p.slet + snitch_riscv_instr::P_SLETU, // Xpulpv2: p.sletu + snitch_riscv_instr::P_MIN, // Xpulpv2: p.min + snitch_riscv_instr::P_MINU, // Xpulpv2: p.minu + snitch_riscv_instr::P_MAX, // Xpulpv2: p.max + snitch_riscv_instr::P_MAXU, // Xpulpv2: p.maxu + snitch_riscv_instr::P_EXTHS, // Xpulpv2: p.exths + snitch_riscv_instr::P_EXTHZ, // Xpulpv2: p.exthz + snitch_riscv_instr::P_EXTBS, // Xpulpv2: p.extbs + snitch_riscv_instr::P_EXTBZ, // Xpulpv2: p.extbz + snitch_riscv_instr::P_CLIP, // Xpulpv2: p.clip + snitch_riscv_instr::P_CLIPU, // Xpulpv2: p.clipu + snitch_riscv_instr::P_CLIPR, // Xpulpv2: p.clipr + snitch_riscv_instr::P_CLIPUR, // Xpulpv2: p.clipur + snitch_riscv_instr::P_MAC, // Xpulpv2: p.mac + snitch_riscv_instr::P_MSU, // Xpulpv2: p.msu + snitch_riscv_instr::PV_ADD_H, // Xpulpv2: pv.add.h + snitch_riscv_instr::PV_ADD_SC_H, // Xpulpv2: pv.add.sc.h + snitch_riscv_instr::PV_ADD_SCI_H, // Xpulpv2: pv.add.sci.h + snitch_riscv_instr::PV_ADD_B, // Xpulpv2: pv.add.b + snitch_riscv_instr::PV_ADD_SC_B, // Xpulpv2: pv.add.sc.b + snitch_riscv_instr::PV_ADD_SCI_B, // Xpulpv2: pv.add.sci.b + snitch_riscv_instr::PV_SUB_H, // Xpulpv2: pv.sub.h + snitch_riscv_instr::PV_SUB_SC_H, // Xpulpv2: pv.sub.sc.h + snitch_riscv_instr::PV_SUB_SCI_H, // Xpulpv2: pv.sub.sci.h + snitch_riscv_instr::PV_SUB_B, // Xpulpv2: pv.sub.b + snitch_riscv_instr::PV_SUB_SC_B, // Xpulpv2: pv.sub.sc.b + snitch_riscv_instr::PV_SUB_SCI_B, // Xpulpv2: pv.sub.sci.b + snitch_riscv_instr::PV_AVG_H, // Xpulpv2: pv.avg.h + snitch_riscv_instr::PV_AVG_SC_H, // Xpulpv2: pv.avg.sc.h + snitch_riscv_instr::PV_AVG_SCI_H, // Xpulpv2: pv.avg.sci.h + snitch_riscv_instr::PV_AVG_B, // Xpulpv2: pv.avg.b + snitch_riscv_instr::PV_AVG_SC_B, // Xpulpv2: pv.avg.sc.b + snitch_riscv_instr::PV_AVG_SCI_B, // Xpulpv2: pv.avg.sci.b + snitch_riscv_instr::PV_AVGU_H, // Xpulpv2: pv.avgu.h + snitch_riscv_instr::PV_AVGU_SC_H, // Xpulpv2: pv.avgu.sc.h + snitch_riscv_instr::PV_AVGU_SCI_H, // Xpulpv2: pv.avgu.sci.h + snitch_riscv_instr::PV_AVGU_B, // Xpulpv2: pv.avgu.b + snitch_riscv_instr::PV_AVGU_SC_B, // Xpulpv2: pv.avgu.sc.b + snitch_riscv_instr::PV_AVGU_SCI_B, // Xpulpv2: pv.avgu.sci.b + snitch_riscv_instr::PV_MIN_H, // Xpulpv2: pv.min.h + snitch_riscv_instr::PV_MIN_SC_H, // Xpulpv2: pv.min.sc.h + snitch_riscv_instr::PV_MIN_SCI_H, // Xpulpv2: pv.min.sci.h + snitch_riscv_instr::PV_MIN_B, // Xpulpv2: pv.min.b + snitch_riscv_instr::PV_MIN_SC_B, // Xpulpv2: pv.min.sc.b + snitch_riscv_instr::PV_MIN_SCI_B, // Xpulpv2: pv.min.sci.b + snitch_riscv_instr::PV_MINU_H, // Xpulpv2: pv.minu.h + snitch_riscv_instr::PV_MINU_SC_H, // Xpulpv2: pv.minu.sc.h + snitch_riscv_instr::PV_MINU_SCI_H, // Xpulpv2: pv.minu.sci.h + snitch_riscv_instr::PV_MINU_B, // Xpulpv2: pv.minu.b + snitch_riscv_instr::PV_MINU_SC_B, // Xpulpv2: pv.minu.sc.b + snitch_riscv_instr::PV_MINU_SCI_B, // Xpulpv2: pv.minu.sci.b + snitch_riscv_instr::PV_MAX_H, // Xpulpv2: pv.max.h + snitch_riscv_instr::PV_MAX_SC_H, // Xpulpv2: pv.max.sc.h + snitch_riscv_instr::PV_MAX_SCI_H, // Xpulpv2: pv.max.sci.h + snitch_riscv_instr::PV_MAX_B, // Xpulpv2: pv.max.b + snitch_riscv_instr::PV_MAX_SC_B, // Xpulpv2: pv.max.sc.b + snitch_riscv_instr::PV_MAX_SCI_B, // Xpulpv2: pv.max.sci.b + snitch_riscv_instr::PV_MAXU_H, // Xpulpv2: pv.maxu.h + snitch_riscv_instr::PV_MAXU_SC_H, // Xpulpv2: pv.maxu.sc.h + snitch_riscv_instr::PV_MAXU_SCI_H, // Xpulpv2: pv.maxu.sci.h + snitch_riscv_instr::PV_MAXU_B, // Xpulpv2: pv.maxu.b + snitch_riscv_instr::PV_MAXU_SC_B, // Xpulpv2: pv.maxu.sc.b + snitch_riscv_instr::PV_MAXU_SCI_B, // Xpulpv2: pv.maxu.sci.b + snitch_riscv_instr::PV_SRL_H, // Xpulpv2: pv.srl.h + snitch_riscv_instr::PV_SRL_SC_H, // Xpulpv2: pv.srl.sc.h + snitch_riscv_instr::PV_SRL_SCI_H, // Xpulpv2: pv.srl.sci.h + snitch_riscv_instr::PV_SRL_B, // Xpulpv2: pv.srl.b + snitch_riscv_instr::PV_SRL_SC_B, // Xpulpv2: pv.srl.sc.b + snitch_riscv_instr::PV_SRL_SCI_B, // Xpulpv2: pv.srl.sci.b + snitch_riscv_instr::PV_SRA_H, // Xpulpv2: pv.sra.h + snitch_riscv_instr::PV_SRA_SC_H, // Xpulpv2: pv.sra.sc.h + snitch_riscv_instr::PV_SRA_SCI_H, // Xpulpv2: pv.sra.sci.h + snitch_riscv_instr::PV_SRA_B, // Xpulpv2: pv.sra.b + snitch_riscv_instr::PV_SRA_SC_B, // Xpulpv2: pv.sra.sc.b + snitch_riscv_instr::PV_SRA_SCI_B, // Xpulpv2: pv.sra.sci.b + snitch_riscv_instr::PV_SLL_H, // Xpulpv2: pv.sll.h + snitch_riscv_instr::PV_SLL_SC_H, // Xpulpv2: pv.sll.sc.h + snitch_riscv_instr::PV_SLL_SCI_H, // Xpulpv2: pv.sll.sci.h + snitch_riscv_instr::PV_SLL_B, // Xpulpv2: pv.sll.b + snitch_riscv_instr::PV_SLL_SC_B, // Xpulpv2: pv.sll.sc.b + snitch_riscv_instr::PV_SLL_SCI_B, // Xpulpv2: pv.sll.sci.b + snitch_riscv_instr::PV_OR_H, // Xpulpv2: pv.or.h + snitch_riscv_instr::PV_OR_SC_H, // Xpulpv2: pv.or.sc.h + snitch_riscv_instr::PV_OR_SCI_H, // Xpulpv2: pv.or.sci.h + snitch_riscv_instr::PV_OR_B, // Xpulpv2: pv.or.b + snitch_riscv_instr::PV_OR_SC_B, // Xpulpv2: pv.or.sc.b + snitch_riscv_instr::PV_OR_SCI_B, // Xpulpv2: pv.or.sci.b + snitch_riscv_instr::PV_XOR_H, // Xpulpv2: pv.xor.h + snitch_riscv_instr::PV_XOR_SC_H, // Xpulpv2: pv.xor.sc.h + snitch_riscv_instr::PV_XOR_SCI_H, // Xpulpv2: pv.xor.sci.h + snitch_riscv_instr::PV_XOR_B, // Xpulpv2: pv.xor.b + snitch_riscv_instr::PV_XOR_SC_B, // Xpulpv2: pv.xor.sc.b + snitch_riscv_instr::PV_XOR_SCI_B, // Xpulpv2: pv.xor.sci.b + snitch_riscv_instr::PV_AND_H, // Xpulpv2: pv.and.h + snitch_riscv_instr::PV_AND_SC_H, // Xpulpv2: pv.and.sc.h + snitch_riscv_instr::PV_AND_SCI_H, // Xpulpv2: pv.and.sci.h + snitch_riscv_instr::PV_AND_B, // Xpulpv2: pv.and.b + snitch_riscv_instr::PV_AND_SC_B, // Xpulpv2: pv.and.sc.b + snitch_riscv_instr::PV_AND_SCI_B, // Xpulpv2: pv.and.sci.b + snitch_riscv_instr::PV_ABS_H, // Xpulpv2: pv.abs.h + snitch_riscv_instr::PV_ABS_B, // Xpulpv2: pv.abs.b + snitch_riscv_instr::PV_EXTRACT_H, // Xpulpv2: pv.extract.h + snitch_riscv_instr::PV_EXTRACT_B, // Xpulpv2: pv.extract.b + snitch_riscv_instr::PV_EXTRACTU_H, // Xpulpv2: pv.extractu.h + snitch_riscv_instr::PV_EXTRACTU_B, // Xpulpv2: pv.extractu.b + snitch_riscv_instr::PV_INSERT_H, // Xpulpv2: pv.insert.h + snitch_riscv_instr::PV_INSERT_B, // Xpulpv2: pv.insert.b + snitch_riscv_instr::PV_DOTUP_H, // Xpulpv2: pv.dotup.h + snitch_riscv_instr::PV_DOTUP_SC_H, // Xpulpv2: pv.dotup.sc.h + snitch_riscv_instr::PV_DOTUP_SCI_H, // Xpulpv2: pv.dotup.sci.h + snitch_riscv_instr::PV_DOTUP_B, // Xpulpv2: pv.dotup.b + snitch_riscv_instr::PV_DOTUP_SC_B, // Xpulpv2: pv.dotup.sc.b + snitch_riscv_instr::PV_DOTUP_SCI_B, // Xpulpv2: pv.dotup.sci.b + snitch_riscv_instr::PV_DOTUSP_H, // Xpulpv2: pv.dotusp.h + snitch_riscv_instr::PV_DOTUSP_SC_H, // Xpulpv2: pv.dotusp.sc.h + snitch_riscv_instr::PV_DOTUSP_SCI_H, // Xpulpv2: pv.dotusp.sci.h + snitch_riscv_instr::PV_DOTUSP_B, // Xpulpv2: pv.dotusp.b + snitch_riscv_instr::PV_DOTUSP_SC_B, // Xpulpv2: pv.dotusp.sc.b + snitch_riscv_instr::PV_DOTUSP_SCI_B, // Xpulpv2: pv.dotusp.sci.b + snitch_riscv_instr::PV_DOTSP_H, // Xpulpv2: pv.dotsp.h + snitch_riscv_instr::PV_DOTSP_SC_H, // Xpulpv2: pv.dotsp.sc.h + snitch_riscv_instr::PV_DOTSP_SCI_H, // Xpulpv2: pv.dotsp.sci.h + snitch_riscv_instr::PV_DOTSP_B, // Xpulpv2: pv.dotsp.b + snitch_riscv_instr::PV_DOTSP_SC_B, // Xpulpv2: pv.dotsp.sc.b + snitch_riscv_instr::PV_DOTSP_SCI_B, // Xpulpv2: pv.dotsp.sci.b + snitch_riscv_instr::PV_SDOTUP_H, // Xpulpv2: pv.sdotup.h + snitch_riscv_instr::PV_SDOTUP_SC_H, // Xpulpv2: pv.sdotup.sc.h + snitch_riscv_instr::PV_SDOTUP_SCI_H, // Xpulpv2: pv.sdotup.sci.h + snitch_riscv_instr::PV_SDOTUP_B, // Xpulpv2: pv.sdotup.b + snitch_riscv_instr::PV_SDOTUP_SC_B, // Xpulpv2: pv.sdotup.sc.b + snitch_riscv_instr::PV_SDOTUP_SCI_B, // Xpulpv2: pv.sdotup.sci.b + snitch_riscv_instr::PV_SDOTUSP_H, // Xpulpv2: pv.sdotusp.h + snitch_riscv_instr::PV_SDOTUSP_SC_H, // Xpulpv2: pv.sdotusp.sc.h + snitch_riscv_instr::PV_SDOTUSP_SCI_H, // Xpulpv2: pv.sdotusp.sci.h + snitch_riscv_instr::PV_SDOTUSP_B, // Xpulpv2: pv.sdotusp.b + snitch_riscv_instr::PV_SDOTUSP_SC_B, // Xpulpv2: pv.sdotusp.sc.b + snitch_riscv_instr::PV_SDOTUSP_SCI_B, // Xpulpv2: pv.sdotusp.sci.b + snitch_riscv_instr::PV_SDOTSP_H, // Xpulpv2: pv.sdotsp.h + snitch_riscv_instr::PV_SDOTSP_SC_H, // Xpulpv2: pv.sdotsp.sc.h + snitch_riscv_instr::PV_SDOTSP_SCI_H, // Xpulpv2: pv.sdotsp.sci.h + snitch_riscv_instr::PV_SDOTSP_B, // Xpulpv2: pv.sdotsp.b + snitch_riscv_instr::PV_SDOTSP_SC_B, // Xpulpv2: pv.sdotsp.sc.b + snitch_riscv_instr::PV_SDOTSP_SCI_B, // Xpulpv2: pv.sdotsp.sci.b + snitch_riscv_instr::PV_SHUFFLE2_H, // Xpulpv2: pv.shuffle2.h + snitch_riscv_instr::PV_SHUFFLE2_B, // Xpulpv2: pv.shuffle2.b + snitch_riscv_instr::PV_PACK, // Xpulpv2: pv.pack + snitch_riscv_instr::PV_PACK_H: begin // Xpulpv2: pv.pack.h if (Xpulpv2) begin dsp_valid_op = acc_req_i.q_valid; acc_rsp_o.q_ready = dsp_ready_op; @@ -443,606 +443,606 @@ module dspu #( simd_dotp_acc = 0; unique casez (operator_i) // Multiplications from M extension - riscv_instr::MUL: begin + snitch_riscv_instr::MUL: begin mac_op = MulLow; mac_op_a_sign = 1'b1; mac_op_b_sign = 1'b1; res_sel = Mac; end - riscv_instr::MULH: begin + snitch_riscv_instr::MULH: begin mac_op = MulHigh; mac_op_a_sign = 1'b1; mac_op_b_sign = 1'b1; res_sel = Mac; end - riscv_instr::MULHSU: begin + snitch_riscv_instr::MULHSU: begin mac_op = MulHigh; mac_op_a_sign = 1'b1; res_sel = Mac; end - riscv_instr::MULHU: begin + snitch_riscv_instr::MULHU: begin mac_op = MulHigh; res_sel = Mac; end // Instructions from Xpulpv2 - riscv_instr::P_ABS: begin + snitch_riscv_instr::P_ABS: begin cmp_op_b_sel = Zero; res_sel = Abs; end - riscv_instr::P_SLET: begin + snitch_riscv_instr::P_SLET: begin cmp_op_b_sel = Reg; res_sel = Sle; end - riscv_instr::P_SLETU: begin + snitch_riscv_instr::P_SLETU: begin cmp_signed = 1'b0; cmp_op_b_sel = Reg; res_sel = Sle; end - riscv_instr::P_MIN: begin + snitch_riscv_instr::P_MIN: begin cmp_op_b_sel = Reg; res_sel = Min; end - riscv_instr::P_MINU: begin + snitch_riscv_instr::P_MINU: begin cmp_signed = 1'b0; cmp_op_b_sel = Reg; res_sel = Min; end - riscv_instr::P_MAX: begin + snitch_riscv_instr::P_MAX: begin cmp_op_b_sel = Reg; res_sel = Max; end - riscv_instr::P_MAXU: begin + snitch_riscv_instr::P_MAXU: begin cmp_signed = 1'b0; cmp_op_b_sel = Reg; res_sel = Max; end - riscv_instr::P_EXTHS: begin + snitch_riscv_instr::P_EXTHS: begin cmp_op_b_sel = Reg; res_sel = Exths; end - riscv_instr::P_EXTHZ: begin + snitch_riscv_instr::P_EXTHZ: begin cmp_op_b_sel = Reg; res_sel = Exthz; end - riscv_instr::P_EXTBS: begin + snitch_riscv_instr::P_EXTBS: begin cmp_op_b_sel = Reg; res_sel = Extbs; end - riscv_instr::P_EXTBZ: begin + snitch_riscv_instr::P_EXTBZ: begin cmp_op_b_sel = Reg; res_sel = Extbz; end - riscv_instr::P_CLIP: begin + snitch_riscv_instr::P_CLIP: begin cmp_op_b_sel = ClipBound; res_sel = Clip; end - riscv_instr::P_CLIPU: begin + snitch_riscv_instr::P_CLIPU: begin clip_unsigned = 1'b1; cmp_op_b_sel = ClipBound; res_sel = Clip; end - riscv_instr::P_CLIPR: begin + snitch_riscv_instr::P_CLIPR: begin clip_register = 1'b1; cmp_op_b_sel = ClipBound; res_sel = Clip; end - riscv_instr::P_CLIPUR: begin + snitch_riscv_instr::P_CLIPUR: begin clip_unsigned = 1'b1; clip_register = 1'b1; cmp_op_b_sel = ClipBound; res_sel = Clip; end - riscv_instr::P_MAC: begin + snitch_riscv_instr::P_MAC: begin mac_op = MulMac; mac_op_a_sign = 1'b1; mac_op_b_sign = 1'b1; res_sel = Mac; end - riscv_instr::P_MSU: begin + snitch_riscv_instr::P_MSU: begin mac_op = MulMac; mac_msu = 1'b1; mac_op_a_sign = 1'b1; mac_op_b_sign = 1'b1; res_sel = Mac; end - riscv_instr::PV_ADD_H: begin + snitch_riscv_instr::PV_ADD_H: begin simd_op = SimdAdd; res_sel = Simd; end - riscv_instr::PV_ADD_SC_H: begin + snitch_riscv_instr::PV_ADD_SC_H: begin simd_op = SimdAdd; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_ADD_SCI_H: begin + snitch_riscv_instr::PV_ADD_SCI_H: begin simd_op = SimdAdd; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_ADD_B: begin + snitch_riscv_instr::PV_ADD_B: begin simd_op = SimdAdd; simd_size = Byte; res_sel = Simd; end - riscv_instr::PV_ADD_SC_B: begin + snitch_riscv_instr::PV_ADD_SC_B: begin simd_op = SimdAdd; simd_size = Byte; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_ADD_SCI_B: begin + snitch_riscv_instr::PV_ADD_SCI_B: begin simd_op = SimdAdd; simd_size = Byte; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_SUB_H: begin + snitch_riscv_instr::PV_SUB_H: begin simd_op = SimdSub; res_sel = Simd; end - riscv_instr::PV_SUB_SC_H: begin + snitch_riscv_instr::PV_SUB_SC_H: begin simd_op = SimdSub; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_SUB_SCI_H: begin + snitch_riscv_instr::PV_SUB_SCI_H: begin simd_op = SimdSub; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_SUB_B: begin + snitch_riscv_instr::PV_SUB_B: begin simd_op = SimdSub; simd_size = Byte; res_sel = Simd; end - riscv_instr::PV_SUB_SC_B: begin + snitch_riscv_instr::PV_SUB_SC_B: begin simd_op = SimdSub; simd_size = Byte; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_SUB_SCI_B: begin + snitch_riscv_instr::PV_SUB_SCI_B: begin simd_op = SimdSub; simd_size = Byte; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_AVG_H: begin + snitch_riscv_instr::PV_AVG_H: begin simd_op = SimdAvg; res_sel = Simd; end - riscv_instr::PV_AVG_SC_H: begin + snitch_riscv_instr::PV_AVG_SC_H: begin simd_op = SimdAvg; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_AVG_SCI_H: begin + snitch_riscv_instr::PV_AVG_SCI_H: begin simd_op = SimdAvg; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_AVG_B: begin + snitch_riscv_instr::PV_AVG_B: begin simd_op = SimdAvg; simd_size = Byte; res_sel = Simd; end - riscv_instr::PV_AVG_SC_B: begin + snitch_riscv_instr::PV_AVG_SC_B: begin simd_op = SimdAvg; simd_size = Byte; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_AVG_SCI_B: begin + snitch_riscv_instr::PV_AVG_SCI_B: begin simd_op = SimdAvg; simd_size = Byte; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_AVGU_H: begin + snitch_riscv_instr::PV_AVGU_H: begin simd_op = SimdAvg; simd_signed = 0; res_sel = Simd; end - riscv_instr::PV_AVGU_SC_H: begin + snitch_riscv_instr::PV_AVGU_SC_H: begin simd_op = SimdAvg; simd_mode = Sc; simd_signed = 0; res_sel = Simd; end - riscv_instr::PV_AVGU_SCI_H: begin + snitch_riscv_instr::PV_AVGU_SCI_H: begin simd_op = SimdAvg; simd_mode = Sci; simd_signed = 0; res_sel = Simd; end - riscv_instr::PV_AVGU_B: begin + snitch_riscv_instr::PV_AVGU_B: begin simd_op = SimdAvg; simd_size = Byte; simd_signed = 0; res_sel = Simd; end - riscv_instr::PV_AVGU_SC_B: begin + snitch_riscv_instr::PV_AVGU_SC_B: begin simd_op = SimdAvg; simd_size = Byte; simd_mode = Sc; simd_signed = 0; res_sel = Simd; end - riscv_instr::PV_AVGU_SCI_B: begin + snitch_riscv_instr::PV_AVGU_SCI_B: begin simd_op = SimdAvg; simd_size = Byte; simd_mode = Sci; simd_signed = 0; res_sel = Simd; end - riscv_instr::PV_MIN_H: begin + snitch_riscv_instr::PV_MIN_H: begin simd_op = SimdMin; res_sel = Simd; end - riscv_instr::PV_MIN_SC_H: begin + snitch_riscv_instr::PV_MIN_SC_H: begin simd_op = SimdMin; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_MIN_SCI_H: begin + snitch_riscv_instr::PV_MIN_SCI_H: begin simd_op = SimdMin; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_MIN_B: begin + snitch_riscv_instr::PV_MIN_B: begin simd_op = SimdMin; simd_size = Byte; res_sel = Simd; end - riscv_instr::PV_MIN_SC_B: begin + snitch_riscv_instr::PV_MIN_SC_B: begin simd_op = SimdMin; simd_size = Byte; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_MIN_SCI_B: begin + snitch_riscv_instr::PV_MIN_SCI_B: begin simd_op = SimdMin; simd_size = Byte; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_MINU_H: begin + snitch_riscv_instr::PV_MINU_H: begin simd_op = SimdMin; simd_signed = 0; res_sel = Simd; end - riscv_instr::PV_MINU_SC_H: begin + snitch_riscv_instr::PV_MINU_SC_H: begin simd_op = SimdMin; simd_mode = Sc; simd_signed = 0; res_sel = Simd; end - riscv_instr::PV_MINU_SCI_H: begin + snitch_riscv_instr::PV_MINU_SCI_H: begin simd_op = SimdMin; simd_mode = Sci; simd_signed = 0; res_sel = Simd; end - riscv_instr::PV_MINU_B: begin + snitch_riscv_instr::PV_MINU_B: begin simd_op = SimdMin; simd_size = Byte; simd_signed = 0; res_sel = Simd; end - riscv_instr::PV_MINU_SC_B: begin + snitch_riscv_instr::PV_MINU_SC_B: begin simd_op = SimdMin; simd_size = Byte; simd_mode = Sc; simd_signed = 0; res_sel = Simd; end - riscv_instr::PV_MINU_SCI_B: begin + snitch_riscv_instr::PV_MINU_SCI_B: begin simd_op = SimdMin; simd_size = Byte; simd_mode = Sci; simd_signed = 0; res_sel = Simd; end - riscv_instr::PV_MAX_H: begin + snitch_riscv_instr::PV_MAX_H: begin simd_op = SimdMax; res_sel = Simd; end - riscv_instr::PV_MAX_SC_H: begin + snitch_riscv_instr::PV_MAX_SC_H: begin simd_op = SimdMax; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_MAX_SCI_H: begin + snitch_riscv_instr::PV_MAX_SCI_H: begin simd_op = SimdMax; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_MAX_B: begin + snitch_riscv_instr::PV_MAX_B: begin simd_op = SimdMax; simd_size = Byte; res_sel = Simd; end - riscv_instr::PV_MAX_SC_B: begin + snitch_riscv_instr::PV_MAX_SC_B: begin simd_op = SimdMax; simd_size = Byte; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_MAX_SCI_B: begin + snitch_riscv_instr::PV_MAX_SCI_B: begin simd_op = SimdMax; simd_size = Byte; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_MAXU_H: begin + snitch_riscv_instr::PV_MAXU_H: begin simd_op = SimdMax; simd_signed = 0; res_sel = Simd; end - riscv_instr::PV_MAXU_SC_H: begin + snitch_riscv_instr::PV_MAXU_SC_H: begin simd_op = SimdMax; simd_mode = Sc; simd_signed = 0; res_sel = Simd; end - riscv_instr::PV_MAXU_SCI_H: begin + snitch_riscv_instr::PV_MAXU_SCI_H: begin simd_op = SimdMax; simd_mode = Sci; simd_signed = 0; res_sel = Simd; end - riscv_instr::PV_MAXU_B: begin + snitch_riscv_instr::PV_MAXU_B: begin simd_op = SimdMax; simd_size = Byte; simd_signed = 0; res_sel = Simd; end - riscv_instr::PV_MAXU_SC_B: begin + snitch_riscv_instr::PV_MAXU_SC_B: begin simd_op = SimdMax; simd_size = Byte; simd_mode = Sc; simd_signed = 0; res_sel = Simd; end - riscv_instr::PV_MAXU_SCI_B: begin + snitch_riscv_instr::PV_MAXU_SCI_B: begin simd_op = SimdMax; simd_size = Byte; simd_mode = Sci; simd_signed = 0; res_sel = Simd; end - riscv_instr::PV_SRL_H: begin + snitch_riscv_instr::PV_SRL_H: begin simd_op = SimdSrl; res_sel = Simd; end - riscv_instr::PV_SRL_SC_H: begin + snitch_riscv_instr::PV_SRL_SC_H: begin simd_op = SimdSrl; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_SRL_SCI_H: begin + snitch_riscv_instr::PV_SRL_SCI_H: begin simd_op = SimdSrl; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_SRL_B: begin + snitch_riscv_instr::PV_SRL_B: begin simd_op = SimdSrl; simd_size = Byte; res_sel = Simd; end - riscv_instr::PV_SRL_SC_B: begin + snitch_riscv_instr::PV_SRL_SC_B: begin simd_op = SimdSrl; simd_size = Byte; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_SRL_SCI_B: begin + snitch_riscv_instr::PV_SRL_SCI_B: begin simd_op = SimdSrl; simd_size = Byte; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_SRA_H: begin + snitch_riscv_instr::PV_SRA_H: begin simd_op = SimdSra; res_sel = Simd; end - riscv_instr::PV_SRA_SC_H: begin + snitch_riscv_instr::PV_SRA_SC_H: begin simd_op = SimdSra; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_SRA_SCI_H: begin + snitch_riscv_instr::PV_SRA_SCI_H: begin simd_op = SimdSra; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_SRA_B: begin + snitch_riscv_instr::PV_SRA_B: begin simd_op = SimdSra; simd_size = Byte; res_sel = Simd; end - riscv_instr::PV_SRA_SC_B: begin + snitch_riscv_instr::PV_SRA_SC_B: begin simd_op = SimdSra; simd_size = Byte; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_SRA_SCI_B: begin + snitch_riscv_instr::PV_SRA_SCI_B: begin simd_op = SimdSra; simd_size = Byte; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_SLL_H: begin + snitch_riscv_instr::PV_SLL_H: begin simd_op = SimdSll; res_sel = Simd; end - riscv_instr::PV_SLL_SC_H: begin + snitch_riscv_instr::PV_SLL_SC_H: begin simd_op = SimdSll; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_SLL_SCI_H: begin + snitch_riscv_instr::PV_SLL_SCI_H: begin simd_op = SimdSll; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_SLL_B: begin + snitch_riscv_instr::PV_SLL_B: begin simd_op = SimdSll; simd_size = Byte; res_sel = Simd; end - riscv_instr::PV_SLL_SC_B: begin + snitch_riscv_instr::PV_SLL_SC_B: begin simd_op = SimdSll; simd_size = Byte; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_SLL_SCI_B: begin + snitch_riscv_instr::PV_SLL_SCI_B: begin simd_op = SimdSll; simd_size = Byte; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_OR_H: begin + snitch_riscv_instr::PV_OR_H: begin simd_op = SimdOr; res_sel = Simd; end - riscv_instr::PV_OR_SC_H: begin + snitch_riscv_instr::PV_OR_SC_H: begin simd_op = SimdOr; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_OR_SCI_H: begin + snitch_riscv_instr::PV_OR_SCI_H: begin simd_op = SimdOr; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_OR_B: begin + snitch_riscv_instr::PV_OR_B: begin simd_op = SimdOr; simd_size = Byte; res_sel = Simd; end - riscv_instr::PV_OR_SC_B: begin + snitch_riscv_instr::PV_OR_SC_B: begin simd_op = SimdOr; simd_size = Byte; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_OR_SCI_B: begin + snitch_riscv_instr::PV_OR_SCI_B: begin simd_op = SimdOr; simd_size = Byte; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_XOR_H: begin + snitch_riscv_instr::PV_XOR_H: begin simd_op = SimdXor; res_sel = Simd; end - riscv_instr::PV_XOR_SC_H: begin + snitch_riscv_instr::PV_XOR_SC_H: begin simd_op = SimdXor; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_XOR_SCI_H: begin + snitch_riscv_instr::PV_XOR_SCI_H: begin simd_op = SimdXor; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_XOR_B: begin + snitch_riscv_instr::PV_XOR_B: begin simd_op = SimdXor; simd_size = Byte; res_sel = Simd; end - riscv_instr::PV_XOR_SC_B: begin + snitch_riscv_instr::PV_XOR_SC_B: begin simd_op = SimdXor; simd_size = Byte; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_XOR_SCI_B: begin + snitch_riscv_instr::PV_XOR_SCI_B: begin simd_op = SimdXor; simd_size = Byte; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_AND_H: begin + snitch_riscv_instr::PV_AND_H: begin simd_op = SimdAnd; res_sel = Simd; end - riscv_instr::PV_AND_SC_H: begin + snitch_riscv_instr::PV_AND_SC_H: begin simd_op = SimdAnd; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_AND_SCI_H: begin + snitch_riscv_instr::PV_AND_SCI_H: begin simd_op = SimdAnd; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_AND_B: begin + snitch_riscv_instr::PV_AND_B: begin simd_op = SimdAnd; simd_size = Byte; res_sel = Simd; end - riscv_instr::PV_AND_SC_B: begin + snitch_riscv_instr::PV_AND_SC_B: begin simd_op = SimdAnd; simd_size = Byte; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_AND_SCI_B: begin + snitch_riscv_instr::PV_AND_SCI_B: begin simd_op = SimdAnd; simd_size = Byte; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_ABS_H: begin + snitch_riscv_instr::PV_ABS_H: begin simd_op = SimdAbs; res_sel = Simd; end - riscv_instr::PV_ABS_B: begin + snitch_riscv_instr::PV_ABS_B: begin simd_op = SimdAbs; simd_size = Byte; res_sel = Simd; end - riscv_instr::PV_EXTRACT_H: begin + snitch_riscv_instr::PV_EXTRACT_H: begin simd_op = SimdExt; res_sel = Simd; end - riscv_instr::PV_EXTRACT_B: begin + snitch_riscv_instr::PV_EXTRACT_B: begin simd_op = SimdExt; simd_size = Byte; res_sel = Simd; end - riscv_instr::PV_EXTRACTU_H: begin + snitch_riscv_instr::PV_EXTRACTU_H: begin simd_op = SimdExt; simd_signed = 0; res_sel = Simd; end - riscv_instr::PV_EXTRACTU_B: begin + snitch_riscv_instr::PV_EXTRACTU_B: begin simd_op = SimdExt; simd_size = Byte; simd_signed = 0; res_sel = Simd; end - riscv_instr::PV_INSERT_H: begin + snitch_riscv_instr::PV_INSERT_H: begin simd_op = SimdIns; res_sel = Simd; end - riscv_instr::PV_INSERT_B: begin + snitch_riscv_instr::PV_INSERT_B: begin simd_op = SimdIns; simd_size = Byte; res_sel = Simd; end - riscv_instr::PV_DOTUP_H: begin + snitch_riscv_instr::PV_DOTUP_H: begin simd_op = SimdDotp; simd_signed = 0; simd_dotp_op_a_signed = 0; simd_dotp_op_b_signed = 0; res_sel = Simd; end - riscv_instr::PV_DOTUP_SC_H: begin + snitch_riscv_instr::PV_DOTUP_SC_H: begin simd_op = SimdDotp; simd_mode = Sc; simd_signed = 0; @@ -1050,7 +1050,7 @@ module dspu #( simd_dotp_op_b_signed = 0; res_sel = Simd; end - riscv_instr::PV_DOTUP_SCI_H: begin + snitch_riscv_instr::PV_DOTUP_SCI_H: begin simd_op = SimdDotp; simd_mode = Sci; simd_signed = 0; @@ -1058,7 +1058,7 @@ module dspu #( simd_dotp_op_b_signed = 0; res_sel = Simd; end - riscv_instr::PV_DOTUP_B: begin + snitch_riscv_instr::PV_DOTUP_B: begin simd_op = SimdDotp; simd_size = Byte; simd_signed = 0; @@ -1066,7 +1066,7 @@ module dspu #( simd_dotp_op_b_signed = 0; res_sel = Simd; end - riscv_instr::PV_DOTUP_SC_B: begin + snitch_riscv_instr::PV_DOTUP_SC_B: begin simd_op = SimdDotp; simd_size = Byte; simd_mode = Sc; @@ -1075,7 +1075,7 @@ module dspu #( simd_dotp_op_b_signed = 0; res_sel = Simd; end - riscv_instr::PV_DOTUP_SCI_B: begin + snitch_riscv_instr::PV_DOTUP_SCI_B: begin simd_op = SimdDotp; simd_size = Byte; simd_mode = Sci; @@ -1084,75 +1084,75 @@ module dspu #( simd_dotp_op_b_signed = 0; res_sel = Simd; end - riscv_instr::PV_DOTUSP_H: begin + snitch_riscv_instr::PV_DOTUSP_H: begin simd_op = SimdDotp; simd_dotp_op_a_signed = 0; res_sel = Simd; end - riscv_instr::PV_DOTUSP_SC_H: begin + snitch_riscv_instr::PV_DOTUSP_SC_H: begin simd_op = SimdDotp; simd_mode = Sc; simd_dotp_op_a_signed = 0; res_sel = Simd; end - riscv_instr::PV_DOTUSP_SCI_H: begin + snitch_riscv_instr::PV_DOTUSP_SCI_H: begin simd_op = SimdDotp; simd_mode = Sci; simd_dotp_op_a_signed = 0; res_sel = Simd; end - riscv_instr::PV_DOTUSP_B: begin + snitch_riscv_instr::PV_DOTUSP_B: begin simd_op = SimdDotp; simd_size = Byte; simd_dotp_op_a_signed = 0; res_sel = Simd; end - riscv_instr::PV_DOTUSP_SC_B: begin + snitch_riscv_instr::PV_DOTUSP_SC_B: begin simd_op = SimdDotp; simd_size = Byte; simd_mode = Sc; simd_dotp_op_a_signed = 0; res_sel = Simd; end - riscv_instr::PV_DOTUSP_SCI_B: begin + snitch_riscv_instr::PV_DOTUSP_SCI_B: begin simd_op = SimdDotp; simd_size = Byte; simd_mode = Sci; simd_dotp_op_a_signed = 0; res_sel = Simd; end - riscv_instr::PV_DOTSP_H: begin + snitch_riscv_instr::PV_DOTSP_H: begin simd_op = SimdDotp; res_sel = Simd; end - riscv_instr::PV_DOTSP_SC_H: begin + snitch_riscv_instr::PV_DOTSP_SC_H: begin simd_op = SimdDotp; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_DOTSP_SCI_H: begin + snitch_riscv_instr::PV_DOTSP_SCI_H: begin simd_op = SimdDotp; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_DOTSP_B: begin + snitch_riscv_instr::PV_DOTSP_B: begin simd_op = SimdDotp; simd_size = Byte; res_sel = Simd; end - riscv_instr::PV_DOTSP_SC_B: begin + snitch_riscv_instr::PV_DOTSP_SC_B: begin simd_op = SimdDotp; simd_size = Byte; simd_mode = Sc; res_sel = Simd; end - riscv_instr::PV_DOTSP_SCI_B: begin + snitch_riscv_instr::PV_DOTSP_SCI_B: begin simd_op = SimdDotp; simd_size = Byte; simd_mode = Sci; res_sel = Simd; end - riscv_instr::PV_SDOTUP_H: begin + snitch_riscv_instr::PV_SDOTUP_H: begin simd_op = SimdDotp; simd_signed = 0; simd_dotp_op_a_signed = 0; @@ -1160,7 +1160,7 @@ module dspu #( simd_dotp_acc = 1; res_sel = Simd; end - riscv_instr::PV_SDOTUP_SC_H: begin + snitch_riscv_instr::PV_SDOTUP_SC_H: begin simd_op = SimdDotp; simd_mode = Sc; simd_signed = 0; @@ -1169,7 +1169,7 @@ module dspu #( simd_dotp_acc = 1; res_sel = Simd; end - riscv_instr::PV_SDOTUP_SCI_H: begin + snitch_riscv_instr::PV_SDOTUP_SCI_H: begin simd_op = SimdDotp; simd_mode = Sci; simd_signed = 0; @@ -1178,7 +1178,7 @@ module dspu #( simd_dotp_acc = 1; res_sel = Simd; end - riscv_instr::PV_SDOTUP_B: begin + snitch_riscv_instr::PV_SDOTUP_B: begin simd_op = SimdDotp; simd_size = Byte; simd_signed = 0; @@ -1187,7 +1187,7 @@ module dspu #( simd_dotp_acc = 1; res_sel = Simd; end - riscv_instr::PV_SDOTUP_SC_B: begin + snitch_riscv_instr::PV_SDOTUP_SC_B: begin simd_op = SimdDotp; simd_size = Byte; simd_mode = Sc; @@ -1197,7 +1197,7 @@ module dspu #( simd_dotp_acc = 1; res_sel = Simd; end - riscv_instr::PV_SDOTUP_SCI_B: begin + snitch_riscv_instr::PV_SDOTUP_SCI_B: begin simd_op = SimdDotp; simd_size = Byte; simd_mode = Sci; @@ -1207,34 +1207,34 @@ module dspu #( simd_dotp_acc = 1; res_sel = Simd; end - riscv_instr::PV_SDOTUSP_H: begin + snitch_riscv_instr::PV_SDOTUSP_H: begin simd_op = SimdDotp; simd_dotp_op_a_signed = 0; simd_dotp_acc = 1; res_sel = Simd; end - riscv_instr::PV_SDOTUSP_SC_H: begin + snitch_riscv_instr::PV_SDOTUSP_SC_H: begin simd_op = SimdDotp; simd_mode = Sc; simd_dotp_op_a_signed = 0; simd_dotp_acc = 1; res_sel = Simd; end - riscv_instr::PV_SDOTUSP_SCI_H: begin + snitch_riscv_instr::PV_SDOTUSP_SCI_H: begin simd_op = SimdDotp; simd_mode = Sci; simd_dotp_op_a_signed = 0; simd_dotp_acc = 1; res_sel = Simd; end - riscv_instr::PV_SDOTUSP_B: begin + snitch_riscv_instr::PV_SDOTUSP_B: begin simd_op = SimdDotp; simd_size = Byte; simd_dotp_op_a_signed = 0; simd_dotp_acc = 1; res_sel = Simd; end - riscv_instr::PV_SDOTUSP_SC_B: begin + snitch_riscv_instr::PV_SDOTUSP_SC_B: begin simd_op = SimdDotp; simd_size = Byte; simd_mode = Sc; @@ -1242,7 +1242,7 @@ module dspu #( simd_dotp_acc = 1; res_sel = Simd; end - riscv_instr::PV_SDOTUSP_SCI_B: begin + snitch_riscv_instr::PV_SDOTUSP_SCI_B: begin simd_op = SimdDotp; simd_size = Byte; simd_mode = Sci; @@ -1250,57 +1250,57 @@ module dspu #( simd_dotp_acc = 1; res_sel = Simd; end - riscv_instr::PV_SDOTSP_H: begin + snitch_riscv_instr::PV_SDOTSP_H: begin simd_op = SimdDotp; simd_dotp_acc = 1; res_sel = Simd; end - riscv_instr::PV_SDOTSP_SC_H: begin + snitch_riscv_instr::PV_SDOTSP_SC_H: begin simd_op = SimdDotp; simd_mode = Sc; simd_dotp_acc = 1; res_sel = Simd; end - riscv_instr::PV_SDOTSP_SCI_H: begin + snitch_riscv_instr::PV_SDOTSP_SCI_H: begin simd_op = SimdDotp; simd_mode = Sci; simd_dotp_acc = 1; res_sel = Simd; end - riscv_instr::PV_SDOTSP_B: begin + snitch_riscv_instr::PV_SDOTSP_B: begin simd_op = SimdDotp; simd_size = Byte; simd_dotp_acc = 1; res_sel = Simd; end - riscv_instr::PV_SDOTSP_SC_B: begin + snitch_riscv_instr::PV_SDOTSP_SC_B: begin simd_op = SimdDotp; simd_size = Byte; simd_mode = Sc; simd_dotp_acc = 1; res_sel = Simd; end - riscv_instr::PV_SDOTSP_SCI_B: begin + snitch_riscv_instr::PV_SDOTSP_SCI_B: begin simd_op = SimdDotp; simd_size = Byte; simd_mode = Sci; simd_dotp_acc = 1; res_sel = Simd; end - riscv_instr::PV_SHUFFLE2_H: begin + snitch_riscv_instr::PV_SHUFFLE2_H: begin simd_op = SimdShuffle; res_sel = Simd; end - riscv_instr::PV_SHUFFLE2_B: begin + snitch_riscv_instr::PV_SHUFFLE2_B: begin simd_op = SimdShuffle; simd_size = Byte; res_sel = Simd; end - riscv_instr::PV_PACK: begin + snitch_riscv_instr::PV_PACK: begin simd_op = SimdPack; res_sel = Simd; end - riscv_instr::PV_PACK_H: begin + snitch_riscv_instr::PV_PACK_H: begin simd_op = SimdPack; simd_mode = High; res_sel = Simd; diff --git a/hw/snitch_ipu/src/snitch_multiplier.sv b/hw/snitch_ipu/src/snitch_multiplier.sv index 3f31fc8e88..2e61dfc371 100644 --- a/hw/snitch_ipu/src/snitch_multiplier.sv +++ b/hw/snitch_ipu/src/snitch_multiplier.sv @@ -48,15 +48,15 @@ module snitch_multiplier #( sign_a = 1'b0; sign_b = 1'b0; unique casez (operator_i) - riscv_instr::MULH: begin + snitch_riscv_instr::MULH: begin sign_a = 1'b1; sign_b = 1'b1; select_upper_d = 1'b1; end - riscv_instr::MULHU: begin + snitch_riscv_instr::MULHU: begin select_upper_d = 1'b1; end - riscv_instr::MULHSU: begin + snitch_riscv_instr::MULHSU: begin sign_a = 1'b1; select_upper_d = 1'b1; end diff --git a/hw/snitch_ipu/src/snitch_serial_divider.sv b/hw/snitch_ipu/src/snitch_serial_divider.sv index af3a4dec3c..b3f5c675f2 100644 --- a/hw/snitch_ipu/src/snitch_serial_divider.sv +++ b/hw/snitch_ipu/src/snitch_serial_divider.sv @@ -38,16 +38,16 @@ module snitch_serial_divider #( signed_op = 1'b0; rem = 1'b0; unique casez (operator_i) - riscv_instr::DIV: begin + snitch_riscv_instr::DIV: begin signed_op = 1'b1; end - riscv_instr::DIVU: begin + snitch_riscv_instr::DIVU: begin end - riscv_instr::REM: begin + snitch_riscv_instr::REM: begin signed_op = 1'b1; rem = 1'b1; end - riscv_instr::REMU: begin + snitch_riscv_instr::REMU: begin rem = 1'b1; end default: ; diff --git a/hw/snitch_ssr/src/snitch_ssr.sv b/hw/snitch_ssr/src/snitch_ssr.sv index 31ef5ec0d7..b4e934d6ad 100644 --- a/hw/snitch_ssr/src/snitch_ssr.sv +++ b/hw/snitch_ssr/src/snitch_ssr.sv @@ -125,13 +125,11 @@ module snitch_ssr import snitch_ssr_pkg::*; #( if (Cfg.Indirection) begin : gen_demux tcdm_mux #( - .NrPorts ( 2 ), - .AddrWidth ( AddrWidth ), - .DataWidth ( DataWidth ), - .UserWidth ( UserWidth ), - .RespDepth ( Cfg.MuxRespDepth ), - .tcdm_req_t ( tcdm_req_t ), - .tcdm_rsp_t ( tcdm_rsp_t ) + .NrPorts ( 2 ), + .RspDepth ( Cfg.MuxRspDepth ), + .AddrWidth ( AddrWidth ), + .DataWidth ( DataWidth ), + .UserWidth ( UserWidth ) ) i_tcdm_mux ( .clk_i, .rst_ni, @@ -148,7 +146,7 @@ module snitch_ssr import snitch_ssr_pkg::*; #( end assign data_req.q_valid = data_req_qvalid; - assign data_req.q.amo = snitch_pkg::AMONone; + assign data_req.q.amo = lsu_pkg::AMONone; assign data_req.q.user = '0; assign lane_rdata_o = lane_zero ? '0 : fifo_out; diff --git a/hw/snitch_ssr/src/snitch_ssr_indirector.sv b/hw/snitch_ssr/src/snitch_ssr_indirector.sv index ca5ccefb1e..7411be1957 100644 --- a/hw/snitch_ssr/src/snitch_ssr_indirector.sv +++ b/hw/snitch_ssr/src/snitch_ssr_indirector.sv @@ -122,7 +122,7 @@ module snitch_ssr_indirector import snitch_ssr_pkg::*; #( // Index TCDM request (write-only) assign idx_req_o.q = '{addr: idx_addr, write: 1'b1, - strb: idx_strb_q, data: idx_data_q, amo: snitch_pkg::AMONone, default: '0}; + strb: idx_strb_q, data: idx_data_q, amo: lsu_pkg::AMONone, default: '0}; // Write index word when it is complete or when done is popped assign idx_req_o.q_valid = idx_word_valid_q; @@ -336,7 +336,7 @@ module snitch_ssr_indirector import snitch_ssr_pkg::*; #( end // Index TCDM request (read-only) - assign idx_req_o.q = '{addr: idx_addr, amo: snitch_pkg::AMONone, default: '0}; + assign idx_req_o.q = '{addr: idx_addr, amo: lsu_pkg::AMONone, default: '0}; // Index handshaking assign natit_ena = cfg_indir_i & idx_cred_left & ~isect_mst_blk_q & ~natit_done_i; diff --git a/hw/snitch_ssr/src/snitch_ssr_pkg.sv b/hw/snitch_ssr/src/snitch_ssr_pkg.sv index 5cc25ea85d..1f8bc9d157 100644 --- a/hw/snitch_ssr/src/snitch_ssr_pkg.sv +++ b/hw/snitch_ssr/src/snitch_ssr_pkg.sv @@ -24,7 +24,7 @@ package snitch_ssr_pkg; int unsigned IndexCredits; int unsigned IsectSlaveCredits; int unsigned DataCredits; - int unsigned MuxRespDepth; + int unsigned MuxRspDepth; } ssr_cfg_t; // Derived parameters for intersection diff --git a/hw/snitch_ssr/test/fixture_ssr.sv b/hw/snitch_ssr/test/fixture_ssr.sv index 59d053baef..08f2c4043b 100644 --- a/hw/snitch_ssr/test/fixture_ssr.sv +++ b/hw/snitch_ssr/test/fixture_ssr.sv @@ -152,7 +152,7 @@ module fixture_ssr import snitch_ssr_pkg::*; #( // Connect DUT to TCDM bus `TCDM_ASSIGN_FROM_REQ(tcdm_bus, mem_req_o) - `TCDM_ASSIGN_TO_RESP(mem_rsp_i, tcdm_bus) + `TCDM_ASSIGN_TO_RSP(mem_rsp_i, tcdm_bus) // TCDM driver tcdm_test::tcdm_driver #( diff --git a/hw/snitch_ssr/test/fixture_ssr_streamer.sv b/hw/snitch_ssr/test/fixture_ssr_streamer.sv index a2cfe4e423..f333e2bc3c 100644 --- a/hw/snitch_ssr/test/fixture_ssr_streamer.sv +++ b/hw/snitch_ssr/test/fixture_ssr_streamer.sv @@ -171,7 +171,7 @@ module fixture_ssr_streamer import snitch_ssr_pkg::*; #( // Connect DUT to TCDM bus `TCDM_ASSIGN_FROM_REQ(tcdm_bus, mem_req_o[p]) - `TCDM_ASSIGN_TO_RESP(mem_rsp_i[p], tcdm_bus) + `TCDM_ASSIGN_TO_RSP(mem_rsp_i[p], tcdm_bus) // TCDM driver tcdm_test::tcdm_driver #( diff --git a/hw/snitch_ssr/test/tb_simple_ssr.sv b/hw/snitch_ssr/test/tb_simple_ssr.sv index 9b26b608da..8d24cc5d64 100644 --- a/hw/snitch_ssr/test/tb_simple_ssr.sv +++ b/hw/snitch_ssr/test/tb_simple_ssr.sv @@ -31,7 +31,7 @@ module tb_simple_ssr; ShiftWidth: 3, IndexCredits: 3, DataCredits: 4, - MuxRespDepth: 3, + MuxRspDepth: 3, RptWidth: 4, // Zero intersection params default: '0 diff --git a/hw/snitch_ssr/test/tb_simple_ssr_streamer.sv b/hw/snitch_ssr/test/tb_simple_ssr_streamer.sv index 813c09bc57..abd43f8132 100644 --- a/hw/snitch_ssr/test/tb_simple_ssr_streamer.sv +++ b/hw/snitch_ssr/test/tb_simple_ssr_streamer.sv @@ -32,7 +32,7 @@ module tb_simple_ssr_streamer; ShiftWidth: 3, IndexCredits: 3, DataCredits: 4, - MuxRespDepth: 3, + MuxRspDepth: 3, RptWidth: 4, IsectSlaveSpill: 1, IsectSlaveCredits: 8, diff --git a/hw/snitch_vm/src/snitch_ptw.sv b/hw/snitch_vm/src/snitch_ptw.sv index 72df8df3ca..e9ccbeaebc 100644 --- a/hw/snitch_vm/src/snitch_ptw.sv +++ b/hw/snitch_vm/src/snitch_ptw.sv @@ -6,18 +6,20 @@ `include "common_cells/registers.svh" `include "common_cells/assertions.svh" +`include "snitch/typedef.svh" /// Page table walker (PTW) for RISC-V (Custom)Sv32 address translation. module snitch_ptw import snitch_pkg::*; #( parameter int unsigned AddrWidth = 64, parameter int unsigned DataWidth = 64, - parameter type dreq_t = logic, - parameter type drsp_t = logic, + parameter int unsigned UserWidth = 0, parameter type pa_t = logic, parameter type l0_pte_t = logic, parameter type pte_sv32_t = logic, /// Derived parameter. *Do not change* - parameter int unsigned PPNSize = AddrWidth - PageShift + localparam int unsigned PPNSize = AddrWidth - PageShift, + localparam type lsu_req_t = `LSU_REQ_STRUCT(DataWidth, AddrWidth, UserWidth), + localparam type lsu_rsp_t = `LSU_RSP_STRUCT(DataWidth) ) ( input logic clk_i, input logic rst_ni, @@ -30,8 +32,8 @@ module snitch_ptw import snitch_pkg::*; #( /// Is this a 4 mega page i.e,. super-page output logic is_4mega_o, /// Memory interface - output dreq_t data_req_o, - input drsp_t data_rsp_i + output lsu_req_t data_req_o, + input lsu_rsp_t data_rsp_i ); /// Page Table Entry Size in Bytes @@ -90,10 +92,11 @@ module snitch_ptw import snitch_pkg::*; #( always_comb begin automatic logic [PageShift-1:0] page_table_index; // As of now this is a read only interface. - data_req_o.q.amo = snitch_pkg::AMONone; + data_req_o.q.amo = lsu_pkg::AMONone; data_req_o.q.data = '0; data_req_o.q.write = 0; data_req_o.q.strb = '0; + data_req_o.q.user = '0; lvl_d = lvl_q; state_d = state_q; diff --git a/hw/tcdm_interface/README.md b/hw/tcdm_interface/README.md index 273fd60a2f..25fccd2916 100644 --- a/hw/tcdm_interface/README.md +++ b/hw/tcdm_interface/README.md @@ -37,8 +37,8 @@ channel. | Name | Description | Status | | ---------------- | ----------------------------------------------------------------------------- | ------ | -| `axi_to_tcdm` | Translates from AXI4+ATOP to `tcdm` using `axi_to_reqrsp` and `reqrsp_to_mem` | active | -| `reqrsp_to_tcdm` | Translates from `reqrsp` to `tcdm`. | active | +| `axi_to_tcdm` | Translates from AXI4+ATOP to `tcdm` using `axi_to_lsu` and `lsu_to_tcdm` | active | +| `lsu_to_tcdm` | Translates from the Snitch LSU interface to `tcdm`. | active | | `tcdm_intf` | Systemverilog interface definition of `tcdm` interface. | active | | `tcdm_mux` | Arbitrate multiple ports based on round-robin arbitration. | active | | `tcdm_test` | Common test infrastructure for the `tcdm` protocol. | active | diff --git a/hw/tcdm_interface/include/tcdm_interface/assign.svh b/hw/tcdm_interface/include/tcdm_interface/assign.svh index 76cf21306c..1d23b17f7b 100644 --- a/hw/tcdm_interface/include/tcdm_interface/assign.svh +++ b/hw/tcdm_interface/include/tcdm_interface/assign.svh @@ -55,9 +55,9 @@ // The request macro `TCDM_ASSIGN_FROM_REQ(TCDM_if, req_struct)` assigns the // request channel and the request-side handshake signals of the `TCDM_if` // interface from the signals in `req_struct`. The response macro -// `TCDM_ASSIGN_FROM_RESP(TCDM_if, resp_struct)` assigns the response +// `TCDM_ASSIGN_FROM_RSP(TCDM_if, rsp_struct)` assigns the response // channel and the response-side handshake signals of the `TCDM_if` interface -// from the signals in `resp_struct`. +// from the signals in `rsp_struct`. // // Usage Example: // `TCDM_ASSIGN_FROM_REQ(my_if, my_req_struct) @@ -65,10 +65,10 @@ `TCDM_ASSIGN_VALID(assign, TCDM_if, req_struct, q) \ `TCDM_ASSIGN_Q_CHAN(assign, TCDM_if, req_struct, _, .) -`define TCDM_ASSIGN_FROM_RESP(TCDM_if, resp_struct) \ - `TCDM_ASSIGN_READY(assign, TCDM_if, resp_struct, q) \ - `TCDM_ASSIGN_P_CHAN(assign, TCDM_if, resp_struct, _, .) \ - `TCDM_ASSIGN_VALID(assign, TCDM_if, resp_struct, p) +`define TCDM_ASSIGN_FROM_RSP(TCDM_if, rsp_struct) \ + `TCDM_ASSIGN_READY(assign, TCDM_if, rsp_struct, q) \ + `TCDM_ASSIGN_P_CHAN(assign, TCDM_if, rsp_struct, _, .) \ + `TCDM_ASSIGN_VALID(assign, TCDM_if, rsp_struct, p) //////////////////////////////////////////////////////////////////////////////////////////////////// @@ -76,11 +76,11 @@ // Assigning channel or request/response structs from an interface outside a // process. // -// The request macro `TCDM_ASSIGN_TO_REQ(TCDM_if, req_struct)` assigns all +// The request macro `TCDM_ASSIGN_TO_REQ(req_struct, TCDM_if)` assigns all // signals of `req_struct` payload and request-side handshake signals to the // signals in the `TCDM_if` interface. The response macro -// `TCDM_ASSIGN_TO_RESP(TCDM_if, resp_struct)` assigns all signals of -// `resp_struct` payload and response-side handshake signals to the signals in +// `TCDM_ASSIGN_TO_RSP(rsp_struct, TCDM_if)` assigns all signals of +// `rsp_struct` payload and response-side handshake signals to the signals in // the `TCDM_if` interface. // // Usage Example: @@ -89,10 +89,10 @@ `TCDM_ASSIGN_VALID(assign, req_struct, TCDM_if, q) \ `TCDM_ASSIGN_Q_CHAN(assign, req_struct, TCDM_if, ., _) -`define TCDM_ASSIGN_TO_RESP(resp_struct, TCDM_if) \ - `TCDM_ASSIGN_READY(assign, resp_struct, TCDM_if, q) \ - `TCDM_ASSIGN_P_CHAN(assign, resp_struct, TCDM_if, ., _) \ - `TCDM_ASSIGN_VALID(assign, resp_struct, TCDM_if, p) +`define TCDM_ASSIGN_TO_RSP(rsp_struct, TCDM_if) \ + `TCDM_ASSIGN_READY(assign, rsp_struct, TCDM_if, q) \ + `TCDM_ASSIGN_P_CHAN(assign, rsp_struct, TCDM_if, ., _) \ + `TCDM_ASSIGN_VALID(assign, rsp_struct, TCDM_if, p) //////////////////////////////////////////////////////////////////////////////////////////////////// `endif diff --git a/hw/tcdm_interface/include/tcdm_interface/typedef.svh b/hw/tcdm_interface/include/tcdm_interface/typedef.svh index 954c9c37ab..6ae0bc74c8 100644 --- a/hw/tcdm_interface/include/tcdm_interface/typedef.svh +++ b/hw/tcdm_interface/include/tcdm_interface/typedef.svh @@ -8,11 +8,13 @@ `ifndef TCDM_INTERFACE_TYPEDEF_SVH_ `define TCDM_INTERFACE_TYPEDEF_SVH_ +`include "reqrsp_interface/typedef.svh" + `define TCDM_REQ_CHAN_STRUCT(__data_width, __addr_width, __user_width) \ struct packed { \ logic [``__addr_width``-1:0] addr; \ logic write; \ - snitch_pkg::amo_op_e amo; \ + lsu_pkg::amo_op_e amo; \ logic [``__data_width``-1:0] data; \ logic [``__data_width``/8-1:0] strb; \ logic [``__user_width``-1:0] user; \ @@ -23,35 +25,34 @@ logic [``__data_width``-1:0] data; \ } -`define TCDM_TYPEDEF_REQ_CHAN_T(__req_chan_t, __data_width, __addr_width, __user_width) \ - typedef `TCDM_REQ_CHAN_STRUCT(__data_width, __addr_width, __user_width) __req_chan_t; +`define TCDM_REQ_STRUCT_FROM_CHAN(__req_chan_t) \ + struct packed { \ + __req_chan_t q; \ + logic q_valid; \ + } -`define TCDM_TYPEDEF_RSP_CHAN_T(__rsp_chan_t, __data_width) \ - typedef `TCDM_RSP_CHAN_STRUCT(__data_width) __rsp_chan_t; +`define TCDM_REQ_STRUCT(__data_width, __addr_width, __user_width) \ + `TCDM_REQ_STRUCT_FROM_CHAN(`TCDM_REQ_CHAN_STRUCT(__data_width, __addr_width, __user_width)) -`define TCDM_REQ_STRUCT(__data_width, __addr_width, __user_width) \ - struct packed { \ - `TCDM_REQ_CHAN_STRUCT(__data_width, __addr_width, __user_width) q; \ - logic q_valid; \ - } +`define TCDM_RSP_STRUCT(__data_width) \ + `REQRSP_RSP_STRUCT(`TCDM_RSP_CHAN_STRUCT(__data_width)) -`define TCDM_RSP_STRUCT(__data_width) \ - struct packed { \ - `TCDM_RSP_CHAN_STRUCT(__data_width) p; \ - logic p_valid; \ - logic q_ready; \ - } +`define TCDM_TYPEDEF_REQ_CHAN_T(__name, __data_width, __addr_width, __user_width) \ + typedef `TCDM_REQ_CHAN_STRUCT(__data_width, __addr_width, __user_width) __name``_req_chan_t; + +`define TCDM_TYPEDEF_RSP_CHAN_T(__name, __data_width) \ + typedef `TCDM_RSP_CHAN_STRUCT(__data_width) __name``_rsp_chan_t; -`define TCDM_TYPEDEF_REQ_T(__req_t, __data_width, __addr_width, __user_width) \ - typedef `TCDM_REQ_STRUCT(__data_width, __addr_width, __user_width) __req_t; +`define TCDM_TYPEDEF_REQRSP_CHAN_ALL(__name, __data_width, __addr_width, __user_width) \ + `TCDM_TYPEDEF_REQ_CHAN_T(__name, __data_width, __addr_width, __user_width) \ + `TCDM_TYPEDEF_RSP_CHAN_T(__name, __data_width) \ -`define TCDM_TYPEDEF_RSP_T(__rsp_t, __data_width) \ - typedef `TCDM_RSP_STRUCT(__data_width) __rsp_t; +`define TCDM_TYPEDEF_REQ_T(__req_t, __req_chan_t) \ + typedef `TCDM_REQ_STRUCT_FROM_CHAN(__req_chan_t) __req_t; -`define TCDM_TYPEDEF_ALL(__name, __data_width, __addr_width, __user_width) \ - `TCDM_TYPEDEF_REQ_CHAN_T(__name``_req_chan_t, __data_width, __addr_width, __user_width) \ - `TCDM_TYPEDEF_RSP_CHAN_T(__name``_rsp_chan_t, __data_width) \ - `TCDM_TYPEDEF_REQ_T(__name``_req_t, __data_width, __addr_width, __user_width) \ - `TCDM_TYPEDEF_RSP_T(__name``_rsp_t, __data_width) +`define TCDM_TYPEDEF_ALL(__name, __data_width, __addr_width, __user_width) \ + `TCDM_TYPEDEF_REQRSP_CHAN_ALL(__name, __data_width, __addr_width, __user_width) \ + `TCDM_TYPEDEF_REQ_T(__name``_req_t, __name``_req_chan_t) \ + `REQRSP_TYPEDEF_RSP_T(__name``_rsp_t, __name``_rsp_chan_t) -`endif +`endif // TCDM_INTERFACE_TYPEDEF_SVH_ diff --git a/hw/tcdm_interface/src/axi_to_tcdm.sv b/hw/tcdm_interface/src/axi_to_tcdm.sv index 4eeb18dbfe..e183c43eec 100644 --- a/hw/tcdm_interface/src/axi_to_tcdm.sv +++ b/hw/tcdm_interface/src/axi_to_tcdm.sv @@ -4,18 +4,33 @@ // Author: Florian Zaruba `include "reqrsp_interface/typedef.svh" +`include "lsu_interface/typedef.svh" +`include "tcdm_interface/typedef.svh" +`include "axi/typedef.svh" /// Convert AXI to TCDM protocol. module axi_to_tcdm #( - parameter type axi_req_t = logic, - parameter type axi_rsp_t = logic, - parameter type tcdm_req_t = logic, - parameter type tcdm_rsp_t = logic, - parameter int unsigned AddrWidth = 0, - parameter int unsigned DataWidth = 0, - parameter int unsigned UserWidth = 0, - parameter int unsigned IdWidth = 0, - parameter int unsigned BufDepth = 1 + parameter int unsigned AddrWidth = 0, + parameter int unsigned DataWidth = 0, + parameter int unsigned IdWidth = 0, + parameter int unsigned UserWidth = 0, + parameter int unsigned BufDepth = 1, + /// Derived parameters *do not override* + localparam int unsigned StrbWidth = DataWidth/8, + localparam type addr_t = logic [AddrWidth-1:0], + localparam type data_t = logic [DataWidth-1:0], + localparam type strb_t = logic [StrbWidth-1:0], + localparam type id_t = logic [IdWidth-1:0], + localparam type user_t = logic [UserWidth-1:0], + localparam type tcdm_req_t = `TCDM_REQ_STRUCT(DataWidth, AddrWidth, UserWidth), + localparam type tcdm_rsp_t = `TCDM_RSP_STRUCT(DataWidth), + localparam type aw_chan_t = `AXI_DECL_AW_CHAN_T(addr_t, id_t, user_t), + localparam type w_chan_t = `AXI_DECL_W_CHAN_T(data_t, strb_t, user_t), + localparam type b_chan_t = `AXI_DECL_B_CHAN_T(id_t, user_t), + localparam type ar_chan_t = `AXI_DECL_AR_CHAN_T(addr_t, id_t, user_t), + localparam type r_chan_t = `AXI_DECL_R_CHAN_T(data_t, id_t, user_t), + localparam type axi_req_t = `AXI_DECL_REQ_T(aw_chan_t, w_chan_t, ar_chan_t), + localparam type axi_rsp_t = `AXI_DECL_RESP_T(b_chan_t, r_chan_t) ) ( input logic clk_i, input logic rst_ni, @@ -25,49 +40,37 @@ module axi_to_tcdm #( input tcdm_rsp_t tcdm_rsp_i ); - typedef logic [AddrWidth-1:0] addr_t; - typedef logic [DataWidth-1:0] data_t; - typedef logic [DataWidth/8-1:0] strb_t; - typedef logic [UserWidth-1:0] user_t; + `LSU_TYPEDEF_ALL(lsu, DataWidth, AddrWidth, UserWidth) - `REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t) + lsu_req_t lsu_req; + lsu_rsp_t lsu_rsp; - reqrsp_req_t reqrsp_req; - reqrsp_rsp_t reqrsp_rsp; - - axi_to_reqrsp #( - .axi_req_t (axi_req_t), - .axi_rsp_t (axi_rsp_t), + axi_to_lsu #( .AddrWidth (AddrWidth), .DataWidth (DataWidth), .IdWidth (IdWidth), - .BufDepth (BufDepth), - .reqrsp_req_t (reqrsp_req_t), - .reqrsp_rsp_t (reqrsp_rsp_t) - ) i_axi_to_reqrsp ( + .UserWidth (UserWidth), + .BufDepth (BufDepth) + ) i_axi_to_lsu ( .clk_i (clk_i), .rst_ni (rst_ni), .busy_o (/* open */), .axi_req_i (axi_req_i), .axi_rsp_o (axi_rsp_o), - .reqrsp_req_o (reqrsp_req), - .reqrsp_rsp_i (reqrsp_rsp) + .lsu_req_o (lsu_req), + .lsu_rsp_i (lsu_rsp) ); - reqrsp_to_tcdm #( + lsu_to_tcdm #( + .BufDepth (BufDepth), .AddrWidth (AddrWidth), - .DataWidth (DataWidth), .UserWidth (UserWidth), - .BufDepth (BufDepth), - .reqrsp_req_t (reqrsp_req_t), - .reqrsp_rsp_t (reqrsp_rsp_t), - .tcdm_req_t (tcdm_req_t), - .tcdm_rsp_t (tcdm_rsp_t) - ) i_reqrsp_to_tcdm ( + .DataWidth (DataWidth) + ) i_lsu_to_tcdm ( .clk_i (clk_i), .rst_ni (rst_ni), - .reqrsp_req_i (reqrsp_req), - .reqrsp_rsp_o (reqrsp_rsp), + .lsu_req_i (lsu_req), + .lsu_rsp_o (lsu_rsp), .tcdm_req_o (tcdm_req_o), .tcdm_rsp_i (tcdm_rsp_i) ); diff --git a/hw/tcdm_interface/src/lsu_to_tcdm.sv b/hw/tcdm_interface/src/lsu_to_tcdm.sv new file mode 100644 index 0000000000..165dc89738 --- /dev/null +++ b/hw/tcdm_interface/src/lsu_to_tcdm.sv @@ -0,0 +1,71 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +// Author: Florian Zaruba + +`include "reqrsp_interface/typedef.svh" +`include "lsu_interface/typedef.svh" +`include "tcdm_interface/typedef.svh" + +/// Convert from the Snitch LSU interface to tcdm. +module lsu_to_tcdm #( + parameter int unsigned BufDepth = 2, + parameter int unsigned AddrWidth = 0, + parameter int unsigned UserWidth = 0, + parameter int unsigned DataWidth = 0, + /// Derived parameters *do not override* + localparam type lsu_req_t = `LSU_REQ_STRUCT(DataWidth, AddrWidth, UserWidth), + localparam type lsu_rsp_t = `LSU_RSP_STRUCT(DataWidth), + localparam type tcdm_req_t = `TCDM_REQ_STRUCT(DataWidth, AddrWidth, UserWidth), + localparam type tcdm_rsp_t = `TCDM_RSP_STRUCT(DataWidth) +) ( + input logic clk_i, + input logic rst_ni, + input lsu_req_t lsu_req_i, + output lsu_rsp_t lsu_rsp_o, + output tcdm_req_t tcdm_req_o, + input tcdm_rsp_t tcdm_rsp_i +); + + `LSU_TYPEDEF_REQRSP_CHAN_ALL(lsu, DataWidth, AddrWidth, UserWidth) + + lsu_req_chan_t req; + lsu_rsp_chan_t rsp; + + cc_stream_to_mem #( + .mem_req_t (lsu_req_chan_t), + .mem_resp_t (lsu_rsp_chan_t), + .BufDepth (BufDepth) + ) i_stream_to_mem ( + .clk_i, + .rst_ni, + .clr_i (1'b0), + .req_i (lsu_req_i.q), + .req_valid_i (lsu_req_i.q_valid), + .req_ready_o (lsu_rsp_o.q_ready), + .resp_o (lsu_rsp_o.p), + .resp_valid_o (lsu_rsp_o.p_valid), + .resp_ready_i (lsu_req_i.p_ready), + .mem_req_o (req), + .mem_req_valid_o (tcdm_req_o.q_valid), + .mem_req_ready_i (tcdm_rsp_i.q_ready), + .mem_resp_i (rsp), + .mem_resp_valid_i (tcdm_rsp_i.p_valid) + ); + + assign tcdm_req_o.q = '{ + addr: req.addr, + write: req.write, + amo: req.amo, + data: req.data, + strb: req.strb, + user: req.user + }; + + assign rsp = '{ + data: tcdm_rsp_i.p.data, + error: 1'b0 + }; + +endmodule diff --git a/hw/tcdm_interface/src/reqrsp_to_tcdm.sv b/hw/tcdm_interface/src/reqrsp_to_tcdm.sv deleted file mode 100644 index 43d3e3189a..0000000000 --- a/hw/tcdm_interface/src/reqrsp_to_tcdm.sv +++ /dev/null @@ -1,130 +0,0 @@ -// Copyright 2020 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Author: Florian Zaruba - -`include "reqrsp_interface/typedef.svh" - -/// Convert from reqrsp to tcdm. -module reqrsp_to_tcdm #( - parameter int unsigned AddrWidth = 0, - parameter int unsigned DataWidth = 0, - parameter int unsigned UserWidth = 0, - parameter int unsigned BufDepth = 2, - parameter type reqrsp_req_t = logic, - parameter type reqrsp_rsp_t = logic, - parameter type tcdm_req_t = logic, - parameter type tcdm_rsp_t = logic -) ( - input logic clk_i, - input logic rst_ni, - input reqrsp_req_t reqrsp_req_i, - output reqrsp_rsp_t reqrsp_rsp_o, - output tcdm_req_t tcdm_req_o, - input tcdm_rsp_t tcdm_rsp_i -); - - typedef logic [AddrWidth-1:0] addr_t; - typedef logic [DataWidth-1:0] data_t; - typedef logic [DataWidth/8-1:0] strb_t; - typedef logic [UserWidth-1:0] user_t; - - `REQRSP_TYPEDEF_ALL(rr, addr_t, data_t, strb_t, user_t) - rr_req_chan_t req; - rr_rsp_chan_t rsp; - - cc_stream_to_mem #( - .mem_req_t (rr_req_chan_t), - .mem_resp_t (rr_rsp_chan_t), - .BufDepth (BufDepth) - ) i_stream_to_mem ( - .clk_i, - .rst_ni, - .clr_i (1'b0), - .req_i (reqrsp_req_i.q), - .req_valid_i (reqrsp_req_i.q_valid), - .req_ready_o (reqrsp_rsp_o.q_ready), - .resp_o (reqrsp_rsp_o.p), - .resp_valid_o (reqrsp_rsp_o.p_valid), - .resp_ready_i (reqrsp_req_i.p_ready), - .mem_req_o (req), - .mem_req_valid_o (tcdm_req_o.q_valid), - .mem_req_ready_i (tcdm_rsp_i.q_ready), - .mem_resp_i (rsp), - .mem_resp_valid_i (tcdm_rsp_i.p_valid) - ); - - assign tcdm_req_o.q = '{ - addr: req.addr, - write: req.write, - amo: req.amo, - data: req.data, - strb: req.strb, - user: req.user - }; - - assign rsp = '{ - data: tcdm_rsp_i.p.data, - error: 1'b0 - }; - -endmodule - -`include "reqrsp_interface/typedef.svh" -`include "reqrsp_interface/assign.svh" -`include "tcdm_interface/typedef.svh" -`include "tcdm_interface/assign.svh" - -/// Interface wrapper. -module reqrsp_to_tcdm_intf #( - parameter int unsigned AddrWidth = 0, - parameter int unsigned DataWidth = 0, - parameter int unsigned UserWidth = 0, - parameter int unsigned BufDepth = 2 -) ( - input logic clk_i, - input logic rst_ni, - REQRSP_BUS reqrsp, - TCDM_BUS tcdm -); - - typedef logic [AddrWidth-1:0] addr_t; - typedef logic [DataWidth-1:0] data_t; - typedef logic [DataWidth/8-1:0] strb_t; - typedef logic [UserWidth-1:0] user_t; - - `REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t, user_t) - `TCDM_TYPEDEF_ALL(tcdm, DataWidth, AddrWidth, UserWidth) - - reqrsp_req_t reqrsp_req; - reqrsp_rsp_t reqrsp_rsp; - - tcdm_req_t tcdm_req; - tcdm_rsp_t tcdm_rsp; - - reqrsp_to_tcdm #( - .AddrWidth (AddrWidth), - .DataWidth (DataWidth), - .UserWidth (UserWidth), - .BufDepth (BufDepth), - .reqrsp_req_t (reqrsp_req_t), - .reqrsp_rsp_t (reqrsp_rsp_t), - .tcdm_req_t (tcdm_req_t), - .tcdm_rsp_t (tcdm_rsp_t) - ) i_reqrsp_to_tcdm ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .reqrsp_req_i (reqrsp_req), - .reqrsp_rsp_o (reqrsp_rsp), - .tcdm_req_o (tcdm_req), - .tcdm_rsp_i (tcdm_rsp) - ); - - `REQRSP_ASSIGN_TO_REQ(reqrsp_req, reqrsp) - `REQRSP_ASSIGN_FROM_RESP(reqrsp, reqrsp_rsp) - - `TCDM_ASSIGN_FROM_REQ(tcdm, tcdm_req) - `TCDM_ASSIGN_TO_RESP(tcdm_rsp, tcdm) - -endmodule diff --git a/hw/tcdm_interface/src/tcdm_interface.sv b/hw/tcdm_interface/src/tcdm_interface.sv index 72bfa81512..9854ccb975 100644 --- a/hw/tcdm_interface/src/tcdm_interface.sv +++ b/hw/tcdm_interface/src/tcdm_interface.sv @@ -15,7 +15,7 @@ interface TCDM_BUS #( parameter type user_t = logic ); - import snitch_pkg::*; + import lsu_pkg::*; localparam int unsigned StrbWidth = DATA_WIDTH / 8; @@ -66,7 +66,7 @@ interface TCDM_BUS_DV #( input logic clk_i ); - import snitch_pkg::*; + import lsu_pkg::*; localparam int unsigned StrbWidth = DATA_WIDTH / 8; diff --git a/hw/tcdm_interface/src/tcdm_mux.sv b/hw/tcdm_interface/src/tcdm_mux.sv index e935a2cbe8..96d4a85dc2 100644 --- a/hw/tcdm_interface/src/tcdm_mux.sv +++ b/hw/tcdm_interface/src/tcdm_mux.sv @@ -7,12 +7,13 @@ /// Multiplex `NrPorts` TCDM interfaces onto one. module tcdm_mux #( parameter int unsigned NrPorts = 2, + parameter int unsigned RspDepth = 8, parameter int unsigned AddrWidth = 0, parameter int unsigned DataWidth = 0, parameter int unsigned UserWidth = 0, - parameter int unsigned RespDepth = 8, - parameter type tcdm_req_t = logic, - parameter type tcdm_rsp_t = logic + /// Derived parameters *do not override* + localparam type tcdm_req_t = `TCDM_REQ_STRUCT(DataWidth, AddrWidth, UserWidth), + localparam type tcdm_rsp_t = `TCDM_RSP_STRUCT(DataWidth) ) ( input logic clk_i, input logic rst_ni, @@ -24,8 +25,7 @@ module tcdm_mux #( localparam int unsigned SelectWidth = cc_pkg::idx_width(NrPorts); typedef logic [SelectWidth-1:0] select_t; - - `TCDM_TYPEDEF_REQ_CHAN_T(tcdm_req_chan_t, DataWidth, AddrWidth, UserWidth) + `TCDM_TYPEDEF_REQ_CHAN_T(tcdm, DataWidth, AddrWidth, UserWidth) if (NrPorts > 1) begin : gen_mux logic [NrPorts-1:0] slv_req_valid, slv_req_ready; @@ -77,7 +77,7 @@ module tcdm_mux #( cc_stream_fifo #( .FallThrough (1'b0), - .Depth (RespDepth), + .Depth (RspDepth), .data_t (select_t) ) i_stream_fifo ( .clk_i, @@ -108,7 +108,7 @@ module tcdm_mux_intf #( parameter int unsigned AddrWidth = 0, parameter int unsigned DataWidth = 0, parameter int unsigned UserWidth = 0, - parameter int unsigned RespDepth = 8 + parameter int unsigned RspDepth = 8 ) ( input logic clk_i, input logic rst_ni, @@ -126,12 +126,10 @@ module tcdm_mux_intf #( tcdm_mux #( .NrPorts (NrPorts), + .RspDepth (RspDepth), .AddrWidth (AddrWidth), .DataWidth (DataWidth), - .UserWidth (UserWidth), - .RespDepth (RespDepth), - .tcdm_req_t (tcdm_req_t), - .tcdm_rsp_t (tcdm_rsp_t) + .UserWidth (UserWidth) ) i_tcdm_mux ( .clk_i, .rst_ni, @@ -143,10 +141,10 @@ module tcdm_mux_intf #( for (genvar i = 0; i < NrPorts; i++) begin : gen_interface_assignment `TCDM_ASSIGN_TO_REQ(tcdm_slv_req[i], slv[i]) - `TCDM_ASSIGN_FROM_RESP(slv[i], tcdm_slv_rsp[i]) + `TCDM_ASSIGN_FROM_RSP(slv[i], tcdm_slv_rsp[i]) end `TCDM_ASSIGN_FROM_REQ(mst, tcdm_mst_req) - `TCDM_ASSIGN_TO_RESP(tcdm_mst_rsp, mst) + `TCDM_ASSIGN_TO_RSP(tcdm_mst_rsp, mst) endmodule diff --git a/hw/tcdm_interface/src/tcdm_test.sv b/hw/tcdm_interface/src/tcdm_test.sv index a96610594a..c534823fd6 100644 --- a/hw/tcdm_interface/src/tcdm_test.sv +++ b/hw/tcdm_interface/src/tcdm_test.sv @@ -12,7 +12,7 @@ package tcdm_test; ); rand logic [AW-1:0] addr; rand logic write; - rand snitch_pkg::amo_op_e amo; + rand lsu_pkg::amo_op_e amo; rand logic [DW-1:0] data; rand logic [DW/8-1:0] strb; rand user_t user; @@ -21,31 +21,31 @@ package tcdm_test; constraint legal_amo_op_c { amo inside { - snitch_pkg::AMOSwap, - snitch_pkg::AMOAdd, - snitch_pkg::AMOAnd, - snitch_pkg::AMOOr, - snitch_pkg::AMOXor, - snitch_pkg::AMOMax, - snitch_pkg::AMOMaxu, - snitch_pkg::AMOMin, - snitch_pkg::AMOMinu, - snitch_pkg::AMOSC} -> write == 1; + lsu_pkg::AMOSwap, + lsu_pkg::AMOAdd, + lsu_pkg::AMOAnd, + lsu_pkg::AMOOr, + lsu_pkg::AMOXor, + lsu_pkg::AMOMax, + lsu_pkg::AMOMaxu, + lsu_pkg::AMOMin, + lsu_pkg::AMOMinu, + lsu_pkg::AMOSC} -> write == 1; } // Reduce the amount of atomics. constraint amo_reduce_c { is_amo dist { 1:= 1, 0:= 10}; is_amo -> amo inside { - snitch_pkg::AMOSwap, - snitch_pkg::AMOAdd, - snitch_pkg::AMOAnd, - snitch_pkg::AMOOr, - snitch_pkg::AMOXor, - snitch_pkg::AMOMax, - snitch_pkg::AMOMaxu, - snitch_pkg::AMOMin, - snitch_pkg::AMOMinu + lsu_pkg::AMOSwap, + lsu_pkg::AMOAdd, + lsu_pkg::AMOAnd, + lsu_pkg::AMOOr, + lsu_pkg::AMOXor, + lsu_pkg::AMOMax, + lsu_pkg::AMOMaxu, + lsu_pkg::AMOMin, + lsu_pkg::AMOMinu }; } @@ -100,7 +100,7 @@ package tcdm_test; task reset_master; bus.q_addr <= '0; bus.q_write <= '0; - bus.q_amo <= snitch_pkg::AMONone; + bus.q_amo <= lsu_pkg::AMONone; bus.q_data <= '0; bus.q_strb <= '0; bus.q_user <= '0; diff --git a/hw/tcdm_interface/src/tcdm_width_converter.sv b/hw/tcdm_interface/src/tcdm_width_converter.sv new file mode 100644 index 0000000000..7d45f49bac --- /dev/null +++ b/hw/tcdm_interface/src/tcdm_width_converter.sv @@ -0,0 +1,44 @@ +// Copyright 2026 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +`include "tcdm_interface/typedef.svh" + +/// Combinational TCDM interface width converter. +/// +/// Narrower outputs keep the least-significant bits. Wider outputs are padded +/// with zeros. +module tcdm_width_converter #( + parameter int unsigned InAddrWidth = 0, + parameter int unsigned InDataWidth = 0, + parameter int unsigned InUserWidth = 0, + parameter int unsigned OutAddrWidth = 0, + parameter int unsigned OutDataWidth = 0, + parameter int unsigned OutUserWidth = 0, + /// Derived parameter *Do not override* + localparam type in_req_t = `TCDM_REQ_STRUCT(InDataWidth, InAddrWidth, InUserWidth), + localparam type in_rsp_t = `TCDM_RSP_STRUCT(InDataWidth), + localparam type out_req_t = `TCDM_REQ_STRUCT(OutDataWidth, OutAddrWidth, OutUserWidth), + localparam type out_rsp_t = `TCDM_RSP_STRUCT(OutDataWidth) +) ( + input in_req_t tcdm_req_i, + output in_rsp_t tcdm_rsp_o, + output out_req_t tcdm_req_o, + input out_rsp_t tcdm_rsp_i +); + + always_comb begin + tcdm_req_o.q.addr = tcdm_req_i.q.addr; + tcdm_req_o.q.write = tcdm_req_i.q.write; + tcdm_req_o.q.amo = tcdm_req_i.q.amo; + tcdm_req_o.q.data = tcdm_req_i.q.data; + tcdm_req_o.q.strb = tcdm_req_i.q.strb; + tcdm_req_o.q.user = tcdm_req_i.q.user; + tcdm_req_o.q_valid = tcdm_req_i.q_valid; + + tcdm_rsp_o.p.data = tcdm_rsp_i.p.data; + tcdm_rsp_o.p_valid = tcdm_rsp_i.p_valid; + tcdm_rsp_o.q_ready = tcdm_rsp_i.q_ready; + end + +endmodule diff --git a/hw/tcdm_interface/test/lsu_to_tcdm_intf.sv b/hw/tcdm_interface/test/lsu_to_tcdm_intf.sv new file mode 100644 index 0000000000..67c3b4f0bf --- /dev/null +++ b/hw/tcdm_interface/test/lsu_to_tcdm_intf.sv @@ -0,0 +1,53 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 + +`include "reqrsp_interface/typedef.svh" +`include "reqrsp_interface/assign.svh" +`include "lsu_interface/typedef.svh" +`include "tcdm_interface/typedef.svh" +`include "tcdm_interface/assign.svh" + +/// Interface wrapper for `lsu_to_tcdm`. +module lsu_to_tcdm_intf #( + parameter int unsigned AddrWidth = 0, + parameter int unsigned DataWidth = 0, + parameter int unsigned UserWidth = 0, + parameter int unsigned BufDepth = 2 +) ( + input logic clk_i, + input logic rst_ni, + LSU_BUS lsu, + TCDM_BUS tcdm +); + + `LSU_TYPEDEF_ALL(lsu, DataWidth, AddrWidth, UserWidth) + `TCDM_TYPEDEF_ALL(tcdm, DataWidth, AddrWidth, UserWidth) + + lsu_req_t lsu_req; + lsu_rsp_t lsu_rsp; + + tcdm_req_t tcdm_req; + tcdm_rsp_t tcdm_rsp; + + lsu_to_tcdm #( + .BufDepth (BufDepth), + .AddrWidth (AddrWidth), + .UserWidth (UserWidth), + .DataWidth (DataWidth) + ) i_lsu_to_tcdm ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .lsu_req_i (lsu_req), + .lsu_rsp_o (lsu_rsp), + .tcdm_req_o (tcdm_req), + .tcdm_rsp_i (tcdm_rsp) + ); + + `LSU_ASSIGN_TO_REQ(lsu_req, lsu) + `LSU_ASSIGN_FROM_RSP(lsu, lsu_rsp) + + `TCDM_ASSIGN_FROM_REQ(tcdm, tcdm_req) + `TCDM_ASSIGN_TO_RSP(tcdm_rsp, tcdm) + +endmodule diff --git a/hw/tcdm_interface/test/reqrsp_to_tcdm_tb.sv b/hw/tcdm_interface/test/lsu_to_tcdm_tb.sv similarity index 80% rename from hw/tcdm_interface/test/reqrsp_to_tcdm_tb.sv rename to hw/tcdm_interface/test/lsu_to_tcdm_tb.sv index fdd68fc83c..1cd4334029 100644 --- a/hw/tcdm_interface/test/reqrsp_to_tcdm_tb.sv +++ b/hw/tcdm_interface/test/lsu_to_tcdm_tb.sv @@ -3,10 +3,11 @@ // SPDX-License-Identifier: SHL-0.51 `include "reqrsp_interface/assign.svh" +`include "lsu_interface/typedef.svh" `include "tcdm_interface/assign.svh" -/// Testbench for `reqrsp_to_tcdm` module. -module reqrsp_to_tcdm_tb import reqrsp_pkg::*; #( +/// Testbench for `lsu_to_tcdm` module. +module lsu_to_tcdm_tb #( parameter int unsigned AW = 32, parameter int unsigned DW = 32, parameter int unsigned BufDepth = 4, @@ -24,12 +25,12 @@ module reqrsp_to_tcdm_tb import reqrsp_pkg::*; #( typedef logic [DW/8-1:0] strb_t; // interfaces - REQRSP_BUS #( + LSU_BUS #( .ADDR_WIDTH ( AW ), .DATA_WIDTH ( DW ) ) master (); - REQRSP_BUS_DV #( + LSU_BUS_DV #( .ADDR_WIDTH ( AW ), .DATA_WIDTH ( DW ) ) master_dv (clk); @@ -47,18 +48,18 @@ module reqrsp_to_tcdm_tb import reqrsp_pkg::*; #( ) slave_dv (clk); - reqrsp_to_tcdm_intf #( + lsu_to_tcdm_intf #( .AddrWidth (AW), .DataWidth (DW), .BufDepth (BufDepth) ) i_dut ( .clk_i (clk), .rst_ni (rst_n), - .reqrsp (master), + .lsu (master), .tcdm (slave) ); - `REQRSP_ASSIGN(master, master_dv) + `LSU_ASSIGN(master, master_dv) `TCDM_ASSIGN(slave_dv, slave) // ---------------- @@ -93,16 +94,16 @@ module reqrsp_to_tcdm_tb import reqrsp_pkg::*; #( rand_tcdm_slave_t rand_tcdm_slave = new (slave_dv); - typedef reqrsp_test::rand_reqrsp_master #( - // Reqrsp bus interface paramaters; + typedef lsu_test::rand_lsu_master #( + // LSU bus interface paramaters; .AW ( AW ), .DW ( DW ), // Stimuli application and test time .TA ( ApplTime ), .TT ( TestTime ) - ) reqrsp_driver_t; + ) lsu_driver_t; - reqrsp_driver_t rand_reqrsp_master = new (master_dv); + lsu_driver_t rand_lsu_master = new (master_dv); // tcdm side. initial begin @@ -113,9 +114,9 @@ module reqrsp_to_tcdm_tb import reqrsp_pkg::*; #( // tcdm side. initial begin - rand_reqrsp_master.reset(); + rand_lsu_master.reset(); @(posedge rst_n); - rand_reqrsp_master.run(NrRandomTransactions); + rand_lsu_master.run(NrRandomTransactions); repeat (100) @(posedge clk); $finish; end @@ -123,20 +124,20 @@ module reqrsp_to_tcdm_tb import reqrsp_pkg::*; #( // ------- // Monitor // ------- - typedef reqrsp_test::reqrsp_monitor #( - // Reqrsp bus interface paramaters; + typedef lsu_test::lsu_monitor #( + // LSU bus interface paramaters; .AW ( AW ), .DW ( DW ), // Stimuli application and test time .TA ( ApplTime ), .TT ( TestTime ) - ) reqrsp_monitor_t; + ) lsu_monitor_t; - reqrsp_monitor_t reqrsp_monitor = new (master_dv); - // Reqrsp Monitor. + lsu_monitor_t lsu_monitor = new (master_dv); + // LSU Monitor. initial begin @(posedge rst_n); - reqrsp_monitor.monitor(); + lsu_monitor.monitor(); end // TCDM Monitor @@ -164,12 +165,12 @@ module reqrsp_to_tcdm_tb import reqrsp_pkg::*; #( /// output. initial begin forever begin - automatic reqrsp_test::req_t req; - automatic reqrsp_test::rsp_t rsp; + automatic lsu_test::req_t req; + automatic lsu_test::rsp_t rsp; automatic tcdm_test::req_t tcdm_req; automatic tcdm_test::rsp_t tcdm_rsp; - reqrsp_monitor.req_mbx.get(req); - reqrsp_monitor.rsp_mbx.get(rsp); + lsu_monitor.req_mbx.get(req); + lsu_monitor.rsp_mbx.get(rsp); tcdm_monitor.req_mbx.get(tcdm_req); tcdm_monitor.rsp_mbx.get(tcdm_rsp); nr_transactions++; @@ -185,8 +186,8 @@ module reqrsp_to_tcdm_tb import reqrsp_pkg::*; #( end final begin - assert(reqrsp_monitor.req_mbx.num() == 0); - assert(reqrsp_monitor.req_mbx.num() == 0); + assert(lsu_monitor.req_mbx.num() == 0); + assert(lsu_monitor.req_mbx.num() == 0); assert(tcdm_monitor.req_mbx.num() == 0); assert(tcdm_monitor.rsp_mbx.num() == 0); $info("Finished with %d transactions.", nr_transactions); diff --git a/hw/tcdm_interface/test/tcdm_mux_tb.sv b/hw/tcdm_interface/test/tcdm_mux_tb.sv index d3f3c0e76c..658d06b209 100644 --- a/hw/tcdm_interface/test/tcdm_mux_tb.sv +++ b/hw/tcdm_interface/test/tcdm_mux_tb.sv @@ -7,11 +7,11 @@ /// Testbench for the `tcdm_mux`. Based on the `reqrsp_mux_tb`, see that /// testbench for a more indepth and commented version. This one just /// instantiates the right tcdm drivers. -module tcdm_mux_tb import reqrsp_pkg::*; #( +module tcdm_mux_tb #( parameter int unsigned AW = 32, parameter int unsigned DW = 32, parameter int unsigned NrPorts = 4, - parameter int unsigned RespDepth = 2, + parameter int unsigned RspDepth = 2, parameter int unsigned RegisterReq = 1, parameter int unsigned NrRandomTransactions = 1000 ); @@ -50,7 +50,7 @@ module tcdm_mux_tb import reqrsp_pkg::*; #( .AddrWidth (AW), .DataWidth (DW), .UserWidth (1), - .RespDepth (RespDepth) + .RspDepth (RspDepth) ) dut ( .clk_i (clk), .rst_ni (rst_n), diff --git a/hw/tcdm_interface/util/run_vsim.sh b/hw/tcdm_interface/util/run_vsim.sh index 6f10155d02..e18da3ebf4 100755 --- a/hw/tcdm_interface/util/run_vsim.sh +++ b/hw/tcdm_interface/util/run_vsim.sh @@ -17,4 +17,4 @@ call_vsim() { } call_vsim tcdm_mux_tb -call_vsim reqrsp_to_tcdm_tb \ No newline at end of file +call_vsim lsu_to_tcdm_tb diff --git a/iis-setup.sh b/iis-setup.sh index 071e9d1fd0..8c5261a2e6 100755 --- a/iis-setup.sh +++ b/iis-setup.sh @@ -24,11 +24,14 @@ export PATH=$PWD/target/sim/build/bin:$PATH # Initialize submodules git -c submodule.nonfree.update=checkout submodule update --init --recursive +# Initialize Bender dependencies +$SN_BENDER checkout + # Bootstrap the Python environment # Prefix with flock to prevent race condition in managed Python installation, # see https://github.com/astral-sh/uv/issues/19329 flock-2.41 --fcntl "${HOME}/uv-ci.lock" bash -euo pipefail -c ' - uv sync --all-extras --locked + uv sync --all-extras --all-groups --locked uv pip install -e nonfree ' source .venv/bin/activate diff --git a/make/common.mk b/make/common.mk index ac57cf1df9..60bae3917d 100644 --- a/make/common.mk +++ b/make/common.mk @@ -47,11 +47,14 @@ SN_GENTRACE_SRC = $(SN_UTIL_DIR)/trace/sequencer.py SN_ANNOTATE_SRC = $(SN_UTIL_DIR)/trace/a2l.py # Clustergen prerequisites -SN_CLUSTER_GEN_SRC = $(SN_ROOT)/util/clustergen/cluster.py +SN_CLUSTER_GEN_SRC = $(SN_ROOT)/util/clustergen/cluster.py +SN_CLUSTER_GEN_SRC += $(SN_ROOT)/util/clustergen/snitch_cluster.schema.json # Bender prerequisites -SN_BENDER_LOCK = $(SN_ROOT)/Bender.lock -SN_BENDER_YML = $(SN_ROOT)/Bender.yml +SN_BENDER_LOCK = $(SN_ROOT)/Bender.lock +SN_BENDER_YML = $(SN_ROOT)/Bender.yml +SN_BENDER_PREREQS = $(SN_BENDER_LOCK) +SN_BENDER_PREREQS += $(SN_BENDER_YML) # Flags SN_COMMON_BENDER_FLAGS += -t rtl -t cc_no_deprecated -t tech_cells_generic_include_tc_sync @@ -111,7 +114,7 @@ endef # Arg 5: name of target for which prerequisites are generated # Arg 6: additional prerequisites to generate Bender filelist define sn_gen_rtl_prerequisites -$(2)/$(4).f: $(SN_BENDER_YML) $(SN_BENDER_LOCK) $(SN_GEN_RTL_SRCS) $(6) | $(2) +$(2)/$(4).f: $(SN_BENDER_PREREQS) $(SN_GEN_RTL_SRCS) $(6) | $(2) $(SN_BENDER) script verilator $(3) > $$@ $(1): $(2)/$(4).f $(SN_GEN_RTL_SRCS) | $(2) @@ -127,5 +130,5 @@ endef # Usage: # $(call sn_include_deps) define sn_include_deps -$(eval $(if $(strip $(MAKECMDGOALS)),$(shell list-dependent-make-targets -M -r -f "$(MAKEOVERRIDES)" $(SN_DEPS)))) +$(eval $(if $(strip $(SN_DEPS)),$(if $(strip $(MAKECMDGOALS)),$(shell list-dependent-make-targets -M -r -f "$(MAKEOVERRIDES)" $(SN_DEPS))))) endef diff --git a/make/rtl.mk b/make/rtl.mk index 08cb5d8bd7..9e4c3b69d8 100644 --- a/make/rtl.mk +++ b/make/rtl.mk @@ -2,12 +2,20 @@ # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 +# bootrom build is dependent on toolchain.mk and must thus be deferred +# after the toolchain.mk file is included and read. +ifdef SN_TOOLCHAIN_MK_READ + +# Sentinel to test that rtl.mk has been included and read +SN_RTL_MK_READ = 1 + # Directories SN_BOOTROM_DIR ?= $(SN_HW_DIR)/bootrom # Templates SN_CLUSTER_WRAPPER_PKG_TPL = $(SN_HW_DIR)/snitch_cluster/src/snitch_cluster_wrapper_pkg.sv.tpl SN_CLUSTER_RDL_TPL = $(SN_HW_DIR)/snitch_cluster/src/snitch_cluster.rdl.tpl +SN_SPATZ_CFG_TPL = $(SN_HW_DIR)/snitch_cc/src/spatz_cfg.json.tpl # Generated RTL sources SN_CLUSTER_WRAPPER_PKG = $(SN_GEN_DIR)/snitch_cluster_wrapper_pkg.sv @@ -17,8 +25,14 @@ SN_CLUSTER_PERIPH_PKG = $(SN_PERIPH_DIR)/snitch_cluster_peripheral_reg_pkg.sv SN_BOOTROM = $(SN_BOOTROM_DIR)/snitch_bootrom.sv SN_CLUSTER_RDL = $(SN_GEN_DIR)/snitch_cluster.rdl +# Spatz package generation +SN_SPATZ_HW_DIR = $(shell $(SN_BENDER) path spatz_vpu)/hw +SN_SPATZ_CFG = $(SN_GEN_DIR)/spatz_cfg.json +SN_SPATZ_PKG_TPL = $(SN_SPATZ_HW_DIR)/src/spatz_pkg.sv.tpl +SN_SPATZ_PKG = $(SN_GEN_DIR)/spatz_pkg.sv + # All generated RTL sources -SN_GEN_RTL_SRCS = $(SN_CLUSTER_WRAPPER_PKG) $(SN_CLUSTER_ADDRMAP_SVH) $(SN_CLUSTER_PERIPH) $(SN_CLUSTER_PERIPH_PKG) $(SN_BOOTROM) +SN_GEN_RTL_SRCS = $(SN_CLUSTER_WRAPPER_PKG) $(SN_CLUSTER_ADDRMAP_SVH) $(SN_CLUSTER_PERIPH) $(SN_CLUSTER_PERIPH_PKG) $(SN_BOOTROM) $(SN_SPATZ_PKG) # Intermediate artifacts SN_BOOTROM_ELF = $(SN_BOOTROM_DIR)/bootrom.elf @@ -29,6 +43,16 @@ SN_BOOTROM_ARTIFACTS = $(SN_BOOTROM_ELF) $(SN_BOOTROM_DUMP) $(SN_BOOTROM_BIN) # CLUSTERGEN rules $(eval $(call sn_cluster_gen_rule,$(SN_CLUSTER_WRAPPER_PKG),$(SN_CLUSTER_WRAPPER_PKG_TPL))) $(eval $(call sn_cluster_gen_rule,$(SN_CLUSTER_RDL),$(SN_CLUSTER_RDL_TPL))) +$(eval $(call sn_cluster_gen_rule,$(SN_SPATZ_CFG),$(SN_SPATZ_CFG_TPL))) + +# Spatz package generation via the Spatz hw/Makefile flow: +# import_cfg.py extracts Spatz VFU fields from the cluster config, +# apply_cfg.py renders spatz_pkg.sv.tpl into the generated file. +$(SN_SPATZ_PKG): $(SN_SPATZ_CFG) $(SN_SPATZ_PKG_TPL) | $(SN_GEN_DIR) $(SN_SPATZ_HW_DIR) + @echo "[SPATZ] Generating $@" + cd $(SN_SPATZ_HW_DIR) && python import_cfg.py $(abspath $(SN_SPATZ_CFG)) + cd $(SN_SPATZ_HW_DIR) && python apply_cfg.py $(basename $(notdir $(SN_SPATZ_CFG))) + cp $(SN_SPATZ_HW_DIR)/src/generated/spatz_pkg.sv $@ # peakRDL rules $(SN_CLUSTER_PERIPH_PKG): $(SN_CLUSTER_PERIPH) @@ -39,12 +63,15 @@ $(SN_CLUSTER_ADDRMAP_SVH): $(SN_CLUSTER_RDL) @echo "[peakrdl] Generating $@" $(SN_PEAKRDL) raw-header $< -o $@ --format svh -I $(SN_PERIPH_DIR) -# Bootrom rules -$(SN_BOOTROM_ELF) $(SN_BOOTROM_DUMP) $(SN_BOOTROM_BIN) $(SN_BOOTROM): $(SN_BOOTROM_DIR)/bootrom.S $(SN_BOOTROM_DIR)/bootrom.ld $(SN_BOOTROM_GEN) | $(SN_BOOTROM_DIR) - $(SN_RISCV_CC) -mabi=ilp32d -march=rv32imafd -static -nostartfiles -fuse-ld=$(SN_RISCV_LD) -L$(SN_ROOT)/sw/runtime -T$(SN_BOOTROM_DIR)/bootrom.ld $< -o $(SN_BOOTROM_ELF) - $(SN_RISCV_OBJDUMP) -d $(SN_BOOTROM_ELF) > $(SN_BOOTROM_DUMP) - $(SN_RISCV_OBJCOPY) -j .text -O binary $(SN_BOOTROM_ELF) $(SN_BOOTROM_BIN) - $(SN_BOOTROM_GEN) --sv-module snitch_bootrom $(SN_BOOTROM_BIN) > $(SN_BOOTROM) +# Bootrom rules: explicit dependency on toolchain.mk ensures that the bootrom is rebuilt if the toolchain is updated +$(SN_BOOTROM_ELF): $(SN_BOOTROM_DIR)/bootrom.S $(SN_BOOTROM_DIR)/bootrom.ld $(SN_TOOLCHAIN_MK) | $(SN_BOOTROM_DIR) + $(SN_RISCV_CC) -mabi=ilp32d -march=rv32imafd -static -nostartfiles -fuse-ld=$(SN_RISCV_LD) -L$(SN_ROOT)/sw/runtime -T$(SN_BOOTROM_DIR)/bootrom.ld $< -o $@ +$(SN_BOOTROM_DUMP): $(SN_BOOTROM_ELF) + $(SN_RISCV_OBJDUMP) -d $< > $@ +$(SN_BOOTROM_BIN): $(SN_BOOTROM_ELF) + $(SN_RISCV_OBJCOPY) -j .text -O binary $< $@ +$(SN_BOOTROM): $(SN_BOOTROM_BIN) $(SN_BOOTROM_GEN) + $(SN_BOOTROM_GEN) --sv-module snitch_bootrom $< > $@ # General RTL targets .PHONY: sn-rtl sn-clean-rtl @@ -52,7 +79,9 @@ $(SN_BOOTROM_ELF) $(SN_BOOTROM_DUMP) $(SN_BOOTROM_BIN) $(SN_BOOTROM): $(SN_BOOTR sn-rtl: $(SN_GEN_RTL_SRCS) sn-clean-rtl: - rm -f $(SN_GEN_RTL_SRCS) $(SN_CLUSTER_RDL) $(SN_BOOTROM_ARTIFACTS) + rm -f $(SN_GEN_RTL_SRCS) $(SN_CLUSTER_RDL) $(SN_BOOTROM_ARTIFACTS) $(SN_SPATZ_CFG) $(SN_BOOTROM_DIR): mkdir -p $@ + +endif diff --git a/make/sw.mk b/make/sw.mk index 0be7258182..c78a326298 100644 --- a/make/sw.mk +++ b/make/sw.mk @@ -4,6 +4,10 @@ # # Luca Colagrande +# Software build is dependent on toolchain.mk and must thus be deferred +# after the toolchain.mk file is included and read. +ifdef SN_TOOLCHAIN_MK_READ + ################### # General targets # ################### @@ -64,7 +68,6 @@ sn-clean-headers: # Subdirectories # ################## -include $(SN_ROOT)/sw/toolchain.mk include $(SN_ROOT)/sw/runtime/runtime.mk include $(SN_ROOT)/sw/tests/tests.mk include $(SN_ROOT)/sw/riscv-tests/riscv-tests.mk @@ -77,6 +80,8 @@ SN_APPS += $(SN_ROOT)/sw/kernels/blas/gemm SN_APPS += $(SN_ROOT)/sw/kernels/blas/gemv SN_APPS += $(SN_ROOT)/sw/kernels/blas/dot SN_APPS += $(SN_ROOT)/sw/kernels/blas/syrk +SN_APPS += $(SN_ROOT)/sw/kernels/blas/spatz-axpy +SN_APPS += $(SN_ROOT)/sw/kernels/blas/spatz-fmatmul SN_APPS += $(SN_ROOT)/sw/kernels/dnn/batchnorm # SN_APPS += $(SN_ROOT)/sw/kernels/dnn/conv2d # SN_APPS += $(SN_ROOT)/sw/kernels/dnn/fusedconv @@ -107,3 +112,5 @@ endif $(foreach app,$(SN_APPS), \ $(eval include $(app)/app.mk) \ ) + +endif diff --git a/make/toolchain.mk b/make/toolchain.mk new file mode 100644 index 0000000000..7f9521c602 --- /dev/null +++ b/make/toolchain.mk @@ -0,0 +1,17 @@ +# Copyright 2020 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 +# +# Luca Colagrande + +SN_TOOLCHAIN_MK = $(SN_ROOT)/sw/toolchain.mk +SN_TOOLCHAIN_MK_TPL = $(SN_ROOT)/sw/toolchain.mk.tpl + +# Toolchain flags are generated from the cluster configuration +$(eval $(call sn_cluster_gen_rule,$(SN_TOOLCHAIN_MK),$(SN_TOOLCHAIN_MK_TPL))) + +include $(SN_TOOLCHAIN_MK) + +.PHONY: sn-clean-toolchain +sn-clean-toolchain: + rm -f $(SN_TOOLCHAIN_MK) diff --git a/make/vcs.mk b/make/vcs.mk index 54b43b0da6..981b079a10 100644 --- a/make/vcs.mk +++ b/make/vcs.mk @@ -2,6 +2,10 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 +# Simulation model build is dependent on rtl.mk and must thus be deferred +# after the rtl.mk file is included and read. +ifdef SN_RTL_MK_READ + ############# # Variables # ############# @@ -43,7 +47,7 @@ $(SN_VCS_BUILDDIR): $(eval $(call sn_gen_rtl_prerequisites,$(SN_VCS_RTL_PREREQ_FILE),$(SN_VCS_BUILDDIR),$(SN_VCS_BENDER_FLAGS),$(SN_VCS_TOP_MODULE),$(SN_BIN_DIR)/$(TARGET).vcs)) # Generate compilation script -$(SN_VCS_BUILDDIR)/compile.sh: $(SN_BENDER_YML) $(SN_BENDER_LOCK) | $(SN_VCS_BUILDDIR) +$(SN_VCS_BUILDDIR)/compile.sh: $(SN_BENDER_PREREQS) | $(SN_VCS_BUILDDIR) $(SN_BENDER) script vcs $(SN_VCS_BENDER_FLAGS) --vlog-arg="$(SN_VLOGAN_FLAGS)" --vcom-arg="$(SN_VHDLAN_FLAGS)" > $@ chmod +x $@ @@ -65,3 +69,5 @@ clean-vcs: clean-work clean: clean-vcs SN_DEPS += $(SN_VCS_RTL_PREREQ_FILE) + +endif \ No newline at end of file diff --git a/make/verilator.mk b/make/verilator.mk index 21ad3d3c29..767d51af0b 100644 --- a/make/verilator.mk +++ b/make/verilator.mk @@ -2,6 +2,10 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 +# Simulation model build is dependent on rtl.mk and must thus be deferred +# after the rtl.mk file is included and read. +ifdef SN_RTL_MK_READ + ####################### # Makefile invocation # ####################### @@ -21,7 +25,6 @@ SN_VLT_FESVR = $(SN_VLT_BUILDDIR)/riscv-isa-sim SN_VLT_BENDER_FLAGS += $(SN_COMMON_BENDER_FLAGS) -t snitch_cluster:tb -t verilator -DASSERTS_OFF SN_VLT_FLAGS += --timing SN_VLT_FLAGS += --timescale 1ns/1ps -SN_VLT_FLAGS += --trace-vcd SN_VLT_FLAGS += --no-assert-case SN_VLT_FLAGS += -Wno-BLKANDNBLK SN_VLT_FLAGS += -Wno-LITENDIAN @@ -35,6 +38,14 @@ SN_VLT_FLAGS += -Wno-fatal SN_VLT_FLAGS += --unroll-count 1024 SN_VLT_FLAGS += --threads $(SN_VLT_NUM_THREADS) +ifeq ($(DEBUG), ON) +SN_VLT_FLAGS += --trace-fst +ifneq ($(CI), ON) +SN_VLT_FLAGS += --trace-structs +SN_VLT_FLAGS += --trace-max-array 128 +endif +endif + # Misc SN_VLT_TOP_MODULE = testharness SN_VLT_RTL_PREREQ_FILE = $(SN_VLT_BUILDDIR)/$(SN_VLT_TOP_MODULE).d @@ -49,16 +60,20 @@ $(SN_VLT_BUILDDIR): # Generate RTL prerequisites $(eval $(call sn_gen_rtl_prerequisites,$(SN_VLT_RTL_PREREQ_FILE),$(SN_VLT_BUILDDIR),$(SN_VLT_BENDER_FLAGS),$(SN_VLT_TOP_MODULE),$(SN_BIN_DIR)/$(TARGET).vlt)) -# Generate and run compilation script, building the Verilator simulation binary -$(SN_BIN_DIR)/$(TARGET)_bin.vlt: $(SN_TB_CC_SOURCES) $(SN_VLT_CC_SOURCES) $(SN_WORK_DIR)/lib/libfesvr.a $(SN_VLT_RTL_PREREQ_FILE) | $(SN_BIN_DIR) $(SN_VLT_BUILDDIR) - $(SN_VLT) $(shell $(SN_BENDER) script verilator $(SN_VLT_BENDER_FLAGS)) \ +# Generate compilation arguments for Verilator +$(SN_VLT_BUILDDIR)/verilator.f: $(SN_BENDER_PREREQS) | $(SN_VLT_BUILDDIR) + $(SN_BENDER) script verilator $(SN_VLT_BENDER_FLAGS) > $@ + +# Build the Verilator simulation binary +$(SN_BIN_DIR)/$(TARGET)_bin.vlt: $(SN_VLT_BUILDDIR)/verilator.f $(SN_TB_CC_SOURCES) $(SN_VLT_CC_SOURCES) $(SN_WORK_DIR)/lib/libfesvr.a $(SN_VLT_RTL_PREREQ_FILE) | $(SN_BIN_DIR) $(SN_VLT_BUILDDIR) + $(SN_VLT) -f $< \ $(SN_VLT_FLAGS) --Mdir $(SN_VLT_BUILDDIR) \ -CFLAGS -std=c++20 \ -CFLAGS -I$(SN_WORK_DIR)/include \ -CFLAGS -I$(SN_TB_DIR) \ -j $(SN_VLT_JOBS) \ -o $@ --cc --exe --build --top-module $(SN_VLT_TOP_MODULE) \ - $(SN_TB_CC_SOURCES) $(SN_VLT_CC_SOURCES) $(SN_WORK_DIR)/lib/libfesvr.a | tee $(SN_VLT_BUILDDIR)/verilator.log + $(SN_TB_CC_SOURCES) $(SN_VLT_CC_SOURCES) $(SN_WORK_DIR)/lib/libfesvr.a 2>&1 | tee $(SN_VLT_BUILDDIR)/verilator.log # This target just redirects the verilator simulation binary. # On IIS machines, verilator needs to be built and run in @@ -78,3 +93,5 @@ clean-verilator: clean-work clean: clean-verilator SN_DEPS += $(SN_VLT_RTL_PREREQ_FILE) + +endif \ No newline at end of file diff --git a/make/vsim.mk b/make/vsim.mk index 63e47fc47d..e9d3d4ca88 100644 --- a/make/vsim.mk +++ b/make/vsim.mk @@ -2,6 +2,10 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 +# Simulation model build is dependent on rtl.mk and must thus be deferred +# after the rtl.mk file is included and read. +ifdef SN_RTL_MK_READ + ############# # Variables # ############# @@ -32,9 +36,12 @@ SN_VSIM_FLAGS += -t 1ps # DEBUG flag ensures visibility of all signals in the waveforms ifeq ($(DEBUG), ON) SN_VSIM_FLAGS += -do "log -r /*" -SN_VSIM_FLAGS += +define+DEBUG SN_VOPT_FLAGS = +acc endif +# TRACE flag allows to disable logging core traces (enabled by default) +ifeq ($(TRACE), OFF) +SN_VLOG_FLAGS += +define+TRACE_OFF +endif # GF12 physical simulation options ifeq ($(TECH),gf12) @@ -85,7 +92,7 @@ $(SN_VSIM_BUILDDIR): $(eval $(call sn_gen_rtl_prerequisites,$(SN_VSIM_RTL_PREREQ_FILE),$(SN_VSIM_BUILDDIR),$(SN_VSIM_BENDER_FLAGS),$(SN_VSIM_TOP_MODULE),$(SN_BIN_DIR)/$(TARGET).vsim)) # Generate compilation script -$(SN_VSIM_BUILDDIR)/compile.vsim.tcl: $(SN_BENDER_YML) $(SN_BENDER_LOCK) | $(SN_VSIM_BUILDDIR) +$(SN_VSIM_BUILDDIR)/compile.vsim.tcl: $(SN_BENDER_PREREQS) | $(SN_VSIM_BUILDDIR) $(SN_VLIB) $(dir $@) $(SN_BENDER) script vsim $(SN_VSIM_BENDER_FLAGS) --vlog-arg="$(SN_VLOG_FLAGS) " > $@ echo '$(SN_VLOG) -work $(SN_VSIM_BUILDDIR) $(SN_TB_CC_SOURCES) $(SN_RTL_CC_SOURCES) -vv -ccflags "$(SN_TB_CC_FLAGS)"' >> $@ @@ -126,3 +133,5 @@ clean-vsim: clean-work clean: clean-vsim SN_DEPS += $(SN_VSIM_RTL_PREREQ_FILE) + +endif \ No newline at end of file diff --git a/nonfree b/nonfree index 02887a1deb..5e6ced3932 160000 --- a/nonfree +++ b/nonfree @@ -1 +1 @@ -Subproject commit 02887a1deb7aad8f6218cc556cf30c63c43b0a76 +Subproject commit 5e6ced3932d9100542fd2835ecadea08bfcb8b1f diff --git a/pyproject.toml b/pyproject.toml index f412f81e02..506aa541ab 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -11,7 +11,7 @@ name = "snitch" authors = [ {name = "Luca Colagrande", email = "colluca@iis.ee.ethz.ch"} ] -requires-python = ">=3.11" +requires-python = ">=3.12" dynamic = ["version"] dependencies = [ # Alphabetically sorted. @@ -40,6 +40,7 @@ dependencies = [ "pyyaml", "reuse", "riscv-opcodes", + "spatz-vpu @ git+https://github.com/pulp-platform/spatz_vpu.git@0411cc6278d65bf46ca700ec5cde84cd681ce082", "tabulate", "termcolor", "yamllint", @@ -65,6 +66,11 @@ all = [ "snitch[kernels,docs]" ] +[dependency-groups] +dev = [ + "tsunami-wave @ git+https://github.com/zarubaf/tsunami.git@4a2d5c02462875fcebaef6f4e84563eb28b99cf8", +] + [tool.uv.sources] riscv-opcodes = { path = "sw/deps/riscv-opcodes", editable = true } torch = [ diff --git a/sw/.gitignore b/sw/.gitignore index 44bbda8b08..1d6449ce35 100644 --- a/sw/.gitignore +++ b/sw/.gitignore @@ -1,2 +1,3 @@ doxygen -build/ \ No newline at end of file +build/ +toolchain.mk \ No newline at end of file diff --git a/sw/kernels/blas/gemm/src/gemm_fp16.h b/sw/kernels/blas/gemm/src/gemm_fp16.h index 75dd3502bf..ec523984a2 100644 --- a/sw/kernels/blas/gemm/src/gemm_fp16.h +++ b/sw/kernels/blas/gemm/src/gemm_fp16.h @@ -11,6 +11,7 @@ void gemm_fp16_naive(uint32_t setup_ssr, uint32_t partition_banks, uint32_t transa, uint32_t transb, uint32_t M, uint32_t N, uint32_t K, void* A_p, uint32_t lda, void* B_p, uint32_t ldb, uint32_t beta, void* C_p, uint32_t ldc) { +#ifdef SNRT_SUPPORTS_SMALLFLOAT __fp16* A = (__fp16*)A_p; __fp16* B = (__fp16*)B_p; __fp16* C = (__fp16*)C_p; @@ -44,6 +45,7 @@ void gemm_fp16_naive(uint32_t setup_ssr, uint32_t partition_banks, C[m * ldc + n] = c; } } +#endif } void gemm_fp16_baseline(uint32_t setup_ssr, uint32_t transa, uint32_t transb, diff --git a/sw/kernels/blas/spatz-axpy/app.mk b/sw/kernels/blas/spatz-axpy/app.mk new file mode 100644 index 0000000000..3837fc53bb --- /dev/null +++ b/sw/kernels/blas/spatz-axpy/app.mk @@ -0,0 +1,14 @@ +# Copyright 2026 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +APP := spatz-axpy +$(APP)_BUILD_DIR ?= $(SN_ROOT)/sw/kernels/blas/$(APP)/build +SRC_DIR := $(SN_ROOT)/sw/kernels/blas/$(APP)/src +SRCS := $(SRC_DIR)/main.c + +include $(SN_ROOT)/sw/kernels/datagen.mk +# For layer.h, shared with the other spatz-* kernels +$(APP)_INCDIRS += $(DATA_DIR) + +include $(SN_ROOT)/sw/kernels/common.mk diff --git a/sw/kernels/blas/spatz-axpy/data/layer.h b/sw/kernels/blas/spatz-axpy/data/layer.h new file mode 100644 index 0000000000..eaf5d4d2a0 --- /dev/null +++ b/sw/kernels/blas/spatz-axpy/data/layer.h @@ -0,0 +1,146 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#pragma once + +#include +#include + +// precision_t is already defined in snitch runtime (sw/runtime/src/types.h) + +/** + * @struct gemm_layer_struct + * @brief This structure contains all parameters necessary for GEMM. + * @var gemm_layer_struct::M + * Dimension of matrix product MxK * KxN + * @var gemm_layer_struct::M_p + * M divided by number of compute cores + * @var gemm_layer_struct::N + * Dimension of matrix product MxK * KxN + * @var gemm_layer_struct::K + * Dimension of matrix product MxK * KxN + * @var gemm_layer_struct::TA + * Transpose matrix A + * @var gemm_layer_struct::TB + * Transpose matrix B + * @var gemm_layer_struct::TILE_M + * Tile factor across M dimension + * @var gemm_layer_struct::TILE_N + * Tile factor across N dimension + * @var gemm_layer_struct::TILE_K + * Tile factor across K dimension + * @var gemm_layer_struct::A + * Pointer to matrix A + * @var gemm_layer_struct::B + * Pointer to matrix B + * @var gemm_layer_struct::C + * Pointer to matrix C + * @var gemm_layer_struct::ALPHA + * constant factor: A * B + ALPHA * C + * @var gemm_layer_struct::dtype + * Precision of GEMM + * @var gemm_layer_struct::expand + * Use expanding DOTP instructions + */ +typedef struct gemm_layer_struct { + uint32_t M; + uint32_t M_p; + uint32_t N; + uint32_t K; + + uint32_t TA; + uint32_t TB; + + uint32_t TILE_M; + uint32_t TILE_N; + uint32_t TILE_K; + + double *A; + double *B; + double *C; + + uint32_t ALPHA; + + precision_t dtype; + uint32_t expand; +} gemm_layer; + +/** + * @struct conv_layer_struct + * @brief This structure contains all parameters necessary for Convolutional + * layers + * @var conv_layer_struct::CO + * Number of output channels + * @var conv_layer_struct::CI + * Number of input channels + * @var conv_layer_struct::IH + * Height of input feature map + * @var conv_layer_struct::IW + * Width of input feature map + * @var conv_layer_struct::OH + * Height of output feature map + * @var conv_layer_struct::OW + * Width of output feature map + * @var conv_layer_struct::FH + * Height of filter + * @var conv_layer_struct::FW + * Width of filter + * @var conv_layer_struct::pad + * Padding on all sides + * @var conv_layer_struct::ifmap + * Pointer to input feature map + * @var conv_layer_struct::weights + * Pointer to weights + * @var conv_layer_struct::ofmap + * Pointer to output feature map + * @var conv_layer_struct::TILE_CI + * Tiling factor of input channel + * @var conv_layer_struct::cluster2cluster + * Flag for enabling cluster 2 cluster communication + * @var conv_layer_struct::im2col + * Flag for enabling im2col + GEMM + * @var conv_layer_struct::gamma + * Pointer to gamma for BatchNorm + * @var conv_layer_struct::beta + * Pointer to beta for BatchNorm + * @var gemm_layer_struct::dtype + * Precision of Convolution layer + */ +typedef struct conv_layer_struct { + // CONV2D + uint32_t CO; + uint32_t CI; + uint32_t IH; + uint32_t IW; + uint32_t OH; + uint32_t OW; + uint32_t FH; + uint32_t FW; + uint32_t pad; + + double *ifmap; + double *weights; + double *ofmap; + + uint32_t TILE_CI; + uint32_t cluster2cluster; + uint32_t im2col; + + // BATCHNORM + double *gamma; + double *beta; + + precision_t dtype; +} conv_layer; + +/** + * @struct axpy_layer_struct + * @brief This structure contains all parameters necessary for AXPY layers + */ +typedef struct axpy_layer_struct { + // AXPY + uint32_t M; + + precision_t dtype; +} axpy_layer; diff --git a/sw/kernels/blas/spatz-axpy/data/params.json b/sw/kernels/blas/spatz-axpy/data/params.json new file mode 100644 index 0000000000..cc5180b268 --- /dev/null +++ b/sw/kernels/blas/spatz-axpy/data/params.json @@ -0,0 +1,8 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +{ + "m": 256, + "prec": "FP64" +} diff --git a/sw/kernels/blas/spatz-axpy/scripts/datagen.py b/sw/kernels/blas/spatz-axpy/scripts/datagen.py new file mode 100755 index 0000000000..349a1179fd --- /dev/null +++ b/sw/kernels/blas/spatz-axpy/scripts/datagen.py @@ -0,0 +1,52 @@ +#!/usr/bin/env python3 +# Copyright 2025 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +import sys + +import snitch.util.sim.data_utils as du + + +class SpatzAxpyDataGen(du.DataGen): + + def golden_model(self, alpha, x, y): + return alpha * x + y + + def emit_header(self, **kwargs): + header = [super().emit_header()] + + m = kwargs['m'] + prec = kwargs['prec'] + ctype = du.ctype_from_precision_t(prec) + + alpha = du.generate_random_array(1, prec=prec, seed=0)[0] + x = du.generate_random_array(m, prec=prec, seed=0) + y = du.generate_random_array(m, prec=prec, seed=0) + + cfg = { + 'M': m, + 'dtype': prec, + } + + # axpy_layer is defined in the shared layer.h, not generated here. + # The plain m/prec scalars below are for verify.py, which can't + # easily unpack fields out of the axpy_l struct directly. + header += ['#include "layer.h"'] + header += [du.format_scalar_definition('extern const uint32_t', 'm', m)] + header += [du.format_scalar_definition('extern const uint32_t', 'prec', + du.size_from_precision_t(prec))] + header += [du.format_struct_definition('const axpy_layer', 'axpy_l', cfg)] + header += [du.format_scalar_definition(f'extern const {ctype}', 'axpy_alpha_dram', alpha)] + header += [du.format_array_definition(ctype, 'axpy_X_dram', x, section=kwargs['section'])] + # axpy_Y_dram is also the kernel's output buffer: it's DMA'd in as the + # initial Y, then overwritten with the result at the end (verify.py + # reads it back post-simulation). + header += [du.format_array_definition(ctype, 'axpy_Y_dram', y, section=kwargs['section'])] + header = '\n\n'.join(header) + + return header + + +if __name__ == '__main__': + sys.exit(SpatzAxpyDataGen().main()) diff --git a/sw/kernels/blas/spatz-axpy/scripts/verify.py b/sw/kernels/blas/spatz-axpy/scripts/verify.py new file mode 100755 index 0000000000..9ef2dc1655 --- /dev/null +++ b/sw/kernels/blas/spatz-axpy/scripts/verify.py @@ -0,0 +1,42 @@ +#!/usr/bin/env python3 +# Copyright 2025 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +import sys +from datagen import SpatzAxpyDataGen + +from snitch.util.sim.verif_utils import Verifier +from snitch.util.sim.data_utils import ctype_from_precision_t + + +class SpatzAxpyVerifier(Verifier): + + OUTPUT_UIDS = ['axpy_Y_dram'] + ERR_THRESHOLD = { + 8: 1e-10, + 4: 1e-5, + 2: 5e-2, + } + + def __init__(self): + super().__init__() + self.prec = self.get_input_from_symbol('prec', 'uint32_t')[0] + + def get_actual_results(self): + return self.get_output_from_symbol(self.OUTPUT_UIDS[0], ctype_from_precision_t(self.prec)) + + def get_expected_results(self): + ctype = ctype_from_precision_t(self.prec) + alpha = self.get_input_from_symbol('axpy_alpha_dram', ctype)[0] + x = self.get_input_from_symbol('axpy_X_dram', ctype) + y = self.get_input_from_symbol('axpy_Y_dram', ctype) + + return SpatzAxpyDataGen().golden_model(alpha, x, y) + + def check_results(self, *args): + return super().check_results(*args, rtol=self.ERR_THRESHOLD[self.prec]) + + +if __name__ == "__main__": + sys.exit(SpatzAxpyVerifier().main()) diff --git a/sw/kernels/blas/spatz-axpy/src/faxpy.c b/sw/kernels/blas/spatz-axpy/src/faxpy.c new file mode 100644 index 0000000000..864d635a0e --- /dev/null +++ b/sw/kernels/blas/spatz-axpy/src/faxpy.c @@ -0,0 +1,150 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Matheus Cavalcante + +#include "faxpy.h" + +// 64-bit AXPY: y = a * x + y +void faxpy_v64b(const double a, const double *x, const double *y, + unsigned int avl) { + unsigned int vl; + + // Stripmine and accumulate a partial vector + do { + // Set the vl + asm volatile("vsetvli %0, %1, e64, m8, ta, ma" : "=r"(vl) : "r"(avl)); + + // Load vectors + asm volatile("vle64.v v0, (%0)" ::"r"(x)); + asm volatile("vle64.v v8, (%0)" ::"r"(y)); + + // Multiply-accumulate + asm volatile("vfmacc.vf v8, %0, v0" ::"f"(a)); + + // Store results + asm volatile("vse64.v v8, (%0)" ::"r"(y)); + + // Bump pointers + x += vl; + y += vl; + avl -= vl; + } while (avl > 0); +} + +// Unrolled 64-bit AXPY: y = a * x + y +void faxpy_v64b_unrl(const double a, const double *x, const double *y, + unsigned int avl) { + unsigned int vl; + const double *y2; + + // Stripmine and accumulate a partial vector + do { + // Set the vl + asm volatile("vsetvli %0, %1, e64, m8, ta, ma" : "=r"(vl) : "r"(avl)); + + // Load vectors + asm volatile("vle64.v v0, (%0)" ::"r"(x)); + asm volatile("vle64.v v8, (%0)" ::"r"(y)); + + // Multiply-accumulate + asm volatile("vfmacc.vf v8, %0, v0" ::"f"(a)); + avl -= vl; + if (avl > 0) { + // Set the vl + asm volatile("vsetvli %0, %1, e64, m8, ta, ma" + : "=r"(vl) + : "r"(avl)); + + // Load vectors + x += vl; + asm volatile("vle64.v v16, (%0)" ::"r"(x)); + y2 = y + vl; + asm volatile("vle64.v v24, (%0)" ::"r"(y2)); + + // Multiply-accumulate + asm volatile("vfmacc.vf v24, %0, v16" ::"f"(a)); + } + + // Store results + asm volatile("vse64.v v8, (%0)" ::"r"(y)); + if (avl > 0) { + // Store results + y += vl; + asm volatile("vse64.v v24, (%0)" ::"r"(y)); + avl -= vl; + } + + // Bump pointers + x += vl; + y += vl; + + } while (avl > 0); +} + +// 32-bit AXPY: y = a * x + y +void faxpy_v32b(const float a, const float *x, const float *y, + unsigned int avl) { + unsigned int vl; + + // Stripmine and accumulate a partial vector + do { + // Set the vl + asm volatile("vsetvli %0, %1, e32, m8, ta, ma" : "=r"(vl) : "r"(avl)); + + // Load vectors + asm volatile("vle32.v v0, (%0)" ::"r"(x)); + asm volatile("vle32.v v8, (%0)" ::"r"(y)); + + // Multiply-accumulate + asm volatile("vfmacc.vf v8, %0, v0" ::"f"(a)); + + // Store results + asm volatile("vse32.v v8, (%0)" ::"r"(y)); + + // Bump pointers + x += vl; + y += vl; + avl -= vl; + } while (avl > 0); +} + +// 16-bit AXPY: y = a * x + y +void faxpy_v16b(const _Float16 a, const _Float16 *x, const _Float16 *y, + unsigned int avl) { + unsigned int vl; + + // Stripmine and accumulate a partial vector + do { + // Set the vl + asm volatile("vsetvli %0, %1, e16, m8, ta, ma" : "=r"(vl) : "r"(avl)); + + // Load vectors + asm volatile("vle16.v v0, (%0)" ::"r"(x)); + asm volatile("vle16.v v8, (%0)" ::"r"(y)); + + // Multiply-accumulate + asm volatile("vfmacc.vf v8, %0, v0" ::"f"(a)); + + // Store results + asm volatile("vse16.v v8, (%0)" ::"r"(y)); + + // Bump pointers + x += vl; + y += vl; + avl -= vl; + } while (avl > 0); +} diff --git a/sw/kernels/blas/spatz-axpy/src/faxpy.h b/sw/kernels/blas/spatz-axpy/src/faxpy.h new file mode 100644 index 0000000000..a5166afa46 --- /dev/null +++ b/sw/kernels/blas/spatz-axpy/src/faxpy.h @@ -0,0 +1,31 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Matheus Cavalcante + +#ifndef _FAXPY_H_ +#define _FAXPY_H_ + +inline void faxpy_v64b(const double a, const double *x, const double *y, + unsigned int avl) __attribute__((always_inline)); +inline void faxpy_v64b_unrl(const double a, const double *x, const double *y, + unsigned int avl) __attribute__((always_inline)); +inline void faxpy_v32b(const float a, const float *x, const float *y, + unsigned int avl) __attribute__((always_inline)); +inline void faxpy_v16b(const _Float16 a, const _Float16 *x, const _Float16 *y, + unsigned int avl) __attribute__((always_inline)); + +#endif diff --git a/sw/kernels/blas/spatz-axpy/src/main.c b/sw/kernels/blas/spatz-axpy/src/main.c new file mode 100644 index 0000000000..297661eb16 --- /dev/null +++ b/sw/kernels/blas/spatz-axpy/src/main.c @@ -0,0 +1,104 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Matheus Cavalcante, ETH Zürich + +#include +#include + +#include "data.h" + +#ifndef SNRT_SUPPORTS_VECTOR +int main() { return 0; } +#else + +#include "faxpy.c" + +// Number of FPU lanes per Spatz core (matches N_FPU in spatz_pkg) +#ifndef SNRT_NFPU_PER_CORE +#define SNRT_NFPU_PER_CORE 8 +#endif + +double *a; +double *x; +double *y; + +int main() { + const unsigned int dim = axpy_l.M; + + // DM core: allocate L1 buffers and DMA data from DRAM + if (snrt_is_dm_core()) { + x = (double *)snrt_l1_alloc(dim * sizeof(double)); + y = (double *)snrt_l1_alloc(dim * sizeof(double)); + a = (double *)snrt_l1_alloc(sizeof(double)); + + *a = axpy_alpha_dram; + snrt_dma_start_1d(x, axpy_X_dram, dim * sizeof(double)); + snrt_dma_start_1d(y, axpy_Y_dram, dim * sizeof(double)); + snrt_dma_wait_all(); + } + + snrt_cluster_hw_barrier(); + + // DM core starts the performance counter + unsigned int timer = (unsigned int)-1; + if (snrt_is_dm_core()) { + timer = snrt_mcycle(); + } + + // Compute cores run the kernel, each on its own slice + if (snrt_is_compute_core()) { + const unsigned int compute_num = snrt_cluster_compute_core_num(); + const unsigned int compute_id = snrt_cluster_core_idx(); + const unsigned int dim_core = dim / compute_num; + + double *x_int = x + dim_core * compute_id; + double *y_int = y + dim_core * compute_id; + +#ifdef UNROLL + faxpy_v64b_unrl(*a, x_int, y_int, dim_core); +#else + faxpy_v64b(*a, x_int, y_int, dim_core); +#endif + } + + snrt_cluster_hw_barrier(); + + // DM core stops timer, prints performance, checks results + if (snrt_is_dm_core()) { + timer = snrt_mcycle() - timer; + + const unsigned int compute_num = snrt_cluster_compute_core_num(); + long unsigned int performance = 1000 * 2 * dim / timer; + long unsigned int utilization = + performance / (2 * compute_num * SNRT_NFPU_PER_CORE); + + printf("\n----- (%d) spatz-axpy -----\n", dim); + printf("Compute core: %d \n", compute_num); + printf("The execution took %u cycles.\n", timer); + printf("The performance is %ld OP/1000cycle (%ld%%o utilization).\n", + performance, utilization); + + // Write results back to DRAM; verify.py reads axpy_Y_dram post-simulation + snrt_dma_start_1d(axpy_Y_dram, y, dim * sizeof(double)); + snrt_dma_wait_all(); + } + + snrt_cluster_hw_barrier(); + + return 0; +} +#endif diff --git a/sw/kernels/blas/spatz-fmatmul/app.mk b/sw/kernels/blas/spatz-fmatmul/app.mk new file mode 100644 index 0000000000..930db1a448 --- /dev/null +++ b/sw/kernels/blas/spatz-fmatmul/app.mk @@ -0,0 +1,14 @@ +# Copyright 2026 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +APP := spatz-fmatmul +$(APP)_BUILD_DIR ?= $(SN_ROOT)/sw/kernels/blas/$(APP)/build +SRC_DIR := $(SN_ROOT)/sw/kernels/blas/$(APP)/src +SRCS := $(SRC_DIR)/main.c + +include $(SN_ROOT)/sw/kernels/datagen.mk +# For layer.h, shared with the other spatz-* kernels +$(APP)_INCDIRS += $(DATA_DIR) + +include $(SN_ROOT)/sw/kernels/common.mk diff --git a/sw/kernels/blas/spatz-fmatmul/data/layer.h b/sw/kernels/blas/spatz-fmatmul/data/layer.h new file mode 100644 index 0000000000..fba6210b36 --- /dev/null +++ b/sw/kernels/blas/spatz-fmatmul/data/layer.h @@ -0,0 +1,135 @@ +// Copyright 2020 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#pragma once + +#include +#include + +// precision_t is already defined in snitch runtime (sw/runtime/src/types.h) + +/** + * @struct gemm_layer_struct + * @brief This structure contains all parameters necessary for GEMM. + * @var gemm_layer_struct::M + * Dimension of matrix product MxK * KxN + * @var gemm_layer_struct::M_p + * M divided by number of compute cores + * @var gemm_layer_struct::N + * Dimension of matrix product MxK * KxN + * @var gemm_layer_struct::K + * Dimension of matrix product MxK * KxN + * @var gemm_layer_struct::TA + * Transpose matrix A + * @var gemm_layer_struct::TB + * Transpose matrix B + * @var gemm_layer_struct::TILE_M + * Tile factor across M dimension + * @var gemm_layer_struct::TILE_N + * Tile factor across N dimension + * @var gemm_layer_struct::TILE_K + * Tile factor across K dimension + * @var gemm_layer_struct::A + * Pointer to matrix A + * @var gemm_layer_struct::B + * Pointer to matrix B + * @var gemm_layer_struct::C + * Pointer to matrix C + * @var gemm_layer_struct::ALPHA + * constant factor: A * B + ALPHA * C + * @var gemm_layer_struct::dtype + * Precision of GEMM + * @var gemm_layer_struct::expand + * Use expanding DOTP instructions + */ +typedef struct gemm_layer_struct { + uint32_t M; + uint32_t M_p; + uint32_t N; + uint32_t K; + + uint32_t TA; + uint32_t TB; + + uint32_t TILE_M; + uint32_t TILE_N; + uint32_t TILE_K; + + double *A; + double *B; + double *C; + + uint32_t ALPHA; + + precision_t dtype; + uint32_t expand; +} gemm_layer; + +/** + * @struct conv_layer_struct + * @brief This structure contains all parameters necessary for Convolutional + * layers + * @var conv_layer_struct::CO + * Number of output channels + * @var conv_layer_struct::CI + * Number of input channels + * @var conv_layer_struct::IH + * Height of input feature map + * @var conv_layer_struct::IW + * Width of input feature map + * @var conv_layer_struct::OH + * Height of output feature map + * @var conv_layer_struct::OW + * Width of output feature map + * @var conv_layer_struct::FH + * Height of filter + * @var conv_layer_struct::FW + * Width of filter + * @var conv_layer_struct::pad + * Padding on all sides + * @var conv_layer_struct::ifmap + * Pointer to input feature map + * @var conv_layer_struct::weights + * Pointer to weights + * @var conv_layer_struct::ofmap + * Pointer to output feature map + * @var conv_layer_struct::TILE_CI + * Tiling factor of input channel + * @var conv_layer_struct::cluster2cluster + * Flag for enabling cluster 2 cluster communication + * @var conv_layer_struct::im2col + * Flag for enabling im2col + GEMM + * @var conv_layer_struct::gamma + * Pointer to gamma for BatchNorm + * @var conv_layer_struct::beta + * Pointer to beta for BatchNorm + * @var gemm_layer_struct::dtype + * Precision of Convolution layer + */ +typedef struct conv_layer_struct { + // CONV2D + uint32_t CO; + uint32_t CI; + uint32_t IH; + uint32_t IW; + uint32_t OH; + uint32_t OW; + uint32_t FH; + uint32_t FW; + uint32_t pad; + + double *ifmap; + double *weights; + double *ofmap; + + uint32_t TILE_CI; + uint32_t cluster2cluster; + uint32_t im2col; + + // BATCHNORM + double *gamma; + double *beta; + + precision_t dtype; +} conv_layer; diff --git a/sw/kernels/blas/spatz-fmatmul/data/params.json b/sw/kernels/blas/spatz-fmatmul/data/params.json new file mode 100644 index 0000000000..39b9d7b4a4 --- /dev/null +++ b/sw/kernels/blas/spatz-fmatmul/data/params.json @@ -0,0 +1,10 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +{ + "m": 64, + "n": 128, + "k": 64, + "prec": "FP32" +} diff --git a/sw/kernels/blas/spatz-fmatmul/scripts/datagen.py b/sw/kernels/blas/spatz-fmatmul/scripts/datagen.py new file mode 100755 index 0000000000..239a7732d1 --- /dev/null +++ b/sw/kernels/blas/spatz-fmatmul/scripts/datagen.py @@ -0,0 +1,70 @@ +#!/usr/bin/env python3 +# Copyright 2025 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +import sys + +import snitch.util.sim.data_utils as du + + +class FmatmulDataGen(du.DataGen): + + def golden_model(self, a, b): + return a @ b + + def validate(self, **kwargs): + prec_bytes = du.size_from_precision_t(kwargs['prec']) + total_size = (kwargs['m'] * kwargs['k'] + kwargs['k'] * kwargs['n'] + + kwargs['m'] * kwargs['n']) * prec_bytes + du.validate_tcdm_footprint(total_size) + + def emit_header(self, **kwargs): + header = [super().emit_header()] + + self.validate(**kwargs) + + m, n, k = kwargs['m'], kwargs['n'], kwargs['k'] + prec = kwargs['prec'] + ctype = du.ctype_from_precision_t(prec) + prec_bytes = du.size_from_precision_t(prec) + + a = du.generate_random_array((m, k), prec=prec, seed=42) + b = du.generate_random_array((k, n), prec=prec, seed=42) + c = du.generate_random_array((m, n), prec=prec, seed=42) + + cfg = { + 'M': m, + 'N': n, + 'K': k, + 'TA': 0, + 'TB': 0, + 'ALPHA': 0, + 'dtype': prec, + 'expand': 0, + } + + # gemm_layer is defined in the shared layer.h, not generated here. + # PREC (a preprocessor macro) drives main.c's choice of T and of + # which precision-specific kernel source it #includes. The plain + # m/n/k/prec scalars below are for verify.py, which can't easily + # unpack fields out of the gemm_l struct directly. + header += ['#include "layer.h"', f'#define PREC {prec_bytes * 8}'] + header += [du.format_scalar_definition('extern const uint32_t', 'm', m)] + header += [du.format_scalar_definition('extern const uint32_t', 'n', n)] + header += [du.format_scalar_definition('extern const uint32_t', 'k', k)] + header += [du.format_scalar_definition('extern const uint32_t', 'prec', prec_bytes)] + header += [du.format_struct_definition('const gemm_layer', 'gemm_l', cfg)] + header += [du.format_array_definition(ctype, 'gemm_A_dram', a, section=kwargs['section'])] + header += [du.format_array_definition(ctype, 'gemm_B_dram', b, section=kwargs['section'])] + # gemm_C_dram is also the kernel's output buffer: it's DMA'd in as the + # initial C, then overwritten with the result at the end (verify.py + # reads it back post-simulation). + header += [du.format_array_definition(ctype, 'gemm_C_dram', c, section=kwargs['section'])] + header = '\n\n'.join(header) + + return header + + +if __name__ == '__main__': + sys.exit(FmatmulDataGen().main()) diff --git a/sw/kernels/blas/spatz-fmatmul/scripts/verify.py b/sw/kernels/blas/spatz-fmatmul/scripts/verify.py new file mode 100755 index 0000000000..037e5d3684 --- /dev/null +++ b/sw/kernels/blas/spatz-fmatmul/scripts/verify.py @@ -0,0 +1,44 @@ +#!/usr/bin/env python3 +# Copyright 2025 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +import sys +from datagen import FmatmulDataGen + +from snitch.util.sim.verif_utils import Verifier +from snitch.util.sim.data_utils import ctype_from_precision_t + + +class FmatmulVerifier(Verifier): + + OUTPUT_UIDS = ['gemm_C_dram'] + ERR_THRESHOLD = { + 8: 1e-6, + 4: 1e-3, + 2: 5e-1, + } + + def __init__(self): + super().__init__() + self.prec = self.get_input_from_symbol('prec', 'uint32_t')[0] + + def get_actual_results(self): + return self.get_output_from_symbol(self.OUTPUT_UIDS[0], ctype_from_precision_t(self.prec)) + + def get_expected_results(self): + ctype = ctype_from_precision_t(self.prec) + m = self.get_input_from_symbol('m', 'uint32_t')[0] + n = self.get_input_from_symbol('n', 'uint32_t')[0] + k = self.get_input_from_symbol('k', 'uint32_t')[0] + a = self.get_input_from_symbol('gemm_A_dram', ctype).reshape(m, k) + b = self.get_input_from_symbol('gemm_B_dram', ctype).reshape(k, n) + + return FmatmulDataGen().golden_model(a, b).flatten() + + def check_results(self, *args): + return super().check_results(*args, rtol=self.ERR_THRESHOLD[self.prec]) + + +if __name__ == "__main__": + sys.exit(FmatmulVerifier().main()) diff --git a/sw/kernels/blas/spatz-fmatmul/src/fmatmul_fp32.c b/sw/kernels/blas/spatz-fmatmul/src/fmatmul_fp32.c new file mode 100644 index 0000000000..7bf31f1651 --- /dev/null +++ b/sw/kernels/blas/spatz-fmatmul/src/fmatmul_fp32.c @@ -0,0 +1,388 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Matheus Cavalcante, ETH Zurich + +#include "fmatmul_fp32.h" +#include + +#define MIN(a, b) ((a) < (b) ? (a) : (b)) + +void matmul(float *c, const float *a, const float *b, const unsigned int M, + const unsigned int N, const unsigned int P) { + if (M <= 4) { + matmul_2xVL(c, a, b, 0, M, N, P, 0, P); + } else if (M <= 8) { + matmul_4xVL(c, a, b, 0, M, N, P, 0, P); + } else { + matmul_8xVL(c, a, b, 0, M, N, P, 0, P); + } +} + +// --------------- +// 2xVL +// --------------- + +void matmul_2xVL(float *c, const float *a, const float *b, + const unsigned int m_start, const unsigned int m_end, + const unsigned int N, const unsigned int P, + const unsigned int p_start, const unsigned int p_end) { + unsigned int p = p_start; + while (p < p_end) { + // Calculate the vl + size_t gvl; + asm volatile("vsetvli %[gvl], %[vl], e32, m8, ta, ma" + : [ gvl ] "=r"(gvl) + : [ vl ] "r"(p_end - p)); + + const float *b_ = b + p; + float *c_ = c + p; + + for (unsigned int m = m_start; m < m_end; m += 2) { + const float *a_ = a + m * N; + const float *a__ = a_; + + asm volatile("vle32.v v16, (%0);" ::"r"(b_)); + const float *b__ = b_ + P; + + float *c__ = c_ + m * P; + + float t0, t1; + + t0 = *a__; + a__ += N; + t1 = *a__; + + unsigned int n = 0; + + while (n < N) { + a__ = a_ + ++n; + + asm volatile("vle32.v v24, (%0);" ::"r"(b__)); + b__ += P; + + if (n == 1) { + asm volatile("vfmul.vf v0, v16, %0" ::"f"(t0)); + t0 = *a__; + a__ += N; + asm volatile("vfmul.vf v8, v16, %0" ::"f"(t1)); + t1 = *a__; + } else { + asm volatile("vfmacc.vf v0, %0, v16" ::"f"(t0)); + t0 = *a__; + a__ += N; + asm volatile("vfmacc.vf v8, %0, v16" ::"f"(t1)); + t1 = *a__; + } + + a__ = a_ + ++n; + + if (n == N) break; + + asm volatile("vle32.v v16, (%0);" ::"r"(b__)); + b__ += P; + + asm volatile("vfmacc.vf v0, %0, v24" ::"f"(t0)); + t0 = *a__; + a__ += N; + asm volatile("vfmacc.vf v8, %0, v24" ::"f"(t1)); + t1 = *a__; + } + + asm volatile("vfmacc.vf v0, %0, v24" ::"f"(t0)); + asm volatile("vse32.v v0, (%0);" ::"r"(c__)); + c__ += P; + asm volatile("vfmacc.vf v8, %0, v24" ::"f"(t1)); + asm volatile("vse32.v v8, (%0);" ::"r"(c__)); + } + + p += gvl; + } +} + +// --------------- +// 4xVL +// --------------- + +void matmul_4xVL(float *c, const float *a, const float *b, + const unsigned int m_start, const unsigned int m_end, + const unsigned int N, const unsigned int P, + const unsigned int p_start, const unsigned int p_end) { + unsigned int p = p_start; + while (p < p_end) { + // Calculate the vl + size_t gvl; + asm volatile("vsetvli %[gvl], %[vl], e32, m4, ta, ma" + : [ gvl ] "=r"(gvl) + : [ vl ] "r"(p_end - p)); + + const float *b_ = b + p; + float *c_ = c + p; + + for (unsigned int m = m_start; m < m_end; m += 4) { + const float *a_ = a + m * N; + const float *a__ = a_; + + asm volatile("vle32.v v16, (%0);" ::"r"(b_)); + const float *b__ = b_ + P; + + float *c__ = c_ + m * P; + + float t0, t1, t2, t3; + + t0 = *a__; + a__ += N; + t1 = *a__; + a__ += N; + t2 = *a__; + a__ += N; + t3 = *a__; + + unsigned int n = 0; + + while (n < N) { + asm volatile("vle32.v v20, (%0);" ::"r"(b__)); + b__ += P; + + a__ = a_ + ++n; + + if (n == 1) { + asm volatile("vfmul.vf v0, v16, %0" ::"f"(t0)); + t0 = *a__; + a__ += N; + asm volatile("vfmul.vf v4, v16, %0" ::"f"(t1)); + t1 = *a__; + a__ += N; + asm volatile("vfmul.vf v8, v16, %0" ::"f"(t2)); + t2 = *a__; + a__ += N; + asm volatile("vfmul.vf v12, v16, %0" ::"f"(t3)); + t3 = *a__; + } else { + asm volatile("vfmacc.vf v0, %0, v16" ::"f"(t0)); + t0 = *a__; + a__ += N; + asm volatile("vfmacc.vf v4, %0, v16" ::"f"(t1)); + t1 = *a__; + a__ += N; + asm volatile("vfmacc.vf v8, %0, v16" ::"f"(t2)); + t2 = *a__; + a__ += N; + asm volatile("vfmacc.vf v12, %0, v16" ::"f"(t3)); + t3 = *a__; + } + + a__ = a_ + ++n; + + if (n == N) break; + + asm volatile("vle32.v v16, (%0);" ::"r"(b__)); + b__ += P; + + asm volatile("vfmacc.vf v0, %0, v20" ::"f"(t0)); + t0 = *a__; + a__ += N; + asm volatile("vfmacc.vf v4, %0, v20" ::"f"(t1)); + t1 = *a__; + a__ += N; + asm volatile("vfmacc.vf v8, %0, v20" ::"f"(t2)); + t2 = *a__; + a__ += N; + asm volatile("vfmacc.vf v12, %0, v20" ::"f"(t3)); + t3 = *a__; + } + + asm volatile("vfmacc.vf v0, %0, v20" ::"f"(t0)); + asm volatile("vse32.v v0, (%0);" ::"r"(c__)); + c__ += P; + asm volatile("vfmacc.vf v4, %0, v20" ::"f"(t1)); + asm volatile("vse32.v v4, (%0);" ::"r"(c__)); + c__ += P; + asm volatile("vfmacc.vf v8, %0, v20" ::"f"(t2)); + asm volatile("vse32.v v8, (%0);" ::"r"(c__)); + c__ += P; + asm volatile("vfmacc.vf v12, %0, v20" ::"f"(t3)); + asm volatile("vse32.v v12, (%0);" ::"r"(c__)); + } + + p += gvl; + } +} + +// --------------- +// 8xVL +// --------------- + +void matmul_8xVL(float *c, const float *a, const float *b, + const unsigned int m_start, const unsigned int m_end, + const unsigned int N, const unsigned int P, + const unsigned int p_start, const unsigned int p_end) { + unsigned int p = p_start; + while (p < p_end) { + // Calculate the vl + size_t gvl; + asm volatile("vsetvli %[gvl], %[vl], e32, m2, ta, ma" + : [ gvl ] "=r"(gvl) + : [ vl ] "r"(p_end - p)); + + const float *b_ = b + p; + float *c_ = c + p; + + for (unsigned int m = m_start; m < m_end; m += 8) { + const float *a_ = a + m * N; + const float *a__ = a_; + + asm volatile("vle32.v v18, (%0);" ::"r"(b_)); + const float *b__ = b_ + P; + + float *c__ = c_ + m * P; + + float t0, t1, t2, t3, t4, t5, t6, t7; + + t0 = *a__; + a__ += N; + t1 = *a__; + a__ += N; + t2 = *a__; + a__ += N; + t3 = *a__; + a__ += N; + t4 = *a__; + a__ += N; + t5 = *a__; + a__ += N; + t6 = *a__; + a__ += N; + t7 = *a__; + + unsigned int n = 0; + + while (n < N) { + a__ = a_ + ++n; + + asm volatile("vle32.v v20, (%0);" ::"r"(b__)); + b__ += P; + + if (n == 1) { + asm volatile("vfmul.vf v0, v18, %0" ::"f"(t0)); + t0 = *a__; + a__ += N; + asm volatile("vfmul.vf v2, v18, %0" ::"f"(t1)); + t1 = *a__; + a__ += N; + asm volatile("vfmul.vf v4, v18, %0" ::"f"(t2)); + t2 = *a__; + a__ += N; + asm volatile("vfmul.vf v6, v18, %0" ::"f"(t3)); + t3 = *a__; + a__ += N; + asm volatile("vfmul.vf v8, v18, %0" ::"f"(t4)); + t4 = *a__; + a__ += N; + asm volatile("vfmul.vf v10, v18, %0" ::"f"(t5)); + t5 = *a__; + a__ += N; + asm volatile("vfmul.vf v12, v18, %0" ::"f"(t6)); + t6 = *a__; + a__ += N; + asm volatile("vfmul.vf v14, v18, %0" ::"f"(t7)); + t7 = *a__; + } else { + asm volatile("vfmacc.vf v0, %0, v18" ::"f"(t0)); + t0 = *a__; + a__ += N; + asm volatile("vfmacc.vf v2, %0, v18" ::"f"(t1)); + t1 = *a__; + a__ += N; + asm volatile("vfmacc.vf v4, %0, v18" ::"f"(t2)); + t2 = *a__; + a__ += N; + asm volatile("vfmacc.vf v6, %0, v18" ::"f"(t3)); + t3 = *a__; + a__ += N; + asm volatile("vfmacc.vf v8, %0, v18" ::"f"(t4)); + t4 = *a__; + a__ += N; + asm volatile("vfmacc.vf v10, %0, v18" ::"f"(t5)); + t5 = *a__; + a__ += N; + asm volatile("vfmacc.vf v12, %0, v18" ::"f"(t6)); + t6 = *a__; + a__ += N; + asm volatile("vfmacc.vf v14, %0, v18" ::"f"(t7)); + t7 = *a__; + } + + a__ = a_ + ++n; + + if (n == N) break; + + asm volatile("vle32.v v18, (%0);" ::"r"(b__)); + b__ += P; + + asm volatile("vfmacc.vf v0, %0, v20" ::"f"(t0)); + t0 = *a__; + a__ += N; + asm volatile("vfmacc.vf v2, %0, v20" ::"f"(t1)); + t1 = *a__; + a__ += N; + asm volatile("vfmacc.vf v4, %0, v20" ::"f"(t2)); + t2 = *a__; + a__ += N; + asm volatile("vfmacc.vf v6, %0, v20" ::"f"(t3)); + t3 = *a__; + a__ += N; + asm volatile("vfmacc.vf v8, %0, v20" ::"f"(t4)); + t4 = *a__; + a__ += N; + asm volatile("vfmacc.vf v10, %0, v20" ::"f"(t5)); + t5 = *a__; + a__ += N; + asm volatile("vfmacc.vf v12, %0, v20" ::"f"(t6)); + t6 = *a__; + a__ += N; + asm volatile("vfmacc.vf v14, %0, v20" ::"f"(t7)); + t7 = *a__; + } + + asm volatile("vfmacc.vf v0, %0, v20" ::"f"(t0)); + asm volatile("vse32.v v0, (%0);" ::"r"(c__)); + c__ += P; + asm volatile("vfmacc.vf v2, %0, v20" ::"f"(t1)); + asm volatile("vse32.v v2, (%0);" ::"r"(c__)); + c__ += P; + asm volatile("vfmacc.vf v4, %0, v20" ::"f"(t2)); + asm volatile("vse32.v v4, (%0);" ::"r"(c__)); + c__ += P; + asm volatile("vfmacc.vf v6, %0, v20" ::"f"(t3)); + asm volatile("vse32.v v6, (%0);" ::"r"(c__)); + c__ += P; + asm volatile("vfmacc.vf v8, %0, v20" ::"f"(t4)); + asm volatile("vse32.v v8, (%0);" ::"r"(c__)); + c__ += P; + asm volatile("vfmacc.vf v10, %0, v20" ::"f"(t5)); + asm volatile("vse32.v v10, (%0);" ::"r"(c__)); + c__ += P; + asm volatile("vfmacc.vf v12, %0, v20" ::"f"(t6)); + asm volatile("vse32.v v12, (%0);" ::"r"(c__)); + c__ += P; + asm volatile("vfmacc.vf v14, %0, v20" ::"f"(t7)); + asm volatile("vse32.v v14, (%0);" ::"r"(c__)); + } + + p += gvl; + } +} diff --git a/sw/kernels/blas/spatz-fmatmul/src/fmatmul_fp32.h b/sw/kernels/blas/spatz-fmatmul/src/fmatmul_fp32.h new file mode 100644 index 0000000000..e533e65e16 --- /dev/null +++ b/sw/kernels/blas/spatz-fmatmul/src/fmatmul_fp32.h @@ -0,0 +1,45 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Matheus Cavalcante, ETH Zurich + +#ifndef FMATMUL_FP32_H +#define FMATMUL_FP32_H + +void matmul(float *c, const float *a, const float *b, const unsigned int M, + const unsigned int N, const unsigned int P); + +inline void matmul_single_unrolled(float *c, const float *a, const float *b, + const unsigned int N, const unsigned int P, + unsigned int vl) + __attribute__((always_inline)); +inline void matmul_2xVL(float *c, const float *a, const float *b, + const unsigned int m_start, const unsigned int m_end, + const unsigned int N, const unsigned int P, + const unsigned int p_start, const unsigned int p_end) + __attribute__((always_inline)); +inline void matmul_4xVL(float *c, const float *a, const float *b, + const unsigned int m_start, const unsigned int m_end, + const unsigned int N, const unsigned int P, + const unsigned int p_start, const unsigned int p_end) + __attribute__((always_inline)); +inline void matmul_8xVL(float *c, const float *a, const float *b, + const unsigned int m_start, const unsigned int m_end, + const unsigned int N, const unsigned int P, + const unsigned int p_start, const unsigned int p_end) + __attribute__((always_inline)); + +#endif diff --git a/sw/kernels/blas/spatz-fmatmul/src/fmatmul_fp64.c b/sw/kernels/blas/spatz-fmatmul/src/fmatmul_fp64.c new file mode 100644 index 0000000000..ffe24742b2 --- /dev/null +++ b/sw/kernels/blas/spatz-fmatmul/src/fmatmul_fp64.c @@ -0,0 +1,388 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Matheus Cavalcante, ETH Zurich + +#include "fmatmul_fp64.h" +#include + +#define MIN(a, b) ((a) < (b) ? (a) : (b)) + +void matmul(double *c, const double *a, const double *b, const unsigned int M, + const unsigned int N, const unsigned int P) { + if (M <= 4) { + matmul_2xVL(c, a, b, 0, M, N, P, 0, P); + } else if (M <= 8) { + matmul_4xVL(c, a, b, 0, M, N, P, 0, P); + } else { + matmul_8xVL(c, a, b, 0, M, N, P, 0, P); + } +} + +// --------------- +// 2xVL +// --------------- + +void matmul_2xVL(double *c, const double *a, const double *b, + const unsigned int m_start, const unsigned int m_end, + const unsigned int N, const unsigned int P, + const unsigned int p_start, const unsigned int p_end) { + unsigned int p = p_start; + while (p < p_end) { + // Calculate the vl + size_t gvl; + asm volatile("vsetvli %[gvl], %[vl], e64, m8, ta, ma" + : [ gvl ] "=r"(gvl) + : [ vl ] "r"(p_end - p)); + + const double *b_ = b + p; + double *c_ = c + p; + + for (unsigned int m = m_start; m < m_end; m += 2) { + const double *a_ = a + m * N; + const double *a__ = a_; + + asm volatile("vle64.v v16, (%0);" ::"r"(b_)); + const double *b__ = b_ + P; + + double *c__ = c_ + m * P; + + double t0, t1; + + t0 = *a__; + a__ += N; + t1 = *a__; + + unsigned int n = 0; + + while (n < N) { + a__ = a_ + ++n; + + asm volatile("vle64.v v24, (%0);" ::"r"(b__)); + b__ += P; + + if (n == 1) { + asm volatile("vfmul.vf v0, v16, %0" ::"f"(t0)); + t0 = *a__; + a__ += N; + asm volatile("vfmul.vf v8, v16, %0" ::"f"(t1)); + t1 = *a__; + } else { + asm volatile("vfmacc.vf v0, %0, v16" ::"f"(t0)); + t0 = *a__; + a__ += N; + asm volatile("vfmacc.vf v8, %0, v16" ::"f"(t1)); + t1 = *a__; + } + + a__ = a_ + ++n; + + if (n == N) break; + + asm volatile("vle64.v v16, (%0);" ::"r"(b__)); + b__ += P; + + asm volatile("vfmacc.vf v0, %0, v24" ::"f"(t0)); + t0 = *a__; + a__ += N; + asm volatile("vfmacc.vf v8, %0, v24" ::"f"(t1)); + t1 = *a__; + } + + asm volatile("vfmacc.vf v0, %0, v24" ::"f"(t0)); + asm volatile("vse64.v v0, (%0);" ::"r"(c__)); + c__ += P; + asm volatile("vfmacc.vf v8, %0, v24" ::"f"(t1)); + asm volatile("vse64.v v8, (%0);" ::"r"(c__)); + } + + p += gvl; + } +} + +// --------------- +// 4xVL +// --------------- + +void matmul_4xVL(double *c, const double *a, const double *b, + const unsigned int m_start, const unsigned int m_end, + const unsigned int N, const unsigned int P, + const unsigned int p_start, const unsigned int p_end) { + unsigned int p = p_start; + while (p < p_end) { + // Calculate the vl + size_t gvl; + asm volatile("vsetvli %[gvl], %[vl], e64, m4, ta, ma" + : [ gvl ] "=r"(gvl) + : [ vl ] "r"(p_end - p)); + + const double *b_ = b + p; + double *c_ = c + p; + + for (unsigned int m = m_start; m < m_end; m += 4) { + const double *a_ = a + m * N; + const double *a__ = a_; + + asm volatile("vle64.v v16, (%0);" ::"r"(b_)); + const double *b__ = b_ + P; + + double *c__ = c_ + m * P; + + double t0, t1, t2, t3; + + t0 = *a__; + a__ += N; + t1 = *a__; + a__ += N; + t2 = *a__; + a__ += N; + t3 = *a__; + + unsigned int n = 0; + + while (n < N) { + asm volatile("vle64.v v20, (%0);" ::"r"(b__)); + b__ += P; + + a__ = a_ + ++n; + + if (n == 1) { + asm volatile("vfmul.vf v0, v16, %0" ::"f"(t0)); + t0 = *a__; + a__ += N; + asm volatile("vfmul.vf v4, v16, %0" ::"f"(t1)); + t1 = *a__; + a__ += N; + asm volatile("vfmul.vf v8, v16, %0" ::"f"(t2)); + t2 = *a__; + a__ += N; + asm volatile("vfmul.vf v12, v16, %0" ::"f"(t3)); + t3 = *a__; + } else { + asm volatile("vfmacc.vf v0, %0, v16" ::"f"(t0)); + t0 = *a__; + a__ += N; + asm volatile("vfmacc.vf v4, %0, v16" ::"f"(t1)); + t1 = *a__; + a__ += N; + asm volatile("vfmacc.vf v8, %0, v16" ::"f"(t2)); + t2 = *a__; + a__ += N; + asm volatile("vfmacc.vf v12, %0, v16" ::"f"(t3)); + t3 = *a__; + } + + a__ = a_ + ++n; + + if (n == N) break; + + asm volatile("vle64.v v16, (%0);" ::"r"(b__)); + b__ += P; + + asm volatile("vfmacc.vf v0, %0, v20" ::"f"(t0)); + t0 = *a__; + a__ += N; + asm volatile("vfmacc.vf v4, %0, v20" ::"f"(t1)); + t1 = *a__; + a__ += N; + asm volatile("vfmacc.vf v8, %0, v20" ::"f"(t2)); + t2 = *a__; + a__ += N; + asm volatile("vfmacc.vf v12, %0, v20" ::"f"(t3)); + t3 = *a__; + } + + asm volatile("vfmacc.vf v0, %0, v20" ::"f"(t0)); + asm volatile("vse64.v v0, (%0);" ::"r"(c__)); + c__ += P; + asm volatile("vfmacc.vf v4, %0, v20" ::"f"(t1)); + asm volatile("vse64.v v4, (%0);" ::"r"(c__)); + c__ += P; + asm volatile("vfmacc.vf v8, %0, v20" ::"f"(t2)); + asm volatile("vse64.v v8, (%0);" ::"r"(c__)); + c__ += P; + asm volatile("vfmacc.vf v12, %0, v20" ::"f"(t3)); + asm volatile("vse64.v v12, (%0);" ::"r"(c__)); + } + + p += gvl; + } +} + +// --------------- +// 8xVL +// --------------- + +void matmul_8xVL(double *c, const double *a, const double *b, + const unsigned int m_start, const unsigned int m_end, + const unsigned int N, const unsigned int P, + const unsigned int p_start, const unsigned int p_end) { + unsigned int p = p_start; + while (p < p_end) { + // Calculate the vl + size_t gvl; + asm volatile("vsetvli %[gvl], %[vl], e64, m2, ta, ma" + : [ gvl ] "=r"(gvl) + : [ vl ] "r"(p_end - p)); + + const double *b_ = b + p; + double *c_ = c + p; + + for (unsigned int m = m_start; m < m_end; m += 8) { + const double *a_ = a + m * N; + const double *a__ = a_; + + asm volatile("vle64.v v18, (%0);" ::"r"(b_)); + const double *b__ = b_ + P; + + double *c__ = c_ + m * P; + + double t0, t1, t2, t3, t4, t5, t6, t7; + + t0 = *a__; + a__ += N; + t1 = *a__; + a__ += N; + t2 = *a__; + a__ += N; + t3 = *a__; + a__ += N; + t4 = *a__; + a__ += N; + t5 = *a__; + a__ += N; + t6 = *a__; + a__ += N; + t7 = *a__; + + unsigned int n = 0; + + while (n < N) { + a__ = a_ + ++n; + + asm volatile("vle64.v v20, (%0);" ::"r"(b__)); + b__ += P; + + if (n == 1) { + asm volatile("vfmul.vf v0, v18, %0" ::"f"(t0)); + t0 = *a__; + a__ += N; + asm volatile("vfmul.vf v2, v18, %0" ::"f"(t1)); + t1 = *a__; + a__ += N; + asm volatile("vfmul.vf v4, v18, %0" ::"f"(t2)); + t2 = *a__; + a__ += N; + asm volatile("vfmul.vf v6, v18, %0" ::"f"(t3)); + t3 = *a__; + a__ += N; + asm volatile("vfmul.vf v8, v18, %0" ::"f"(t4)); + t4 = *a__; + a__ += N; + asm volatile("vfmul.vf v10, v18, %0" ::"f"(t5)); + t5 = *a__; + a__ += N; + asm volatile("vfmul.vf v12, v18, %0" ::"f"(t6)); + t6 = *a__; + a__ += N; + asm volatile("vfmul.vf v14, v18, %0" ::"f"(t7)); + t7 = *a__; + } else { + asm volatile("vfmacc.vf v0, %0, v18" ::"f"(t0)); + t0 = *a__; + a__ += N; + asm volatile("vfmacc.vf v2, %0, v18" ::"f"(t1)); + t1 = *a__; + a__ += N; + asm volatile("vfmacc.vf v4, %0, v18" ::"f"(t2)); + t2 = *a__; + a__ += N; + asm volatile("vfmacc.vf v6, %0, v18" ::"f"(t3)); + t3 = *a__; + a__ += N; + asm volatile("vfmacc.vf v8, %0, v18" ::"f"(t4)); + t4 = *a__; + a__ += N; + asm volatile("vfmacc.vf v10, %0, v18" ::"f"(t5)); + t5 = *a__; + a__ += N; + asm volatile("vfmacc.vf v12, %0, v18" ::"f"(t6)); + t6 = *a__; + a__ += N; + asm volatile("vfmacc.vf v14, %0, v18" ::"f"(t7)); + t7 = *a__; + } + + a__ = a_ + ++n; + + if (n == N) break; + + asm volatile("vle64.v v18, (%0);" ::"r"(b__)); + b__ += P; + + asm volatile("vfmacc.vf v0, %0, v20" ::"f"(t0)); + t0 = *a__; + a__ += N; + asm volatile("vfmacc.vf v2, %0, v20" ::"f"(t1)); + t1 = *a__; + a__ += N; + asm volatile("vfmacc.vf v4, %0, v20" ::"f"(t2)); + t2 = *a__; + a__ += N; + asm volatile("vfmacc.vf v6, %0, v20" ::"f"(t3)); + t3 = *a__; + a__ += N; + asm volatile("vfmacc.vf v8, %0, v20" ::"f"(t4)); + t4 = *a__; + a__ += N; + asm volatile("vfmacc.vf v10, %0, v20" ::"f"(t5)); + t5 = *a__; + a__ += N; + asm volatile("vfmacc.vf v12, %0, v20" ::"f"(t6)); + t6 = *a__; + a__ += N; + asm volatile("vfmacc.vf v14, %0, v20" ::"f"(t7)); + t7 = *a__; + } + + asm volatile("vfmacc.vf v0, %0, v20" ::"f"(t0)); + asm volatile("vse64.v v0, (%0);" ::"r"(c__)); + c__ += P; + asm volatile("vfmacc.vf v2, %0, v20" ::"f"(t1)); + asm volatile("vse64.v v2, (%0);" ::"r"(c__)); + c__ += P; + asm volatile("vfmacc.vf v4, %0, v20" ::"f"(t2)); + asm volatile("vse64.v v4, (%0);" ::"r"(c__)); + c__ += P; + asm volatile("vfmacc.vf v6, %0, v20" ::"f"(t3)); + asm volatile("vse64.v v6, (%0);" ::"r"(c__)); + c__ += P; + asm volatile("vfmacc.vf v8, %0, v20" ::"f"(t4)); + asm volatile("vse64.v v8, (%0);" ::"r"(c__)); + c__ += P; + asm volatile("vfmacc.vf v10, %0, v20" ::"f"(t5)); + asm volatile("vse64.v v10, (%0);" ::"r"(c__)); + c__ += P; + asm volatile("vfmacc.vf v12, %0, v20" ::"f"(t6)); + asm volatile("vse64.v v12, (%0);" ::"r"(c__)); + c__ += P; + asm volatile("vfmacc.vf v14, %0, v20" ::"f"(t7)); + asm volatile("vse64.v v14, (%0);" ::"r"(c__)); + } + + p += gvl; + } +} diff --git a/sw/kernels/blas/spatz-fmatmul/src/fmatmul_fp64.h b/sw/kernels/blas/spatz-fmatmul/src/fmatmul_fp64.h new file mode 100644 index 0000000000..5deb6fa206 --- /dev/null +++ b/sw/kernels/blas/spatz-fmatmul/src/fmatmul_fp64.h @@ -0,0 +1,45 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Matheus Cavalcante, ETH Zurich + +#ifndef FMATMUL_FP64_H +#define FMATMUL_FP64_H + +void matmul(double *c, const double *a, const double *b, const unsigned int M, + const unsigned int N, const unsigned int P); + +inline void matmul_single_unrolled(double *c, const double *a, const double *b, + const unsigned int N, const unsigned int P, + unsigned int vl) + __attribute__((always_inline)); +inline void matmul_2xVL(double *c, const double *a, const double *b, + const unsigned int m_start, const unsigned int m_end, + const unsigned int N, const unsigned int P, + const unsigned int p_start, const unsigned int p_end) + __attribute__((always_inline)); +inline void matmul_4xVL(double *c, const double *a, const double *b, + const unsigned int m_start, const unsigned int m_end, + const unsigned int N, const unsigned int P, + const unsigned int p_start, const unsigned int p_end) + __attribute__((always_inline)); +inline void matmul_8xVL(double *c, const double *a, const double *b, + const unsigned int m_start, const unsigned int m_end, + const unsigned int N, const unsigned int P, + const unsigned int p_start, const unsigned int p_end) + __attribute__((always_inline)); + +#endif diff --git a/sw/kernels/blas/spatz-fmatmul/src/main.c b/sw/kernels/blas/spatz-fmatmul/src/main.c new file mode 100644 index 0000000000..b9d9d110b4 --- /dev/null +++ b/sw/kernels/blas/spatz-fmatmul/src/main.c @@ -0,0 +1,117 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Author: Matheus Cavalcante, ETH Zurich + +#include +#include + +#include "data.h" + +#ifndef SNRT_SUPPORTS_VECTOR +int main() { return 0; } +#else + +#if (PREC == 64) +typedef double T; +#include "fmatmul_fp64.c" +#elif (PREC == 32) +typedef float T; +#include "fmatmul_fp32.c" +#elif (PREC == 16) +typedef __fp16 T; +#include "fmatmul_fp16.c" +#endif + +// Number of FPU lanes per Spatz core (matches N_FPU in spatz_pkg) +#ifndef SNRT_NFPU_PER_CORE +#define SNRT_NFPU_PER_CORE 8 +#endif + +T *a; +T *b; +T *c; + +int main() { + // DM core: allocate L1 buffers and DMA data from DRAM + if (snrt_is_dm_core()) { + a = (T *)snrt_l1_alloc(gemm_l.M * gemm_l.K * sizeof(T)); + b = (T *)snrt_l1_alloc(gemm_l.K * gemm_l.N * sizeof(T)); + c = (T *)snrt_l1_alloc(gemm_l.M * gemm_l.N * sizeof(T)); + + snrt_dma_start_1d(a, gemm_A_dram, gemm_l.M * gemm_l.K * sizeof(T)); + snrt_dma_start_1d(b, gemm_B_dram, gemm_l.K * gemm_l.N * sizeof(T)); + snrt_dma_start_1d(c, gemm_C_dram, gemm_l.M * gemm_l.N * sizeof(T)); + snrt_dma_wait_all(); + } + + snrt_cluster_hw_barrier(); + + // DM core starts performance counter + unsigned int timer = (unsigned int)-1; + if (snrt_is_dm_core()) { + timer = snrt_mcycle(); + } + + // Compute cores run the kernel, each on its own row slice + if (snrt_is_compute_core()) { + const unsigned int compute_num = snrt_cluster_compute_core_num(); + const unsigned int compute_id = snrt_cluster_core_idx(); + + const unsigned int m_start = (gemm_l.M / compute_num) * compute_id; + const unsigned int m_end = (gemm_l.M / compute_num) * (compute_id + 1); + const unsigned int p_start = 0; + const unsigned int p_end = gemm_l.N; + + matmul_4xVL(c, a, b, m_start, m_end, gemm_l.K, gemm_l.N, p_start, + p_end); + } + + snrt_cluster_hw_barrier(); + + // DM core stops timer, prints performance, checks results + if (snrt_is_dm_core()) { + timer = snrt_mcycle() - timer; + + const unsigned int compute_num = snrt_cluster_compute_core_num(); + long unsigned int performance = + 1000 * 2 * gemm_l.M * gemm_l.N * gemm_l.K / timer; +// fp32 packs twice as many elements per FPU lane as fp64, doubling peak ops/cycle +#if (PREC == 32) + long unsigned int utilization = + performance / (2 * compute_num * SNRT_NFPU_PER_CORE * 2); +#else + long unsigned int utilization = + performance / (2 * compute_num * SNRT_NFPU_PER_CORE); +#endif + + printf("\n----- (%dx%d) fmatmul (fp%d) -----\n", gemm_l.M, gemm_l.N, + PREC); + printf("Compute cores: %d\n", compute_num); + printf("The execution took %u cycles.\n", timer); + printf("The performance is %ld OP/1000cycle (%ld%%o utilization).\n", + performance, utilization); + + // Write results back to DRAM; verify.py reads gemm_C_dram post-simulation + snrt_dma_start_1d(gemm_C_dram, c, gemm_l.M * gemm_l.N * sizeof(T)); + snrt_dma_wait_all(); + } + + snrt_cluster_hw_barrier(); + + return 0; +} +#endif diff --git a/sw/kernels/common.mk b/sw/kernels/common.mk index 4f1e25e200..5f06ee75b9 100644 --- a/sw/kernels/common.mk +++ b/sw/kernels/common.mk @@ -71,7 +71,8 @@ $(ELF): SRCS := $(SRCS) $(DEP) $(ELF): SN_RISCV_CFLAGS := $($(APP)_RISCV_CFLAGS) $(ELF): SN_RISCV_LDFLAGS := $($(APP)_RISCV_LDFLAGS) -$(DEP): $(SRCS) | $($(APP)_BUILD_DIR) $($(APP)_HEADERS) +# explicit dependency on toolchain.mk ensures that the kernels are rebuilt if the toolchain is updated +$(DEP): $(SRCS) $(SN_TOOLCHAIN_MK) | $($(APP)_BUILD_DIR) $($(APP)_HEADERS) $(SN_RISCV_CXX) $(SN_RISCV_CFLAGS) -MM -MT '$(ELF)' -x c++ $< > $@ $(ELF): $(SRCS) $(DEP) $(SN_RUNTIME_LD_DEPS) | $($(APP)_BUILD_DIR) diff --git a/sw/riscv-tests/riscv-tests.mk b/sw/riscv-tests/riscv-tests.mk index 5efcc8cfd2..fe6e903f82 100644 --- a/sw/riscv-tests/riscv-tests.mk +++ b/sw/riscv-tests/riscv-tests.mk @@ -84,12 +84,12 @@ $(1): $$($(1)_tests_dump) $$($(1)_tests_dump): %.dump: %.elf $$(SN_RISCV_OBJDUMP) $$(SN_RVT_RISCV_OBJDUMP_FLAGS) $$(SN_RVTESTS_BUILDDIR)$$< > $$(SN_RVTESTS_BUILDDIR)$$@ -COMPILER_SUPPORTS_$(1) := $$(shell $(SN_RISCV_CC) $(2) -c -x c /dev/null -o /dev/null 2> /dev/null; echo $$$$?) +ifdef SN_RISCV_CC +COMPILER_SUPPORTS_$(1) := $$(shell $$(SN_RISCV_CC) $(2) -c -x c /dev/null -o /dev/null 2> /dev/null; echo $$$$?) ifeq ($$(COMPILER_SUPPORTS_$(1)),0) tests += $$($(1)_tests) endif - -tests += $$($(1)_tests) +endif endef diff --git a/sw/runtime/impl/snitch_cluster_cfg.h.tpl b/sw/runtime/impl/snitch_cluster_cfg.h.tpl index 77eb6a7a87..3109fb2e65 100644 --- a/sw/runtime/impl/snitch_cluster_cfg.h.tpl +++ b/sw/runtime/impl/snitch_cluster_cfg.h.tpl @@ -15,7 +15,8 @@ supports_copift = False supports_pulp = False supports_smallfloat = False - smallfloat_subextensions = ['xf8', 'xf8alt', 'xf16', 'xf16alt', 'xfdotp', 'xfvec'] + supports_vector = False + smallfloat_subextensions = ['xf8', 'xf8alt', 'zfh', 'xf16alt', 'xfdotp', 'xfvec'] pulp_subextensions = [ 'xcvmem', 'xpulpabs', @@ -36,6 +37,7 @@ supports_copift = supports_copift or core['xcopift'] supports_pulp = supports_pulp or any([core[ext] for ext in pulp_subextensions]) supports_smallfloat = supports_smallfloat or any([core[ext] for ext in smallfloat_subextensions]) + supports_vector = supports_vector or core['isa_parsed'].v %> @@ -91,5 +93,9 @@ #define SNRT_SUPPORTS_SMALLFLOAT % endif +% if supports_vector: +#define SNRT_SUPPORTS_VECTOR +% endif + // Software configuration #define SNRT_LOG2_STACK_SIZE 10 diff --git a/sw/runtime/src/sync.h b/sw/runtime/src/sync.h index e2113faed9..662ff9fa56 100644 --- a/sw/runtime/src/sync.h +++ b/sw/runtime/src/sync.h @@ -346,8 +346,11 @@ inline uint32_t snrt_global_all_to_all_reduction(uint32_t value) { snrt_wait_writeback(tmp); snrt_cluster_hw_barrier(); - // Reduce DM cores across clusters in global memory - if (snrt_is_dm_core()) { + // Reduce DM cores across clusters in global memory. + // If we only have a single cluster, this step is unnecessary and we must + // not enter the inter-cluster barrier (it may deadlock if the barrier state + // is not pristine). + if ((snrt_cluster_num() > 1) && snrt_is_dm_core()) { __atomic_add_fetch(&_reduction_result, *cluster_result, __ATOMIC_RELAXED); snrt_inter_cluster_barrier(); diff --git a/sw/tests/src/vector.c b/sw/tests/src/vector.c new file mode 100644 index 0000000000..aaf3ed8b0d --- /dev/null +++ b/sw/tests/src/vector.c @@ -0,0 +1,61 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#include +#include + +#define N 8 + +// Input data in off-chip memory (DRAM) +double a[N] + __attribute__((aligned(4096))) = {3.0, 3.0, 3.0, 3.0, 3.0, 3.0, 3.0, 3.0}; +double b[N] + __attribute__((aligned(4096))) = {2.0, 2.0, 2.0, 2.0, 2.0, 2.0, 2.0, 2.0}; + +#ifndef SNRT_SUPPORTS_VECTOR +int main() { return 0; } +#else +int main() { + // Allocate space for a, b, c in L1 (TCDM) + double *local_a = (double *)snrt_l1_next(); + double *local_b = local_a + N; + double *local_c = local_b + N; + + // DMA core moves data from DRAM to L1 + if (snrt_is_dm_core()) { + snrt_dma_start_1d(local_a, a, N * sizeof(double)); + snrt_dma_start_1d(local_b, b, N * sizeof(double)); + snrt_dma_wait_all(); + } + + snrt_cluster_hw_barrier(); + + if (snrt_is_compute_core()) { + int errs = 0; + unsigned int vl; + + asm volatile("vsetvli %0, %1, e64, m8, ta, ma" + : "=r"(vl) + : "r"((unsigned int)N)); + + // Load a and b from L1, multiply, store result to L1 + asm volatile("vle64.v v0, (%0)" ::"r"(local_a)); + asm volatile("vle64.v v8, (%0)" ::"r"(local_b)); + asm volatile("vfmul.vv v8, v0, v8"); + asm volatile("vse64.v v8, (%0)" ::"r"(local_c)); + + // Check results via volatile pointer to prevent auto-vectorization + double *vc = (double *)local_c; + for (int i = 0; i < N; i++) { + if ((vc[i] - 6.0) > 0.01f) errs++; + } + + return errs; + } + + snrt_cluster_hw_barrier(); + + return 0; +} +#endif diff --git a/sw/tests/tests.mk b/sw/tests/tests.mk index ff05b3ac0c..3bf247ac64 100644 --- a/sw/tests/tests.mk +++ b/sw/tests/tests.mk @@ -66,7 +66,8 @@ $(SN_TESTS_BUILDDIR): # $(1) = full source path define sn_test_rules -$$(SN_TESTS_BUILDDIR)/$$(notdir $$(basename $(1))).d: $(1) | $$(SN_TESTS_BUILDDIR) +# explicit dependency on toolchain.mk ensures that the tests are rebuilt if the toolchain is updated +$$(SN_TESTS_BUILDDIR)/$$(notdir $$(basename $(1))).d: $(1) $(SN_TOOLCHAIN_MK) | $$(SN_TESTS_BUILDDIR) $$(SN_RISCV_CXX) $$(SN_TESTS_RISCV_CFLAGS) -MM -MT '$$(SN_TESTS_BUILDDIR)/$$(notdir $$(basename $(1))).elf' -x c++ $$< > $$@ $$(SN_TESTS_BUILDDIR)/$$(notdir $$(basename $(1))).elf: $(1) $$(SN_RUNTIME_LD_DEPS) $$(SN_TESTS_BUILDDIR)/$$(notdir $$(basename $(1))).d | $$(SN_TESTS_BUILDDIR) diff --git a/sw/toolchain.mk b/sw/toolchain.mk deleted file mode 100644 index 5241a80fcd..0000000000 --- a/sw/toolchain.mk +++ /dev/null @@ -1,73 +0,0 @@ -# Copyright 2023 ETH Zurich and University of Bologna. -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 -# -# Luca Colagrande -# Viviane Potocnik - -######## -# Util # -######## - -empty := -space := $(empty) $(empty) -comma := , - -comma-join = $(subst $(space),$(comma),$(strip $(1))) - -################### -# Build variables # -################### - -# Compiler toolchain -SN_LLVM_BINROOT ?= $(dir $(shell which riscv32-unknown-elf-clang)) -SN_RISCV_CC ?= $(SN_LLVM_BINROOT)/clang -SN_RISCV_CXX ?= $(SN_LLVM_BINROOT)/clang++ -SN_RISCV_LD ?= $(SN_LLVM_BINROOT)/ld.lld -SN_RISCV_AR ?= $(SN_LLVM_BINROOT)/llvm-ar -SN_RISCV_OBJCOPY ?= $(SN_LLVM_BINROOT)/llvm-objcopy -SN_RISCV_OBJDUMP ?= $(SN_LLVM_BINROOT)/llvm-objdump -SN_RISCV_MC ?= $(SN_LLVM_BINROOT)/llvm-mc -SN_RISCV_ADDR2LINE ?= $(SN_LLVM_BINROOT)/llvm-addr2line - -# Compiler flags -SN_MCPU ?= snitch -ifeq ($(SN_MCPU),snitch-mempool) -SN_RISCV_FEATURES = xdma xcvmem xpulpabs xpulpbitop xpulpbr xpulpclip xpulpmacsi xpulpminmax xpulpslet xpulpvect xpulpvectshufflepack -else -SN_RISCV_FEATURES = xfrep xssr xdma xcopift xsmallfloatb xsmallfloath xsmallfloatvb xsmallfloatvh xsmallfloatvs -endif -SN_RISCV_CFLAGS := -march=rv32imafd_zfh_zifencei -SN_RISCV_CFLAGS += $(foreach feat,$(SN_RISCV_FEATURES),-Xclang -target-feature -Xclang +$(feat)) -SN_RISCV_CFLAGS += -menable-experimental-extensions -SN_RISCV_CFLAGS += -mabi=ilp32d -SN_RISCV_CFLAGS += -mcmodel=medany -# SN_RISCV_CFLAGS += -mno-fdiv -SN_RISCV_CFLAGS += -fno-builtin-printf -SN_RISCV_CFLAGS += -fno-builtin-sqrtf -SN_RISCV_CFLAGS += -fno-common -SN_RISCV_CFLAGS += -fopenmp -SN_RISCV_CFLAGS += -ftls-model=local-exec -SN_RISCV_CFLAGS += -O3 -SN_RISCV_CFLAGS += -Werror -ifeq ($(DEBUG), ON) -SN_RISCV_CFLAGS += -g -endif -ifeq ($(OPENOCD_SEMIHOSTING), ON) -SN_RISCV_CFLAGS += -DOPENOCD_SEMIHOSTING -endif - -# Linker flags -SN_RISCV_LDFLAGS := -fuse-ld=$(SN_RISCV_LD) -SN_RISCV_LDFLAGS += -nostartfiles -SN_RISCV_LDFLAGS += -nostdlib++ -SN_RISCV_LDFLAGS += -lm - -# Archiver flags -SN_RISCV_ARFLAGS := rcs - -# Objdump flags -SN_RISCV_MATTR_FEATURES = $(call comma-join,$(addprefix +,$(SN_RISCV_FEATURES))) -SN_RISCV_MATTR_FLAG = --mattr=+m,+a,+f,+d,+zfh,+zifencei,$(SN_RISCV_MATTR_FEATURES) -SN_RISCV_OBJDUMP_FLAGS := --triple=riscv32 $(SN_RISCV_MATTR_FLAG) -SN_RISCV_OBJDUMP_FLAGS += -D diff --git a/sw/toolchain.mk.tpl b/sw/toolchain.mk.tpl new file mode 100644 index 0000000000..087ac238fd --- /dev/null +++ b/sw/toolchain.mk.tpl @@ -0,0 +1,103 @@ +# Copyright 2026 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +<% + disclaimer = ( + '# AUTOMATICALLY GENERATED by clustergen.py; edit sw/toolchain.mk.tpl or\n' + '# the configuration instead.' + ) + + cores = [core for hive in cfg['cluster']['hives'] for core in hive['cores']] + e = any(c['isa_parsed'].e for c in cores) + zfh = any(c['zfh'] for c in cores) + xfvec = any(c['xfvec'] for c in cores) + march_letters = [l for l in ['m', 'a', 'f', 'd', 'v'] if any(getattr(c['isa_parsed'], l) for c in cores)] + + march = 'rv32' + march += 'e' if e else 'i' + march += ''.join(march_letters) + march += '_zfh' if zfh else '' + march += '_zifencei' + + all_features = ['xssr', 'xfrep', 'xdma', 'xcopift', 'xcvmem', + 'xpulpabs', 'xpulpbitop', 'xpulpbr', 'xpulpclip', 'xpulpmacsi', + 'xpulpminmax', 'xpulpslet', 'xpulpvect', 'xpulpvectshufflepack'] + features = [f for f in all_features if any(c[f] for c in cores)] + + # Features that depend on a combination of configuration parameters + smallfloat_b = any(c['xf8'] or c['xf8alt'] for c in cores) + smallfloat_h = any(c['zfh'] or c['xf16alt'] for c in cores) + + if smallfloat_b: + features.append('xsmallfloatb') + if smallfloat_h: + features.append('xsmallfloath') + if smallfloat_b and xfvec: + features.append('xsmallfloatvb') + if smallfloat_h and xfvec: + features.append('xsmallfloatvh') + if xfvec and 'f' in march_letters and 'd' in march_letters: + features.append('xsmallfloatvs') + + attributes = march_letters + if zfh: + attributes.append('zfh') + attributes.append('zifencei') + + mattr = ','.join(f'+{e}' for e in attributes + features) +%> +${disclaimer} + +# Sentinel to test that toolchain.mk has been included and read +SN_TOOLCHAIN_MK_READ = 1 + +# Compiler toolchain +SN_LLVM_BINROOT ?= $(dir $(shell which riscv32-unknown-elf-clang)) +SN_RISCV_CC ?= $(SN_LLVM_BINROOT)/clang +SN_RISCV_CXX ?= $(SN_LLVM_BINROOT)/clang++ +SN_RISCV_LD ?= $(SN_LLVM_BINROOT)/ld.lld +SN_RISCV_AR ?= $(SN_LLVM_BINROOT)/llvm-ar +SN_RISCV_OBJCOPY ?= $(SN_LLVM_BINROOT)/llvm-objcopy +SN_RISCV_OBJDUMP ?= $(SN_LLVM_BINROOT)/llvm-objdump +SN_RISCV_MC ?= $(SN_LLVM_BINROOT)/llvm-mc +SN_RISCV_ADDR2LINE ?= $(SN_LLVM_BINROOT)/llvm-addr2line + +# Compiler flags +SN_RISCV_FEATURES = ${' '.join(features)} +SN_RISCV_CFLAGS := -march=${march} +SN_RISCV_CFLAGS += $(foreach feat,$(SN_RISCV_FEATURES),-Xclang -target-feature -Xclang +$(feat)) +SN_RISCV_CFLAGS += -menable-experimental-extensions +SN_RISCV_CFLAGS += -mabi=ilp32d +SN_RISCV_CFLAGS += -mcmodel=medany +# SN_RISCV_CFLAGS += -mno-fdiv +SN_RISCV_CFLAGS += -fno-builtin-printf +SN_RISCV_CFLAGS += -fno-builtin-sqrtf +SN_RISCV_CFLAGS += -fno-common +SN_RISCV_CFLAGS += -fopenmp +SN_RISCV_CFLAGS += -ftls-model=local-exec +SN_RISCV_CFLAGS += -O3 +SN_RISCV_CFLAGS += -Werror +# Disable auto-vectorization so the compiler does not emit RVV instructions +# behind the programmer's back. Can be overridden by setting SN_RISCV_V_FLAGS=. +SN_RISCV_V_FLAGS ?= -fno-vectorize -fno-slp-vectorize -mllvm -scalable-vectorization=off +SN_RISCV_CFLAGS += $(SN_RISCV_V_FLAGS) +ifeq ($(DEBUG), ON) +SN_RISCV_CFLAGS += -g +endif +ifeq ($(OPENOCD_SEMIHOSTING), ON) +SN_RISCV_CFLAGS += -DOPENOCD_SEMIHOSTING +endif + +# Linker flags +SN_RISCV_LDFLAGS := -fuse-ld=$(SN_RISCV_LD) +SN_RISCV_LDFLAGS += -nostartfiles +SN_RISCV_LDFLAGS += -nostdlib++ +SN_RISCV_LDFLAGS += -lm + +# Archiver flags +SN_RISCV_ARFLAGS := rcs + +# Objdump flags +SN_RISCV_MATTR_FLAG = --mattr=${mattr} +SN_RISCV_OBJDUMP_FLAGS := --triple=riscv32 $(SN_RISCV_MATTR_FLAG) +SN_RISCV_OBJDUMP_FLAGS += -D diff --git a/target/asic/yosys/yosys.mk b/target/asic/yosys/yosys.mk index d3c374d886..13ba9003ac 100644 --- a/target/asic/yosys/yosys.mk +++ b/target/asic/yosys/yosys.mk @@ -6,6 +6,10 @@ # - Philippe Sauter # - Luca Colagrande +# Yosys build is dependent on rtl.mk and must thus be deferred +# after the rtl.mk file is included and read. +ifdef SN_RTL_MK_READ + ############# # Variables # ############# @@ -78,3 +82,5 @@ clean-yosys: clean: clean-yosys SN_DEPS += $(SN_YOSYS_RTL_PREREQ_FILE) + +endif \ No newline at end of file diff --git a/target/sim/tb/sim.hh b/target/sim/tb/sim.hh index 6194b2decb..318133779d 100644 --- a/target/sim/tb/sim.hh +++ b/target/sim/tb/sim.hh @@ -48,7 +48,7 @@ struct Sim : htif_t { private: context_t *host; context_t target; - bool vlt_vcd = false; + bool vlt_fst = false; bool disable_preloading = false; IpcIface ipc; }; diff --git a/target/sim/tb/verilator_lib.cc b/target/sim/tb/verilator_lib.cc index 41ca269d2a..7accc741a9 100644 --- a/target/sim/tb/verilator_lib.cc +++ b/target/sim/tb/verilator_lib.cc @@ -4,12 +4,16 @@ #include +#include + #include "Vtestharness.h" #include "Vtestharness__Dpi.h" #include "sim.hh" #include "tb_lib.hh" #include "verilated.h" -#include "verilated_vcd_c.h" +#if VM_TRACE_FST +#include "verilated_fst_c.h" +#endif std::unique_ptr s; @@ -27,14 +31,34 @@ void sim_thread_main(void *arg) { ((Sim *)arg)->main(); } // Sim time. vluint64_t TIME = 0; +#if VM_TRACE_FST +// The "target" fiber (running `Sim::main()`'s eval/dump loop) can be +// abandoned mid-loop: if no `--ipc` host is attached, `Sim::run()` returns as +// soon as `htif_t::run()` does, without resuming the target fiber again, so +// it never reaches its own post-loop cleanup below (only reachable once the +// loop itself sees `Verilated::gotFinish()`). That drops any FST data not +// yet flushed on a failing test, exactly the run we most want a usable +// waveform for. Register a process-exit hook so the trace gets closed +// regardless of which path terminates the process. +VerilatedFstC *g_fst = nullptr; +void close_fst_at_exit() { + if (g_fst != nullptr) { + g_fst->close(); + g_fst = nullptr; + } +} +#endif + Sim::Sim(int argc, char **argv) : htif_t(argc, argv), ipc(argc, argv) { - // Search arguments for `--vcd` flag and enable waves if requested +#if VM_TRACE_FST + // Search arguments for `--fst` flag and enable waves if requested for (auto i = 1; i < argc; ++i) { - if (strcmp(argv[i], "--vcd") == 0) { - printf("VCD wave generation enabled\n"); - vlt_vcd = true; + if (strcmp(argv[i], "--fst") == 0) { + printf("FST wave generation enabled\n"); + vlt_fst = true; } } +#endif Verilated::commandArgs(argc, argv); } @@ -63,22 +87,29 @@ int Sim::run() { void Sim::main() { // Initialize verilator environment. Verilated::traceEverOn(true); - // Allocate the simulation state and VCD trace. + // Allocate the simulation state. auto top = std::make_unique(); - auto vcd = std::make_unique(); +#if VM_TRACE_FST + // Allocate the FST trace. + auto fst = std::make_unique(); // Trace 8 levels of hierarchy. - if (vlt_vcd) { - top->trace(vcd.get(), 8); - vcd->open("sim.vcd"); - vcd->dump(TIME); + if (vlt_fst) { + top->trace(fst.get(), 8); + fst->open("sim.fst"); + fst->dump(TIME); + g_fst = fst.get(); + std::atexit(close_fst_at_exit); } +#endif TIME += 2; while (!Verilated::gotFinish()) { // Evaluate the DUT. top->eval(); - if (vlt_vcd) vcd->dump(TIME); +#if VM_TRACE_FST + if (vlt_fst) fst->dump(TIME); +#endif // Increase global time. TIME++; // Switch to the HTIF interface in regular intervals. @@ -87,8 +118,11 @@ void Sim::main() { } } - // Clean up. - if (vlt_vcd) vcd->close(); +#if VM_TRACE_FST + // Clean up. (`close_fst_at_exit` guards against a second close() if this + // path is reached normally, by clearing `g_fst` once closed here.) + if (vlt_fst) close_fst_at_exit(); +#endif } } // namespace sim diff --git a/test/spatz.yaml b/test/spatz.yaml new file mode 100644 index 0000000000..7311c58805 --- /dev/null +++ b/test/spatz.yaml @@ -0,0 +1,10 @@ +# Copyright 2026 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +runs: + - elf: ../sw/tests/build/vector.elf + - elf: ../sw/kernels/blas/spatz-axpy/build/spatz-axpy.elf + cmd: [../sw/kernels/blas/spatz-axpy/scripts/verify.py, "${sim_bin}", "${elf}"] + - elf: ../sw/kernels/blas/spatz-fmatmul/build/spatz-fmatmul.elf + cmd: [../sw/kernels/blas/spatz-fmatmul/scripts/verify.py, "${sim_bin}", "${elf}"] diff --git a/util/clustergen/cluster.py b/util/clustergen/cluster.py index d4b342fda9..6c625edf2a 100644 --- a/util/clustergen/cluster.py +++ b/util/clustergen/cluster.py @@ -89,8 +89,9 @@ class RiscvISA: a: bool = False f: bool = False d: bool = False + v: bool = False - isa_string = re.compile(r"^rv32(i|e)([m|a|f|d]*)$") + isa_string = re.compile(r"^rv32(i|e)([m|a|f|d|v]*)$") def parse_isa_string(s): diff --git a/util/clustergen/generate-opcodes.sh b/util/clustergen/generate-opcodes.sh index 2e2808277c..55d5d672f9 100755 --- a/util/clustergen/generate-opcodes.sh +++ b/util/clustergen/generate-opcodes.sh @@ -9,7 +9,7 @@ ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/../.." && pwd) OPCODES=($(cat "$(dirname "${BASH_SOURCE[0]}")/opcodes.txt")) -INSTR_SV=$ROOT/hw/snitch/src/riscv_instr.sv +INSTR_SV=$ROOT/hw/snitch/src/snitch_riscv_instr.sv cat > $INSTR_SV <<- EOM // Copyright 2023 ETH Zurich and University of Bologna. @@ -18,9 +18,12 @@ cat > $INSTR_SV <<- EOM EOM echo -e "// verilog_lint: waive-start parameter-name-style" >> $INSTR_SV +echo -e "// verilog_lint: waive-start explicit-parameter-storage-type" >> $INSTR_SV riscv_opcodes -sverilog --warn-overlap ${OPCODES[@]} -# Dump riscv_opcodes output to the instruction file -cat inst.sverilog >> $INSTR_SV +# Dump riscv_opcodes output to the instruction file, renaming the generated +# package from riscv_instr to snitch_riscv_instr +sed -e 's/\briscv_instr\b/snitch_riscv_instr/g' inst.sverilog >> $INSTR_SV # Delete riscv_opcodes artifacts rm inst.sverilog instr_dict.json echo -e "// verilog_lint: waive-stop parameter-name-style" >> $INSTR_SV +echo -e "// verilog_lint: waive-stop explicit-parameter-storage-type" >> $INSTR_SV diff --git a/util/clustergen/opcodes.txt b/util/clustergen/opcodes.txt index 73d6479248..508f0f2b5a 100644 --- a/util/clustergen/opcodes.txt +++ b/util/clustergen/opcodes.txt @@ -28,6 +28,7 @@ rv64_zbb rv_zba rv_zbc rv_zbkb +rv_v unratified/rv_xdma unratified/rv_xfrep unratified/rv_xssr diff --git a/util/clustergen/snitch_cluster.schema.json b/util/clustergen/snitch_cluster.schema.json index 3bdfc997ec..be5697a72d 100644 --- a/util/clustergen/snitch_cluster.schema.json +++ b/util/clustergen/snitch_cluster.schema.json @@ -168,7 +168,7 @@ }, "atomic_id_width": { "type": "number", - "description": "Width of the cluster's atomic ID.", + "description": "Width of the cluster's atomic ID. Should be set to clog2(num_atomic_masters + 1); atomic ID 0 is reserved for non-atomic masters. All cores in a cluster use the same atomic ID.", "default": 1 }, "collective_width": { @@ -550,10 +550,10 @@ "description": "Enable Smallfloat Xf8alt extension.", "default": false }, - "xf16": { + "zfh": { "type": "boolean", - "title": "Xf16 16-bit Float Extension", - "description": "Enable Smallfloat Xf16 extension (IEEE 16-bit float).", + "title": "Zfh 16-bit Float Extension", + "description": "Enable Zfh extension (IEEE 16-bit float).", "default": false }, "xf16alt": { @@ -696,7 +696,7 @@ "type": "number" } }, - "ssr_mux_resp_depth": { + "ssr_mux_rsp_depth": { "type": "number", "description": "Depth of response buffer in the TCDM multiplexer arbitrating between core and SSR 0.", "default": 4 @@ -794,6 +794,72 @@ } } } + }, + "spatz": { + "type": "object", + "title": "Spatz configuration", + "description": "Configuration of the Spatz VPU.", + "default": {}, + "properties": { + "num_outstanding_loads": { + "type": "number", + "description": "Number of outstanding loads. Determines the buffer size in Spatz' LSU.", + "default": 1 + }, + "n_ipu": { + "type": "number", + "description": "Number of integer processing units.", + "minimum": 1, + "default": 1 + }, + "n_fpu": { + "type": "number", + "description": "Number of floating-point processing units.", + "minimum": 1, + "default": 8 + }, + "vlen": { + "type": "number", + "description": "Vector length.", + "default": 512 + }, + "spatz_nports": { + "type": "number", + "description": "Number of ports for the Spatz VPU.", + "minimum": 1, + "default": 8 + }, + "double_bw": { + "type": "boolean", + "description": "Whether to use double bandwidth.", + "default": false + }, + "spatz_fpu": { + "type": "boolean", + "description": "Whether to include the Spatz FPU.", + "default": true + }, + "mempool": { + "type": "boolean", + "description": "Whether to use the mempool configuration.", + "default": false + }, + "buf_fpu": { + "type": "number", + "description": "Number of buffers for the FPU.", + "default": 1 + }, + "rvf": { + "type": "boolean", + "description": "Whether to include the RVF extension.", + "default": true + }, + "rvd": { + "type": "boolean", + "description": "Whether to include the RVD extension.", + "default": true + } + } } } } diff --git a/util/container/Dockerfile b/util/container/Dockerfile index c6e89bb9de..89f6b7742c 100644 --- a/util/container/Dockerfile +++ b/util/container/Dockerfile @@ -145,8 +145,9 @@ ARG REPO_DIR COPY . ${REPO_DIR} WORKDIR ${REPO_DIR} -# Build the verilator model -RUN uv run make verilator +# Build the verilator model (with simple FST tracing enabled, to meet CI memory constraints) +RUN bender checkout +RUN uv run make verilator DEBUG=ON CI=ON #------------------------------------------------------------------------------- # Stage 4: Software development stage diff --git a/util/container/entrypoint.sh b/util/container/entrypoint.sh index eae58bbb88..a310d060c9 100644 --- a/util/container/entrypoint.sh +++ b/util/container/entrypoint.sh @@ -6,6 +6,7 @@ set -e # We sync dependencies at Docker startup, so we don't have to bake them in in the build stage +bender checkout uv sync --extra all --locked exec "$@" diff --git a/util/sim/data_utils.py b/util/sim/data_utils.py index b0a876e056..b57dbd4326 100644 --- a/util/sim/data_utils.py +++ b/util/sim/data_utils.py @@ -284,6 +284,7 @@ def from_buffer(byte_array, ctype='uint32_t'): """ # Types which have a direct correspondence in Numpy NP_DTYPE_FROM_CTYPE = { + 'uint16_t': np.uint16, 'uint32_t': np.uint32, 'int32_t': np.int32, 'double': np.float64, @@ -303,6 +304,8 @@ def from_buffer(byte_array, ctype='uint32_t'): return np.frombuffer(byte_array, dtype=dtype) elif ctype == '__fp8': return ff.frombuffer(byte_array, 'e5m2') + else: + raise ValueError(f"Unsupported ctype for from_buffer(): {ctype}") class DataGen: diff --git a/uv.lock b/uv.lock index 0c1bf0c455..ed876c8b5c 100644 --- a/uv.lock +++ b/uv.lock @@ -1,11 +1,22 @@ version = 1 revision = 3 -requires-python = ">=3.11" +requires-python = ">=3.12" resolution-markers = [ - "python_full_version >= '3.12' and sys_platform != 'darwin'", - "python_full_version >= '3.12' and sys_platform == 'darwin'", - "python_full_version < '3.12' and sys_platform != 'darwin'", - "python_full_version < '3.12' and sys_platform == 'darwin'", + "python_full_version >= '3.14' and sys_platform == 'win32'", + "python_full_version >= '3.14' and sys_platform != 'darwin' and sys_platform != 'win32'", + "python_full_version < '3.14' and sys_platform == 'win32'", + "python_full_version < '3.14' and sys_platform != 'darwin' and sys_platform != 'win32'", + "python_full_version >= '3.14' and sys_platform == 'darwin'", + "python_full_version < '3.14' and sys_platform == 'darwin'", +] + +[[package]] +name = "annotated-types" +version = "0.8.0" +source = { registry = "https://pypi.org/simple" } +sdist = { url = "https://files.pythonhosted.org/packages/5f/56/a8120250d128bed162cd73c76d45f6ef9991f3e068f62a8ee060afa3104a/annotated_types-0.8.0.tar.gz", hash = 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