From 8d983aaa6c8fd44c2fa22d4c8f892ced1b729cae Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 13 Aug 2026 07:49:23 -0700 Subject: [PATCH 1/3] eyeriss: regenerate FakeRAM macros with current bsg_fakeram (fixes #234) eyeriss was the only design whose FakeRAM cfgs lived under designs//eyeriss/sram/ instead of the standard designs/src//dev/generated/. tools/regenerate_sram.sh only looks at the standard path, so the mass regeneration in 94296798 -- the bump to bsg_fakeram c83ecb4 that fixed the wd_in LEF pin-direction bug -- silently skipped eyeriss. Its committed LEFs still declared the upper half of every rw*/w*_wd_in bus as DIRECTION OUTPUT while Liberty said input, so gate-level sim saw those bits floating and OpenROAD PnR shorted them into one net. Move the three cfgs to the standard path so future sweeps pick eyeriss up, and regenerate LEF/LIB for all three platforms. Beyond the direction fix the macros were stale on a second axis -- they predate the asap7 area calibration and the sky130hd analytical path: nangate45 geometry byte-identical (CACTI path unchanged) asap7 +80% .. +389% area (2.5x periphery overhead + column mux) sky130hd -16% .. -55% area (analytical bitcell replaces scaled CACTI) asap7 and sky130hd floorplans are re-validated in follow-up commits. --- .../eyeriss/sram/lef/fakeram_12x128_1rw.lef | 180 ++++---- .../eyeriss/sram/lef/fakeram_12x2048_1r1w.lef | 310 ++++++------- .../eyeriss/sram/lef/fakeram_13x256_1rw.lef | 130 +++--- .../eyeriss/sram/lef/fakeram_21x32_1r1w.lef | 210 ++++----- .../eyeriss/sram/lef/fakeram_21x512_1r1w.lef | 264 +++++++----- .../eyeriss/sram/lef/fakeram_7x512_1r1w.lef | 148 ++++--- .../eyeriss/sram/lef/fakeram_8x4096_1r1w.lef | 406 ++++++------------ .../eyeriss/sram/lib/fakeram_12x128_1rw.lib | 4 +- .../eyeriss/sram/lib/fakeram_12x2048_1r1w.lib | 4 +- .../eyeriss/sram/lib/fakeram_13x256_1rw.lib | 4 +- .../eyeriss/sram/lib/fakeram_21x32_1r1w.lib | 4 +- .../eyeriss/sram/lib/fakeram_21x512_1r1w.lib | 4 +- .../eyeriss/sram/lib/fakeram_7x512_1r1w.lib | 4 +- .../eyeriss/sram/lib/fakeram_8x4096_1r1w.lib | 4 +- designs/nangate45/eyeriss/BUILD.bazel | 2 +- .../eyeriss/sram/lef/fakeram_12x128_1rw.lef | 12 +- .../eyeriss/sram/lef/fakeram_12x2048_1r1w.lef | 12 +- .../eyeriss/sram/lef/fakeram_13x256_1rw.lef | 12 +- .../eyeriss/sram/lef/fakeram_21x32_1r1w.lef | 20 +- .../eyeriss/sram/lef/fakeram_21x512_1r1w.lef | 20 +- .../eyeriss/sram/lef/fakeram_7x512_1r1w.lef | 6 +- .../eyeriss/sram/lef/fakeram_8x4096_1r1w.lef | 8 +- .../eyeriss/sram/lib/fakeram_12x128_1rw.lib | 2 +- .../eyeriss/sram/lib/fakeram_12x2048_1r1w.lib | 2 +- .../eyeriss/sram/lib/fakeram_13x256_1rw.lib | 2 +- .../eyeriss/sram/lib/fakeram_21x32_1r1w.lib | 2 +- .../eyeriss/sram/lib/fakeram_21x512_1r1w.lib | 2 +- .../eyeriss/sram/lib/fakeram_7x512_1r1w.lib | 2 +- .../eyeriss/sram/lib/fakeram_8x4096_1r1w.lib | 2 +- designs/sky130hd/eyeriss/BUILD.bazel | 6 +- .../eyeriss/sram/lef/fakeram_12x128_1rw.lef | 140 +++--- .../eyeriss/sram/lef/fakeram_12x2048_1r1w.lef | 252 +++++------ .../eyeriss/sram/lef/fakeram_13x256_1rw.lef | 196 ++++----- .../eyeriss/sram/lef/fakeram_21x32_1r1w.lef | 200 ++++----- .../eyeriss/sram/lef/fakeram_21x512_1r1w.lef | 254 ++++++----- .../eyeriss/sram/lef/fakeram_7x512_1r1w.lef | 168 ++++---- .../eyeriss/sram/lef/fakeram_8x4096_1r1w.lef | 180 ++++---- .../eyeriss/sram/lib/fakeram_12x128_1rw.lib | 138 +++--- .../eyeriss/sram/lib/fakeram_12x2048_1r1w.lib | 196 ++++----- .../eyeriss/sram/lib/fakeram_13x256_1rw.lib | 138 +++--- .../eyeriss/sram/lib/fakeram_21x32_1r1w.lib | 196 ++++----- .../eyeriss/sram/lib/fakeram_21x512_1r1w.lib | 196 ++++----- .../eyeriss/sram/lib/fakeram_7x512_1r1w.lib | 196 ++++----- .../eyeriss/sram/lib/fakeram_8x4096_1r1w.lib | 196 ++++----- .../eyeriss/dev/generated}/fakeram_asap7.cfg | 0 .../dev/generated}/fakeram_nangate45.cfg | 0 .../dev/generated}/fakeram_sky130hd.cfg | 0 47 files changed, 2211 insertions(+), 2223 deletions(-) rename designs/{asap7/eyeriss/sram => src/eyeriss/dev/generated}/fakeram_asap7.cfg (100%) rename designs/{nangate45/eyeriss/sram => src/eyeriss/dev/generated}/fakeram_nangate45.cfg (100%) rename designs/{sky130hd/eyeriss/sram => src/eyeriss/dev/generated}/fakeram_sky130hd.cfg (100%) diff --git a/designs/asap7/eyeriss/sram/lef/fakeram_12x128_1rw.lef b/designs/asap7/eyeriss/sram/lef/fakeram_12x128_1rw.lef index bd142846..6f38fc0a 100644 --- a/designs/asap7/eyeriss/sram/lef/fakeram_12x128_1rw.lef +++ b/designs/asap7/eyeriss/sram/lef/fakeram_12x128_1rw.lef @@ -3,7 +3,7 @@ BUSBITCHARS "[]" ; MACRO fakeram_12x128_1rw FOREIGN fakeram_12x128_1rw 0 0 ; SYMMETRY X Y R90 ; - SIZE 6.221 BY 14.472 ; + SIZE 12.960 BY 21.600 ; CLASS BLOCK ; PIN rw0_wd_in[0] DIRECTION INPUT ; @@ -20,7 +20,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.244 0.072 2.268 ; + RECT 0.000 3.252 0.072 3.276 ; END END rw0_wd_in[1] PIN rw0_wd_in[2] @@ -29,7 +29,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.212 0.072 4.236 ; + RECT 0.000 6.228 0.072 6.252 ; END END rw0_wd_in[2] PIN rw0_wd_in[3] @@ -38,7 +38,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 6.149 0.276 6.221 0.300 ; + RECT 12.888 0.276 12.960 0.300 ; END END rw0_wd_in[3] PIN rw0_wd_in[4] @@ -47,7 +47,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 6.149 2.244 6.221 2.268 ; + RECT 12.888 3.252 12.960 3.276 ; END END rw0_wd_in[4] PIN rw0_wd_in[5] @@ -56,11 +56,11 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 6.149 4.212 6.221 4.236 ; + RECT 12.888 6.228 12.960 6.252 ; END END rw0_wd_in[5] PIN rw0_wd_in[6] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -69,48 +69,48 @@ MACRO fakeram_12x128_1rw END END rw0_wd_in[6] PIN rw0_wd_in[7] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.675 0.000 0.693 0.054 ; + RECT 1.215 0.000 1.233 0.054 ; END END rw0_wd_in[7] PIN rw0_wd_in[8] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.143 0.000 1.161 0.054 ; + RECT 2.223 0.000 2.241 0.054 ; END END rw0_wd_in[8] PIN rw0_wd_in[9] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.611 0.000 1.629 0.054 ; + RECT 3.231 0.000 3.249 0.054 ; END END rw0_wd_in[9] PIN rw0_wd_in[10] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.079 0.000 2.097 0.054 ; + RECT 4.239 0.000 4.257 0.054 ; END END rw0_wd_in[10] PIN rw0_wd_in[11] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.547 0.000 2.565 0.054 ; + RECT 5.247 0.000 5.265 0.054 ; END END rw0_wd_in[11] PIN rw0_rd_out[0] @@ -119,7 +119,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.015 0.000 3.033 0.054 ; + RECT 6.255 0.000 6.273 0.054 ; END END rw0_rd_out[0] PIN rw0_rd_out[1] @@ -128,7 +128,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.483 0.000 3.501 0.054 ; + RECT 7.263 0.000 7.281 0.054 ; END END rw0_rd_out[1] PIN rw0_rd_out[2] @@ -137,7 +137,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.951 0.000 3.969 0.054 ; + RECT 8.271 0.000 8.289 0.054 ; END END rw0_rd_out[2] PIN rw0_rd_out[3] @@ -146,7 +146,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.419 0.000 4.437 0.054 ; + RECT 9.279 0.000 9.297 0.054 ; END END rw0_rd_out[3] PIN rw0_rd_out[4] @@ -155,7 +155,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.887 0.000 4.905 0.054 ; + RECT 10.287 0.000 10.305 0.054 ; END END rw0_rd_out[4] PIN rw0_rd_out[5] @@ -164,7 +164,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.355 0.000 5.373 0.054 ; + RECT 11.295 0.000 11.313 0.054 ; END END rw0_rd_out[5] PIN rw0_rd_out[6] @@ -173,7 +173,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 14.418 0.225 14.472 ; + RECT 0.207 21.546 0.225 21.600 ; END END rw0_rd_out[6] PIN rw0_rd_out[7] @@ -182,7 +182,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.819 14.418 0.837 14.472 ; + RECT 1.575 21.546 1.593 21.600 ; END END rw0_rd_out[7] PIN rw0_rd_out[8] @@ -191,7 +191,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.431 14.418 1.449 14.472 ; + RECT 2.943 21.546 2.961 21.600 ; END END rw0_rd_out[8] PIN rw0_rd_out[9] @@ -200,7 +200,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.043 14.418 2.061 14.472 ; + RECT 4.311 21.546 4.329 21.600 ; END END rw0_rd_out[9] PIN rw0_rd_out[10] @@ -209,7 +209,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.655 14.418 2.673 14.472 ; + RECT 5.679 21.546 5.697 21.600 ; END END rw0_rd_out[10] PIN rw0_rd_out[11] @@ -218,7 +218,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.267 14.418 3.285 14.472 ; + RECT 7.047 21.546 7.065 21.600 ; END END rw0_rd_out[11] PIN rw0_addr_in[0] @@ -227,7 +227,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 6.180 0.072 6.204 ; + RECT 0.000 9.204 0.072 9.228 ; END END rw0_addr_in[0] PIN rw0_addr_in[1] @@ -236,7 +236,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 8.148 0.072 8.172 ; + RECT 0.000 12.180 0.072 12.204 ; END END rw0_addr_in[1] PIN rw0_addr_in[2] @@ -245,7 +245,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 10.116 0.072 10.140 ; + RECT 0.000 15.156 0.072 15.180 ; END END rw0_addr_in[2] PIN rw0_addr_in[3] @@ -254,7 +254,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 12.084 0.072 12.108 ; + RECT 0.000 18.132 0.072 18.156 ; END END rw0_addr_in[3] PIN rw0_addr_in[4] @@ -263,7 +263,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 6.149 6.180 6.221 6.204 ; + RECT 12.888 9.204 12.960 9.228 ; END END rw0_addr_in[4] PIN rw0_addr_in[5] @@ -272,7 +272,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 6.149 8.148 6.221 8.172 ; + RECT 12.888 12.180 12.960 12.204 ; END END rw0_addr_in[5] PIN rw0_addr_in[6] @@ -281,7 +281,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 6.149 10.116 6.221 10.140 ; + RECT 12.888 15.156 12.960 15.180 ; END END rw0_addr_in[6] PIN rw0_we_in @@ -290,7 +290,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.879 14.418 3.897 14.472 ; + RECT 8.415 21.546 8.433 21.600 ; END END rw0_we_in PIN rw0_ce_in @@ -299,7 +299,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.491 14.418 4.509 14.472 ; + RECT 9.783 21.546 9.801 21.600 ; END END rw0_ce_in PIN rw0_clk @@ -308,7 +308,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.103 14.418 5.121 14.472 ; + RECT 11.151 21.546 11.169 21.600 ; END END rw0_clk PIN VSS @@ -316,25 +316,34 @@ MACRO fakeram_12x128_1rw USE GROUND ; PORT LAYER M4 ; - RECT 0.216 0.240 6.005 0.336 ; - RECT 0.216 1.008 6.005 1.104 ; - RECT 0.216 1.776 6.005 1.872 ; - RECT 0.216 2.544 6.005 2.640 ; - RECT 0.216 3.312 6.005 3.408 ; - RECT 0.216 4.080 6.005 4.176 ; - RECT 0.216 4.848 6.005 4.944 ; - RECT 0.216 5.616 6.005 5.712 ; - RECT 0.216 6.384 6.005 6.480 ; - RECT 0.216 7.152 6.005 7.248 ; - RECT 0.216 7.920 6.005 8.016 ; - RECT 0.216 8.688 6.005 8.784 ; - RECT 0.216 9.456 6.005 9.552 ; - RECT 0.216 10.224 6.005 10.320 ; - RECT 0.216 10.992 6.005 11.088 ; - RECT 0.216 11.760 6.005 11.856 ; - RECT 0.216 12.528 6.005 12.624 ; - RECT 0.216 13.296 6.005 13.392 ; - RECT 0.216 14.064 6.005 14.160 ; + RECT 0.216 0.240 12.744 0.336 ; + RECT 0.216 1.008 12.744 1.104 ; + RECT 0.216 1.776 12.744 1.872 ; + RECT 0.216 2.544 12.744 2.640 ; + RECT 0.216 3.312 12.744 3.408 ; + RECT 0.216 4.080 12.744 4.176 ; + RECT 0.216 4.848 12.744 4.944 ; + RECT 0.216 5.616 12.744 5.712 ; + RECT 0.216 6.384 12.744 6.480 ; + RECT 0.216 7.152 12.744 7.248 ; + RECT 0.216 7.920 12.744 8.016 ; + RECT 0.216 8.688 12.744 8.784 ; + RECT 0.216 9.456 12.744 9.552 ; + RECT 0.216 10.224 12.744 10.320 ; + RECT 0.216 10.992 12.744 11.088 ; + RECT 0.216 11.760 12.744 11.856 ; + RECT 0.216 12.528 12.744 12.624 ; + RECT 0.216 13.296 12.744 13.392 ; + RECT 0.216 14.064 12.744 14.160 ; + RECT 0.216 14.832 12.744 14.928 ; + RECT 0.216 15.600 12.744 15.696 ; + RECT 0.216 16.368 12.744 16.464 ; + RECT 0.216 17.136 12.744 17.232 ; + RECT 0.216 17.904 12.744 18.000 ; + RECT 0.216 18.672 12.744 18.768 ; + RECT 0.216 19.440 12.744 19.536 ; + RECT 0.216 20.208 12.744 20.304 ; + RECT 0.216 20.976 12.744 21.072 ; END END VSS PIN VDD @@ -342,36 +351,45 @@ MACRO fakeram_12x128_1rw USE POWER ; PORT LAYER M4 ; - RECT 0.216 0.240 6.005 0.336 ; - RECT 0.216 1.008 6.005 1.104 ; - RECT 0.216 1.776 6.005 1.872 ; - RECT 0.216 2.544 6.005 2.640 ; - RECT 0.216 3.312 6.005 3.408 ; - RECT 0.216 4.080 6.005 4.176 ; - RECT 0.216 4.848 6.005 4.944 ; - RECT 0.216 5.616 6.005 5.712 ; - RECT 0.216 6.384 6.005 6.480 ; - RECT 0.216 7.152 6.005 7.248 ; - RECT 0.216 7.920 6.005 8.016 ; - RECT 0.216 8.688 6.005 8.784 ; - RECT 0.216 9.456 6.005 9.552 ; - RECT 0.216 10.224 6.005 10.320 ; - RECT 0.216 10.992 6.005 11.088 ; - RECT 0.216 11.760 6.005 11.856 ; - RECT 0.216 12.528 6.005 12.624 ; - RECT 0.216 13.296 6.005 13.392 ; - RECT 0.216 14.064 6.005 14.160 ; + RECT 0.216 0.240 12.744 0.336 ; + RECT 0.216 1.008 12.744 1.104 ; + RECT 0.216 1.776 12.744 1.872 ; + RECT 0.216 2.544 12.744 2.640 ; + RECT 0.216 3.312 12.744 3.408 ; + RECT 0.216 4.080 12.744 4.176 ; + RECT 0.216 4.848 12.744 4.944 ; + RECT 0.216 5.616 12.744 5.712 ; + RECT 0.216 6.384 12.744 6.480 ; + RECT 0.216 7.152 12.744 7.248 ; + RECT 0.216 7.920 12.744 8.016 ; + RECT 0.216 8.688 12.744 8.784 ; + RECT 0.216 9.456 12.744 9.552 ; + RECT 0.216 10.224 12.744 10.320 ; + RECT 0.216 10.992 12.744 11.088 ; + RECT 0.216 11.760 12.744 11.856 ; + RECT 0.216 12.528 12.744 12.624 ; + RECT 0.216 13.296 12.744 13.392 ; + RECT 0.216 14.064 12.744 14.160 ; + RECT 0.216 14.832 12.744 14.928 ; + RECT 0.216 15.600 12.744 15.696 ; + RECT 0.216 16.368 12.744 16.464 ; + RECT 0.216 17.136 12.744 17.232 ; + RECT 0.216 17.904 12.744 18.000 ; + RECT 0.216 18.672 12.744 18.768 ; + RECT 0.216 19.440 12.744 19.536 ; + RECT 0.216 20.208 12.744 20.304 ; + RECT 0.216 20.976 12.744 21.072 ; END END VDD OBS LAYER M1 ; - RECT 0 0 6.221 14.472 ; + RECT 0 0 12.960 21.600 ; LAYER M2 ; - RECT 0 0 6.221 14.472 ; + RECT 0 0 12.960 21.600 ; LAYER M3 ; - RECT 0 0 6.221 14.472 ; + RECT 0 0 12.960 21.600 ; LAYER M4 ; - RECT 0 0 6.221 14.472 ; + RECT 0 0 12.960 21.600 ; END END fakeram_12x128_1rw diff --git a/designs/asap7/eyeriss/sram/lef/fakeram_12x2048_1r1w.lef b/designs/asap7/eyeriss/sram/lef/fakeram_12x2048_1r1w.lef index ea4f3a2f..188a801f 100644 --- a/designs/asap7/eyeriss/sram/lef/fakeram_12x2048_1r1w.lef +++ b/designs/asap7/eyeriss/sram/lef/fakeram_12x2048_1r1w.lef @@ -3,7 +3,7 @@ BUSBITCHARS "[]" ; MACRO fakeram_12x2048_1r1w FOREIGN fakeram_12x2048_1r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 9.643 BY 43.859 ; + SIZE 40.176 BY 33.481 ; CLASS BLOCK ; PIN w0_wd_in[0] DIRECTION INPUT ; @@ -20,7 +20,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.164 0.072 4.188 ; + RECT 0.000 3.252 0.072 3.276 ; END END w0_wd_in[1] PIN w0_wd_in[2] @@ -29,7 +29,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 8.052 0.072 8.076 ; + RECT 0.000 6.228 0.072 6.252 ; END END w0_wd_in[2] PIN w0_wd_in[3] @@ -38,7 +38,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 0.276 9.643 0.300 ; + RECT 40.104 0.276 40.176 0.300 ; END END w0_wd_in[3] PIN w0_wd_in[4] @@ -47,7 +47,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 4.164 9.643 4.188 ; + RECT 40.104 3.252 40.176 3.276 ; END END w0_wd_in[4] PIN w0_wd_in[5] @@ -56,11 +56,11 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 8.052 9.643 8.076 ; + RECT 40.104 6.228 40.176 6.252 ; END END w0_wd_in[5] PIN w0_wd_in[6] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -69,48 +69,48 @@ MACRO fakeram_12x2048_1r1w END END w0_wd_in[6] PIN w0_wd_in[7] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.963 0.000 0.981 0.054 ; + RECT 3.483 0.000 3.501 0.054 ; END END w0_wd_in[7] PIN w0_wd_in[8] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.719 0.000 1.737 0.054 ; + RECT 6.759 0.000 6.777 0.054 ; END END w0_wd_in[8] PIN w0_wd_in[9] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.475 0.000 2.493 0.054 ; + RECT 10.035 0.000 10.053 0.054 ; END END w0_wd_in[9] PIN w0_wd_in[10] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.231 0.000 3.249 0.054 ; + RECT 13.311 0.000 13.329 0.054 ; END END w0_wd_in[10] PIN w0_wd_in[11] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.987 0.000 4.005 0.054 ; + RECT 16.587 0.000 16.605 0.054 ; END END w0_wd_in[11] PIN r0_rd_out[0] @@ -119,7 +119,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.743 0.000 4.761 0.054 ; + RECT 19.863 0.000 19.881 0.054 ; END END r0_rd_out[0] PIN r0_rd_out[1] @@ -128,7 +128,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.499 0.000 5.517 0.054 ; + RECT 23.139 0.000 23.157 0.054 ; END END r0_rd_out[1] PIN r0_rd_out[2] @@ -137,7 +137,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.255 0.000 6.273 0.054 ; + RECT 26.415 0.000 26.433 0.054 ; END END r0_rd_out[2] PIN r0_rd_out[3] @@ -146,7 +146,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.011 0.000 7.029 0.054 ; + RECT 29.691 0.000 29.709 0.054 ; END END r0_rd_out[3] PIN r0_rd_out[4] @@ -155,7 +155,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.767 0.000 7.785 0.054 ; + RECT 32.967 0.000 32.985 0.054 ; END END r0_rd_out[4] PIN r0_rd_out[5] @@ -164,7 +164,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.523 0.000 8.541 0.054 ; + RECT 36.243 0.000 36.261 0.054 ; END END r0_rd_out[5] PIN r0_rd_out[6] @@ -173,7 +173,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 43.805 0.225 43.859 ; + RECT 0.207 33.427 0.225 33.481 ; END END r0_rd_out[6] PIN r0_rd_out[7] @@ -182,7 +182,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.035 43.805 1.053 43.859 ; + RECT 3.807 33.427 3.825 33.481 ; END END r0_rd_out[7] PIN r0_rd_out[8] @@ -191,7 +191,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.863 43.805 1.881 43.859 ; + RECT 7.407 33.427 7.425 33.481 ; END END r0_rd_out[8] PIN r0_rd_out[9] @@ -200,7 +200,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.691 43.805 2.709 43.859 ; + RECT 11.007 33.427 11.025 33.481 ; END END r0_rd_out[9] PIN r0_rd_out[10] @@ -209,7 +209,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.519 43.805 3.537 43.859 ; + RECT 14.607 33.427 14.625 33.481 ; END END r0_rd_out[10] PIN r0_rd_out[11] @@ -218,7 +218,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.347 43.805 4.365 43.859 ; + RECT 18.207 33.427 18.225 33.481 ; END END r0_rd_out[11] PIN w0_addr_in[0] @@ -227,7 +227,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 11.940 0.072 11.964 ; + RECT 0.000 9.204 0.072 9.228 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -236,7 +236,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 15.828 0.072 15.852 ; + RECT 0.000 12.180 0.072 12.204 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -245,7 +245,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 19.716 0.072 19.740 ; + RECT 0.000 15.156 0.072 15.180 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -254,7 +254,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 23.604 0.072 23.628 ; + RECT 0.000 18.132 0.072 18.156 ; END END w0_addr_in[3] PIN w0_addr_in[4] @@ -263,7 +263,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 11.940 9.643 11.964 ; + RECT 40.104 9.204 40.176 9.228 ; END END w0_addr_in[4] PIN w0_addr_in[5] @@ -272,7 +272,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 15.828 9.643 15.852 ; + RECT 40.104 12.180 40.176 12.204 ; END END w0_addr_in[5] PIN w0_addr_in[6] @@ -281,7 +281,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 19.716 9.643 19.740 ; + RECT 40.104 15.156 40.176 15.180 ; END END w0_addr_in[6] PIN w0_addr_in[7] @@ -290,7 +290,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 23.604 9.643 23.628 ; + RECT 40.104 18.132 40.176 18.156 ; END END w0_addr_in[7] PIN r0_addr_in[0] @@ -299,7 +299,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 27.492 0.072 27.516 ; + RECT 0.000 21.108 0.072 21.132 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -308,7 +308,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 31.380 0.072 31.404 ; + RECT 0.000 24.084 0.072 24.108 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -317,7 +317,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 35.268 0.072 35.292 ; + RECT 0.000 27.060 0.072 27.084 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -326,7 +326,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 39.156 0.072 39.180 ; + RECT 0.000 30.036 0.072 30.060 ; END END r0_addr_in[3] PIN r0_addr_in[4] @@ -335,7 +335,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 27.492 9.643 27.516 ; + RECT 40.104 21.108 40.176 21.132 ; END END r0_addr_in[4] PIN r0_addr_in[5] @@ -344,7 +344,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 31.380 9.643 31.404 ; + RECT 40.104 24.084 40.176 24.108 ; END END r0_addr_in[5] PIN r0_addr_in[6] @@ -353,7 +353,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 35.268 9.643 35.292 ; + RECT 40.104 27.060 40.176 27.084 ; END END r0_addr_in[6] PIN r0_addr_in[7] @@ -362,7 +362,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 39.156 9.643 39.180 ; + RECT 40.104 30.036 40.176 30.060 ; END END r0_addr_in[7] PIN w0_we_in @@ -371,7 +371,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.175 43.805 5.193 43.859 ; + RECT 21.807 33.427 21.825 33.481 ; END END w0_we_in PIN w0_ce_in @@ -380,7 +380,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.003 43.805 6.021 43.859 ; + RECT 25.407 33.427 25.425 33.481 ; END END w0_ce_in PIN w0_clk @@ -389,7 +389,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.831 43.805 6.849 43.859 ; + RECT 29.007 33.427 29.025 33.481 ; END END w0_clk PIN r0_ce_in @@ -398,7 +398,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.659 43.805 7.677 43.859 ; + RECT 32.607 33.427 32.625 33.481 ; END END r0_ce_in PIN r0_clk @@ -407,7 +407,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.487 43.805 8.505 43.859 ; + RECT 36.207 33.427 36.225 33.481 ; END END r0_clk PIN VSS @@ -415,63 +415,50 @@ MACRO fakeram_12x2048_1r1w USE GROUND ; PORT LAYER M4 ; - RECT 0.216 0.240 9.427 0.336 ; - RECT 0.216 1.008 9.427 1.104 ; - RECT 0.216 1.776 9.427 1.872 ; - RECT 0.216 2.544 9.427 2.640 ; - RECT 0.216 3.312 9.427 3.408 ; - RECT 0.216 4.080 9.427 4.176 ; - RECT 0.216 4.848 9.427 4.944 ; - RECT 0.216 5.616 9.427 5.712 ; - RECT 0.216 6.384 9.427 6.480 ; - RECT 0.216 7.152 9.427 7.248 ; - RECT 0.216 7.920 9.427 8.016 ; - RECT 0.216 8.688 9.427 8.784 ; - RECT 0.216 9.456 9.427 9.552 ; - RECT 0.216 10.224 9.427 10.320 ; - RECT 0.216 10.992 9.427 11.088 ; - RECT 0.216 11.760 9.427 11.856 ; - RECT 0.216 12.528 9.427 12.624 ; - RECT 0.216 13.296 9.427 13.392 ; - RECT 0.216 14.064 9.427 14.160 ; - RECT 0.216 14.832 9.427 14.928 ; - RECT 0.216 15.600 9.427 15.696 ; - RECT 0.216 16.368 9.427 16.464 ; - RECT 0.216 17.136 9.427 17.232 ; - RECT 0.216 17.904 9.427 18.000 ; - RECT 0.216 18.672 9.427 18.768 ; - RECT 0.216 19.440 9.427 19.536 ; - RECT 0.216 20.208 9.427 20.304 ; - RECT 0.216 20.976 9.427 21.072 ; - RECT 0.216 21.744 9.427 21.840 ; - RECT 0.216 22.512 9.427 22.608 ; - RECT 0.216 23.280 9.427 23.376 ; - RECT 0.216 24.048 9.427 24.144 ; - RECT 0.216 24.816 9.427 24.912 ; - RECT 0.216 25.584 9.427 25.680 ; - RECT 0.216 26.352 9.427 26.448 ; - RECT 0.216 27.120 9.427 27.216 ; - RECT 0.216 27.888 9.427 27.984 ; - RECT 0.216 28.656 9.427 28.752 ; - RECT 0.216 29.424 9.427 29.520 ; - RECT 0.216 30.192 9.427 30.288 ; - RECT 0.216 30.960 9.427 31.056 ; - RECT 0.216 31.728 9.427 31.824 ; - RECT 0.216 32.496 9.427 32.592 ; - RECT 0.216 33.264 9.427 33.360 ; - RECT 0.216 34.032 9.427 34.128 ; - RECT 0.216 34.800 9.427 34.896 ; - RECT 0.216 35.568 9.427 35.664 ; - RECT 0.216 36.336 9.427 36.432 ; - RECT 0.216 37.104 9.427 37.200 ; - RECT 0.216 37.872 9.427 37.968 ; - RECT 0.216 38.640 9.427 38.736 ; - RECT 0.216 39.408 9.427 39.504 ; - RECT 0.216 40.176 9.427 40.272 ; - RECT 0.216 40.944 9.427 41.040 ; - RECT 0.216 41.712 9.427 41.808 ; - RECT 0.216 42.480 9.427 42.576 ; - RECT 0.216 43.248 9.427 43.344 ; + RECT 0.216 0.240 39.960 0.336 ; + RECT 0.216 1.008 39.960 1.104 ; + RECT 0.216 1.776 39.960 1.872 ; + RECT 0.216 2.544 39.960 2.640 ; + RECT 0.216 3.312 39.960 3.408 ; + RECT 0.216 4.080 39.960 4.176 ; + RECT 0.216 4.848 39.960 4.944 ; + RECT 0.216 5.616 39.960 5.712 ; + RECT 0.216 6.384 39.960 6.480 ; + RECT 0.216 7.152 39.960 7.248 ; + RECT 0.216 7.920 39.960 8.016 ; + RECT 0.216 8.688 39.960 8.784 ; + RECT 0.216 9.456 39.960 9.552 ; + RECT 0.216 10.224 39.960 10.320 ; + RECT 0.216 10.992 39.960 11.088 ; + RECT 0.216 11.760 39.960 11.856 ; + RECT 0.216 12.528 39.960 12.624 ; + RECT 0.216 13.296 39.960 13.392 ; + RECT 0.216 14.064 39.960 14.160 ; + RECT 0.216 14.832 39.960 14.928 ; + RECT 0.216 15.600 39.960 15.696 ; + RECT 0.216 16.368 39.960 16.464 ; + RECT 0.216 17.136 39.960 17.232 ; + RECT 0.216 17.904 39.960 18.000 ; + RECT 0.216 18.672 39.960 18.768 ; + RECT 0.216 19.440 39.960 19.536 ; + RECT 0.216 20.208 39.960 20.304 ; + RECT 0.216 20.976 39.960 21.072 ; + RECT 0.216 21.744 39.960 21.840 ; + RECT 0.216 22.512 39.960 22.608 ; + RECT 0.216 23.280 39.960 23.376 ; + RECT 0.216 24.048 39.960 24.144 ; + RECT 0.216 24.816 39.960 24.912 ; + RECT 0.216 25.584 39.960 25.680 ; + RECT 0.216 26.352 39.960 26.448 ; + RECT 0.216 27.120 39.960 27.216 ; + RECT 0.216 27.888 39.960 27.984 ; + RECT 0.216 28.656 39.960 28.752 ; + RECT 0.216 29.424 39.960 29.520 ; + RECT 0.216 30.192 39.960 30.288 ; + RECT 0.216 30.960 39.960 31.056 ; + RECT 0.216 31.728 39.960 31.824 ; + RECT 0.216 32.496 39.960 32.592 ; + RECT 0.216 33.264 39.960 33.360 ; END END VSS PIN VDD @@ -479,74 +466,61 @@ MACRO fakeram_12x2048_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.216 0.240 9.427 0.336 ; - RECT 0.216 1.008 9.427 1.104 ; - RECT 0.216 1.776 9.427 1.872 ; - RECT 0.216 2.544 9.427 2.640 ; - RECT 0.216 3.312 9.427 3.408 ; - RECT 0.216 4.080 9.427 4.176 ; - RECT 0.216 4.848 9.427 4.944 ; - RECT 0.216 5.616 9.427 5.712 ; - RECT 0.216 6.384 9.427 6.480 ; - RECT 0.216 7.152 9.427 7.248 ; - RECT 0.216 7.920 9.427 8.016 ; - RECT 0.216 8.688 9.427 8.784 ; - RECT 0.216 9.456 9.427 9.552 ; - RECT 0.216 10.224 9.427 10.320 ; - RECT 0.216 10.992 9.427 11.088 ; - RECT 0.216 11.760 9.427 11.856 ; - RECT 0.216 12.528 9.427 12.624 ; - RECT 0.216 13.296 9.427 13.392 ; - RECT 0.216 14.064 9.427 14.160 ; - RECT 0.216 14.832 9.427 14.928 ; - RECT 0.216 15.600 9.427 15.696 ; - RECT 0.216 16.368 9.427 16.464 ; - RECT 0.216 17.136 9.427 17.232 ; - RECT 0.216 17.904 9.427 18.000 ; - RECT 0.216 18.672 9.427 18.768 ; - RECT 0.216 19.440 9.427 19.536 ; - RECT 0.216 20.208 9.427 20.304 ; - RECT 0.216 20.976 9.427 21.072 ; - RECT 0.216 21.744 9.427 21.840 ; - RECT 0.216 22.512 9.427 22.608 ; - RECT 0.216 23.280 9.427 23.376 ; - RECT 0.216 24.048 9.427 24.144 ; - RECT 0.216 24.816 9.427 24.912 ; - RECT 0.216 25.584 9.427 25.680 ; - RECT 0.216 26.352 9.427 26.448 ; - RECT 0.216 27.120 9.427 27.216 ; - RECT 0.216 27.888 9.427 27.984 ; - RECT 0.216 28.656 9.427 28.752 ; - RECT 0.216 29.424 9.427 29.520 ; - RECT 0.216 30.192 9.427 30.288 ; - RECT 0.216 30.960 9.427 31.056 ; - RECT 0.216 31.728 9.427 31.824 ; - RECT 0.216 32.496 9.427 32.592 ; - RECT 0.216 33.264 9.427 33.360 ; - RECT 0.216 34.032 9.427 34.128 ; - RECT 0.216 34.800 9.427 34.896 ; - RECT 0.216 35.568 9.427 35.664 ; - RECT 0.216 36.336 9.427 36.432 ; - RECT 0.216 37.104 9.427 37.200 ; - RECT 0.216 37.872 9.427 37.968 ; - RECT 0.216 38.640 9.427 38.736 ; - RECT 0.216 39.408 9.427 39.504 ; - RECT 0.216 40.176 9.427 40.272 ; - RECT 0.216 40.944 9.427 41.040 ; - RECT 0.216 41.712 9.427 41.808 ; - RECT 0.216 42.480 9.427 42.576 ; - RECT 0.216 43.248 9.427 43.344 ; + RECT 0.216 0.240 39.960 0.336 ; + RECT 0.216 1.008 39.960 1.104 ; + RECT 0.216 1.776 39.960 1.872 ; + RECT 0.216 2.544 39.960 2.640 ; + RECT 0.216 3.312 39.960 3.408 ; + RECT 0.216 4.080 39.960 4.176 ; + RECT 0.216 4.848 39.960 4.944 ; + RECT 0.216 5.616 39.960 5.712 ; + RECT 0.216 6.384 39.960 6.480 ; + RECT 0.216 7.152 39.960 7.248 ; + RECT 0.216 7.920 39.960 8.016 ; + RECT 0.216 8.688 39.960 8.784 ; + RECT 0.216 9.456 39.960 9.552 ; + RECT 0.216 10.224 39.960 10.320 ; + RECT 0.216 10.992 39.960 11.088 ; + RECT 0.216 11.760 39.960 11.856 ; + RECT 0.216 12.528 39.960 12.624 ; + RECT 0.216 13.296 39.960 13.392 ; + RECT 0.216 14.064 39.960 14.160 ; + RECT 0.216 14.832 39.960 14.928 ; + RECT 0.216 15.600 39.960 15.696 ; + RECT 0.216 16.368 39.960 16.464 ; + RECT 0.216 17.136 39.960 17.232 ; + RECT 0.216 17.904 39.960 18.000 ; + RECT 0.216 18.672 39.960 18.768 ; + RECT 0.216 19.440 39.960 19.536 ; + RECT 0.216 20.208 39.960 20.304 ; + RECT 0.216 20.976 39.960 21.072 ; + RECT 0.216 21.744 39.960 21.840 ; + RECT 0.216 22.512 39.960 22.608 ; + RECT 0.216 23.280 39.960 23.376 ; + RECT 0.216 24.048 39.960 24.144 ; + RECT 0.216 24.816 39.960 24.912 ; + RECT 0.216 25.584 39.960 25.680 ; + RECT 0.216 26.352 39.960 26.448 ; + RECT 0.216 27.120 39.960 27.216 ; + RECT 0.216 27.888 39.960 27.984 ; + RECT 0.216 28.656 39.960 28.752 ; + RECT 0.216 29.424 39.960 29.520 ; + RECT 0.216 30.192 39.960 30.288 ; + RECT 0.216 30.960 39.960 31.056 ; + RECT 0.216 31.728 39.960 31.824 ; + RECT 0.216 32.496 39.960 32.592 ; + RECT 0.216 33.264 39.960 33.360 ; END END VDD OBS LAYER M1 ; - RECT 0 0 9.643 43.859 ; + RECT 0 0 40.176 33.481 ; LAYER M2 ; - RECT 0 0 9.643 43.859 ; + RECT 0 0 40.176 33.481 ; LAYER M3 ; - RECT 0 0 9.643 43.859 ; + RECT 0 0 40.176 33.481 ; LAYER M4 ; - RECT 0 0 9.643 43.859 ; + RECT 0 0 40.176 33.481 ; END END fakeram_12x2048_1r1w diff --git a/designs/asap7/eyeriss/sram/lef/fakeram_13x256_1rw.lef b/designs/asap7/eyeriss/sram/lef/fakeram_13x256_1rw.lef index 39c41826..fb73f420 100644 --- a/designs/asap7/eyeriss/sram/lef/fakeram_13x256_1rw.lef +++ b/designs/asap7/eyeriss/sram/lef/fakeram_13x256_1rw.lef @@ -3,7 +3,7 @@ BUSBITCHARS "[]" ; MACRO fakeram_13x256_1rw FOREIGN fakeram_13x256_1rw 0 0 ; SYMMETRY X Y R90 ; - SIZE 6.221 BY 6.221 ; + SIZE 7.020 BY 10.800 ; CLASS BLOCK ; PIN rw0_wd_in[0] DIRECTION INPUT ; @@ -20,7 +20,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.044 0.072 1.068 ; + RECT 0.000 1.716 0.072 1.740 ; END END rw0_wd_in[1] PIN rw0_wd_in[2] @@ -29,7 +29,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.812 0.072 1.836 ; + RECT 0.000 3.156 0.072 3.180 ; END END rw0_wd_in[2] PIN rw0_wd_in[3] @@ -38,7 +38,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.580 0.072 2.604 ; + RECT 0.000 4.596 0.072 4.620 ; END END rw0_wd_in[3] PIN rw0_wd_in[4] @@ -47,7 +47,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 6.149 0.276 6.221 0.300 ; + RECT 6.948 0.276 7.020 0.300 ; END END rw0_wd_in[4] PIN rw0_wd_in[5] @@ -56,7 +56,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 6.149 1.044 6.221 1.068 ; + RECT 6.948 1.716 7.020 1.740 ; END END rw0_wd_in[5] PIN rw0_wd_in[6] @@ -65,11 +65,11 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 6.149 1.812 6.221 1.836 ; + RECT 6.948 3.156 7.020 3.180 ; END END rw0_wd_in[6] PIN rw0_wd_in[7] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -78,48 +78,48 @@ MACRO fakeram_13x256_1rw END END rw0_wd_in[7] PIN rw0_wd_in[8] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.603 0.000 0.621 0.054 ; + RECT 0.675 0.000 0.693 0.054 ; END END rw0_wd_in[8] PIN rw0_wd_in[9] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.999 0.000 1.017 0.054 ; + RECT 1.143 0.000 1.161 0.054 ; END END rw0_wd_in[9] PIN rw0_wd_in[10] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.395 0.000 1.413 0.054 ; + RECT 1.611 0.000 1.629 0.054 ; END END rw0_wd_in[10] PIN rw0_wd_in[11] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.791 0.000 1.809 0.054 ; + RECT 2.079 0.000 2.097 0.054 ; END END rw0_wd_in[11] PIN rw0_wd_in[12] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.187 0.000 2.205 0.054 ; + RECT 2.547 0.000 2.565 0.054 ; END END rw0_wd_in[12] PIN rw0_rd_out[0] @@ -128,7 +128,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.583 0.000 2.601 0.054 ; + RECT 3.015 0.000 3.033 0.054 ; END END rw0_rd_out[0] PIN rw0_rd_out[1] @@ -137,7 +137,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.979 0.000 2.997 0.054 ; + RECT 3.483 0.000 3.501 0.054 ; END END rw0_rd_out[1] PIN rw0_rd_out[2] @@ -146,7 +146,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.375 0.000 3.393 0.054 ; + RECT 3.951 0.000 3.969 0.054 ; END END rw0_rd_out[2] PIN rw0_rd_out[3] @@ -155,7 +155,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.771 0.000 3.789 0.054 ; + RECT 4.419 0.000 4.437 0.054 ; END END rw0_rd_out[3] PIN rw0_rd_out[4] @@ -164,7 +164,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.167 0.000 4.185 0.054 ; + RECT 4.887 0.000 4.905 0.054 ; END END rw0_rd_out[4] PIN rw0_rd_out[5] @@ -173,7 +173,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.563 0.000 4.581 0.054 ; + RECT 5.355 0.000 5.373 0.054 ; END END rw0_rd_out[5] PIN rw0_rd_out[6] @@ -182,7 +182,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.959 0.000 4.977 0.054 ; + RECT 5.823 0.000 5.841 0.054 ; END END rw0_rd_out[6] PIN rw0_rd_out[7] @@ -191,7 +191,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 6.167 0.225 6.221 ; + RECT 0.207 10.746 0.225 10.800 ; END END rw0_rd_out[7] PIN rw0_rd_out[8] @@ -200,7 +200,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.747 6.167 0.765 6.221 ; + RECT 0.855 10.746 0.873 10.800 ; END END rw0_rd_out[8] PIN rw0_rd_out[9] @@ -209,7 +209,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.287 6.167 1.305 6.221 ; + RECT 1.503 10.746 1.521 10.800 ; END END rw0_rd_out[9] PIN rw0_rd_out[10] @@ -218,7 +218,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.827 6.167 1.845 6.221 ; + RECT 2.151 10.746 2.169 10.800 ; END END rw0_rd_out[10] PIN rw0_rd_out[11] @@ -227,7 +227,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.367 6.167 2.385 6.221 ; + RECT 2.799 10.746 2.817 10.800 ; END END rw0_rd_out[11] PIN rw0_rd_out[12] @@ -236,7 +236,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.907 6.167 2.925 6.221 ; + RECT 3.447 10.746 3.465 10.800 ; END END rw0_rd_out[12] PIN rw0_addr_in[0] @@ -245,7 +245,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.348 0.072 3.372 ; + RECT 0.000 6.036 0.072 6.060 ; END END rw0_addr_in[0] PIN rw0_addr_in[1] @@ -254,7 +254,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.116 0.072 4.140 ; + RECT 0.000 7.476 0.072 7.500 ; END END rw0_addr_in[1] PIN rw0_addr_in[2] @@ -263,7 +263,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.884 0.072 4.908 ; + RECT 0.000 8.916 0.072 8.940 ; END END rw0_addr_in[2] PIN rw0_addr_in[3] @@ -272,7 +272,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 6.149 2.580 6.221 2.604 ; + RECT 6.948 4.596 7.020 4.620 ; END END rw0_addr_in[3] PIN rw0_addr_in[4] @@ -281,7 +281,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 6.149 3.348 6.221 3.372 ; + RECT 6.948 6.036 7.020 6.060 ; END END rw0_addr_in[4] PIN rw0_we_in @@ -290,7 +290,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.447 6.167 3.465 6.221 ; + RECT 4.095 10.746 4.113 10.800 ; END END rw0_we_in PIN rw0_ce_in @@ -299,7 +299,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.987 6.167 4.005 6.221 ; + RECT 4.743 10.746 4.761 10.800 ; END END rw0_ce_in PIN rw0_clk @@ -308,7 +308,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.527 6.167 4.545 6.221 ; + RECT 5.391 10.746 5.409 10.800 ; END END rw0_clk PIN VSS @@ -316,14 +316,20 @@ MACRO fakeram_13x256_1rw USE GROUND ; PORT LAYER M4 ; - RECT 0.216 0.240 6.005 0.336 ; - RECT 0.216 1.008 6.005 1.104 ; - RECT 0.216 1.776 6.005 1.872 ; - RECT 0.216 2.544 6.005 2.640 ; - RECT 0.216 3.312 6.005 3.408 ; - RECT 0.216 4.080 6.005 4.176 ; - RECT 0.216 4.848 6.005 4.944 ; - RECT 0.216 5.616 6.005 5.712 ; + RECT 0.216 0.240 6.804 0.336 ; + RECT 0.216 1.008 6.804 1.104 ; + RECT 0.216 1.776 6.804 1.872 ; + RECT 0.216 2.544 6.804 2.640 ; + RECT 0.216 3.312 6.804 3.408 ; + RECT 0.216 4.080 6.804 4.176 ; + RECT 0.216 4.848 6.804 4.944 ; + RECT 0.216 5.616 6.804 5.712 ; + RECT 0.216 6.384 6.804 6.480 ; + RECT 0.216 7.152 6.804 7.248 ; + RECT 0.216 7.920 6.804 8.016 ; + RECT 0.216 8.688 6.804 8.784 ; + RECT 0.216 9.456 6.804 9.552 ; + RECT 0.216 10.224 6.804 10.320 ; END END VSS PIN VDD @@ -331,25 +337,31 @@ MACRO fakeram_13x256_1rw USE POWER ; PORT LAYER M4 ; - RECT 0.216 0.240 6.005 0.336 ; - RECT 0.216 1.008 6.005 1.104 ; - RECT 0.216 1.776 6.005 1.872 ; - RECT 0.216 2.544 6.005 2.640 ; - RECT 0.216 3.312 6.005 3.408 ; - RECT 0.216 4.080 6.005 4.176 ; - RECT 0.216 4.848 6.005 4.944 ; - RECT 0.216 5.616 6.005 5.712 ; + RECT 0.216 0.240 6.804 0.336 ; + RECT 0.216 1.008 6.804 1.104 ; + RECT 0.216 1.776 6.804 1.872 ; + RECT 0.216 2.544 6.804 2.640 ; + RECT 0.216 3.312 6.804 3.408 ; + RECT 0.216 4.080 6.804 4.176 ; + RECT 0.216 4.848 6.804 4.944 ; + RECT 0.216 5.616 6.804 5.712 ; + RECT 0.216 6.384 6.804 6.480 ; + RECT 0.216 7.152 6.804 7.248 ; + RECT 0.216 7.920 6.804 8.016 ; + RECT 0.216 8.688 6.804 8.784 ; + RECT 0.216 9.456 6.804 9.552 ; + RECT 0.216 10.224 6.804 10.320 ; END END VDD OBS LAYER M1 ; - RECT 0 0 6.221 6.221 ; + RECT 0 0 7.020 10.800 ; LAYER M2 ; - RECT 0 0 6.221 6.221 ; + RECT 0 0 7.020 10.800 ; LAYER M3 ; - RECT 0 0 6.221 6.221 ; + RECT 0 0 7.020 10.800 ; LAYER M4 ; - RECT 0 0 6.221 6.221 ; + RECT 0 0 7.020 10.800 ; END END fakeram_13x256_1rw diff --git a/designs/asap7/eyeriss/sram/lef/fakeram_21x32_1r1w.lef b/designs/asap7/eyeriss/sram/lef/fakeram_21x32_1r1w.lef index 4150c6b3..d01f61aa 100644 --- a/designs/asap7/eyeriss/sram/lef/fakeram_21x32_1r1w.lef +++ b/designs/asap7/eyeriss/sram/lef/fakeram_21x32_1r1w.lef @@ -3,7 +3,7 @@ BUSBITCHARS "[]" ; MACRO fakeram_21x32_1r1w FOREIGN fakeram_21x32_1r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 9.643 BY 9.643 ; + SIZE 17.577 BY 16.741 ; CLASS BLOCK ; PIN w0_wd_in[0] DIRECTION INPUT ; @@ -20,7 +20,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.092 0.072 1.116 ; + RECT 0.000 1.716 0.072 1.740 ; END END w0_wd_in[1] PIN w0_wd_in[2] @@ -29,7 +29,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.908 0.072 1.932 ; + RECT 0.000 3.156 0.072 3.180 ; END END w0_wd_in[2] PIN w0_wd_in[3] @@ -38,7 +38,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.724 0.072 2.748 ; + RECT 0.000 4.596 0.072 4.620 ; END END w0_wd_in[3] PIN w0_wd_in[4] @@ -47,7 +47,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.540 0.072 3.564 ; + RECT 0.000 6.036 0.072 6.060 ; END END w0_wd_in[4] PIN w0_wd_in[5] @@ -56,7 +56,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.356 0.072 4.380 ; + RECT 0.000 7.476 0.072 7.500 ; END END w0_wd_in[5] PIN w0_wd_in[6] @@ -65,7 +65,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 0.276 9.643 0.300 ; + RECT 17.505 0.276 17.577 0.300 ; END END w0_wd_in[6] PIN w0_wd_in[7] @@ -74,7 +74,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 1.092 9.643 1.116 ; + RECT 17.505 1.716 17.577 1.740 ; END END w0_wd_in[7] PIN w0_wd_in[8] @@ -83,7 +83,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 1.908 9.643 1.932 ; + RECT 17.505 3.156 17.577 3.180 ; END END w0_wd_in[8] PIN w0_wd_in[9] @@ -92,7 +92,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 2.724 9.643 2.748 ; + RECT 17.505 4.596 17.577 4.620 ; END END w0_wd_in[9] PIN w0_wd_in[10] @@ -101,11 +101,11 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 3.540 9.643 3.564 ; + RECT 17.505 6.036 17.577 6.060 ; END END w0_wd_in[10] PIN w0_wd_in[11] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -114,84 +114,84 @@ MACRO fakeram_21x32_1r1w END END w0_wd_in[11] PIN w0_wd_in[12] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.603 0.000 0.621 0.054 ; + RECT 0.963 0.000 0.981 0.054 ; END END w0_wd_in[12] PIN w0_wd_in[13] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.999 0.000 1.017 0.054 ; + RECT 1.719 0.000 1.737 0.054 ; END END w0_wd_in[13] PIN w0_wd_in[14] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.395 0.000 1.413 0.054 ; + RECT 2.475 0.000 2.493 0.054 ; END END w0_wd_in[14] PIN w0_wd_in[15] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.791 0.000 1.809 0.054 ; + RECT 3.231 0.000 3.249 0.054 ; END END w0_wd_in[15] PIN w0_wd_in[16] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.187 0.000 2.205 0.054 ; + RECT 3.987 0.000 4.005 0.054 ; END END w0_wd_in[16] PIN w0_wd_in[17] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.583 0.000 2.601 0.054 ; + RECT 4.743 0.000 4.761 0.054 ; END END w0_wd_in[17] PIN w0_wd_in[18] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.979 0.000 2.997 0.054 ; + RECT 5.499 0.000 5.517 0.054 ; END END w0_wd_in[18] PIN w0_wd_in[19] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.375 0.000 3.393 0.054 ; + RECT 6.255 0.000 6.273 0.054 ; END END w0_wd_in[19] PIN w0_wd_in[20] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.771 0.000 3.789 0.054 ; + RECT 7.011 0.000 7.029 0.054 ; END END w0_wd_in[20] PIN r0_rd_out[0] @@ -200,7 +200,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.167 0.000 4.185 0.054 ; + RECT 7.767 0.000 7.785 0.054 ; END END r0_rd_out[0] PIN r0_rd_out[1] @@ -209,7 +209,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.563 0.000 4.581 0.054 ; + RECT 8.523 0.000 8.541 0.054 ; END END r0_rd_out[1] PIN r0_rd_out[2] @@ -218,7 +218,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.959 0.000 4.977 0.054 ; + RECT 9.279 0.000 9.297 0.054 ; END END r0_rd_out[2] PIN r0_rd_out[3] @@ -227,7 +227,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.355 0.000 5.373 0.054 ; + RECT 10.035 0.000 10.053 0.054 ; END END r0_rd_out[3] PIN r0_rd_out[4] @@ -236,7 +236,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.751 0.000 5.769 0.054 ; + RECT 10.791 0.000 10.809 0.054 ; END END r0_rd_out[4] PIN r0_rd_out[5] @@ -245,7 +245,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.147 0.000 6.165 0.054 ; + RECT 11.547 0.000 11.565 0.054 ; END END r0_rd_out[5] PIN r0_rd_out[6] @@ -254,7 +254,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.543 0.000 6.561 0.054 ; + RECT 12.303 0.000 12.321 0.054 ; END END r0_rd_out[6] PIN r0_rd_out[7] @@ -263,7 +263,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.939 0.000 6.957 0.054 ; + RECT 13.059 0.000 13.077 0.054 ; END END r0_rd_out[7] PIN r0_rd_out[8] @@ -272,7 +272,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.335 0.000 7.353 0.054 ; + RECT 13.815 0.000 13.833 0.054 ; END END r0_rd_out[8] PIN r0_rd_out[9] @@ -281,7 +281,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.731 0.000 7.749 0.054 ; + RECT 14.571 0.000 14.589 0.054 ; END END r0_rd_out[9] PIN r0_rd_out[10] @@ -290,7 +290,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.127 0.000 8.145 0.054 ; + RECT 15.327 0.000 15.345 0.054 ; END END r0_rd_out[10] PIN r0_rd_out[11] @@ -299,7 +299,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 9.589 0.225 9.643 ; + RECT 0.207 16.687 0.225 16.741 ; END END r0_rd_out[11] PIN r0_rd_out[12] @@ -308,7 +308,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.747 9.589 0.765 9.643 ; + RECT 1.251 16.687 1.269 16.741 ; END END r0_rd_out[12] PIN r0_rd_out[13] @@ -317,7 +317,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.287 9.589 1.305 9.643 ; + RECT 2.295 16.687 2.313 16.741 ; END END r0_rd_out[13] PIN r0_rd_out[14] @@ -326,7 +326,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.827 9.589 1.845 9.643 ; + RECT 3.339 16.687 3.357 16.741 ; END END r0_rd_out[14] PIN r0_rd_out[15] @@ -335,7 +335,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.367 9.589 2.385 9.643 ; + RECT 4.383 16.687 4.401 16.741 ; END END r0_rd_out[15] PIN r0_rd_out[16] @@ -344,7 +344,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.907 9.589 2.925 9.643 ; + RECT 5.427 16.687 5.445 16.741 ; END END r0_rd_out[16] PIN r0_rd_out[17] @@ -353,7 +353,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.447 9.589 3.465 9.643 ; + RECT 6.471 16.687 6.489 16.741 ; END END r0_rd_out[17] PIN r0_rd_out[18] @@ -362,7 +362,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.987 9.589 4.005 9.643 ; + RECT 7.515 16.687 7.533 16.741 ; END END r0_rd_out[18] PIN r0_rd_out[19] @@ -371,7 +371,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.527 9.589 4.545 9.643 ; + RECT 8.559 16.687 8.577 16.741 ; END END r0_rd_out[19] PIN r0_rd_out[20] @@ -380,7 +380,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.067 9.589 5.085 9.643 ; + RECT 9.603 16.687 9.621 16.741 ; END END r0_rd_out[20] PIN w0_addr_in[0] @@ -389,7 +389,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 5.172 0.072 5.196 ; + RECT 0.000 8.916 0.072 8.940 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -398,7 +398,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 5.988 0.072 6.012 ; + RECT 0.000 10.356 0.072 10.380 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -407,7 +407,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 6.804 0.072 6.828 ; + RECT 0.000 11.796 0.072 11.820 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -416,7 +416,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 4.356 9.643 4.380 ; + RECT 17.505 7.476 17.577 7.500 ; END END w0_addr_in[3] PIN w0_addr_in[4] @@ -425,7 +425,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 5.172 9.643 5.196 ; + RECT 17.505 8.916 17.577 8.940 ; END END w0_addr_in[4] PIN r0_addr_in[0] @@ -434,7 +434,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 7.620 0.072 7.644 ; + RECT 0.000 13.236 0.072 13.260 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -443,7 +443,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 8.436 0.072 8.460 ; + RECT 0.000 14.676 0.072 14.700 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -452,7 +452,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 9.252 0.072 9.276 ; + RECT 0.000 16.116 0.072 16.140 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -461,7 +461,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 5.988 9.643 6.012 ; + RECT 17.505 10.356 17.577 10.380 ; END END r0_addr_in[3] PIN r0_addr_in[4] @@ -470,7 +470,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 6.804 9.643 6.828 ; + RECT 17.505 11.796 17.577 11.820 ; END END r0_addr_in[4] PIN w0_we_in @@ -479,7 +479,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.607 9.589 5.625 9.643 ; + RECT 10.647 16.687 10.665 16.741 ; END END w0_we_in PIN w0_ce_in @@ -488,7 +488,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.147 9.589 6.165 9.643 ; + RECT 11.691 16.687 11.709 16.741 ; END END w0_ce_in PIN w0_clk @@ -497,7 +497,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.687 9.589 6.705 9.643 ; + RECT 12.735 16.687 12.753 16.741 ; END END w0_clk PIN r0_ce_in @@ -506,7 +506,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.227 9.589 7.245 9.643 ; + RECT 13.779 16.687 13.797 16.741 ; END END r0_ce_in PIN r0_clk @@ -515,7 +515,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.767 9.589 7.785 9.643 ; + RECT 14.823 16.687 14.841 16.741 ; END END r0_clk PIN VSS @@ -523,19 +523,28 @@ MACRO fakeram_21x32_1r1w USE GROUND ; PORT LAYER M4 ; - RECT 0.216 0.240 9.427 0.336 ; - RECT 0.216 1.008 9.427 1.104 ; - RECT 0.216 1.776 9.427 1.872 ; - RECT 0.216 2.544 9.427 2.640 ; - RECT 0.216 3.312 9.427 3.408 ; - RECT 0.216 4.080 9.427 4.176 ; - RECT 0.216 4.848 9.427 4.944 ; - RECT 0.216 5.616 9.427 5.712 ; - RECT 0.216 6.384 9.427 6.480 ; - RECT 0.216 7.152 9.427 7.248 ; - RECT 0.216 7.920 9.427 8.016 ; - RECT 0.216 8.688 9.427 8.784 ; - RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 0.240 17.361 0.336 ; + RECT 0.216 1.008 17.361 1.104 ; + RECT 0.216 1.776 17.361 1.872 ; + RECT 0.216 2.544 17.361 2.640 ; + RECT 0.216 3.312 17.361 3.408 ; + RECT 0.216 4.080 17.361 4.176 ; + RECT 0.216 4.848 17.361 4.944 ; + RECT 0.216 5.616 17.361 5.712 ; + RECT 0.216 6.384 17.361 6.480 ; + RECT 0.216 7.152 17.361 7.248 ; + RECT 0.216 7.920 17.361 8.016 ; + RECT 0.216 8.688 17.361 8.784 ; + RECT 0.216 9.456 17.361 9.552 ; + RECT 0.216 10.224 17.361 10.320 ; + RECT 0.216 10.992 17.361 11.088 ; + RECT 0.216 11.760 17.361 11.856 ; + RECT 0.216 12.528 17.361 12.624 ; + RECT 0.216 13.296 17.361 13.392 ; + RECT 0.216 14.064 17.361 14.160 ; + RECT 0.216 14.832 17.361 14.928 ; + RECT 0.216 15.600 17.361 15.696 ; + RECT 0.216 16.368 17.361 16.464 ; END END VSS PIN VDD @@ -543,30 +552,39 @@ MACRO fakeram_21x32_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.216 0.240 9.427 0.336 ; - RECT 0.216 1.008 9.427 1.104 ; - RECT 0.216 1.776 9.427 1.872 ; - RECT 0.216 2.544 9.427 2.640 ; - RECT 0.216 3.312 9.427 3.408 ; - RECT 0.216 4.080 9.427 4.176 ; - RECT 0.216 4.848 9.427 4.944 ; - RECT 0.216 5.616 9.427 5.712 ; - RECT 0.216 6.384 9.427 6.480 ; - RECT 0.216 7.152 9.427 7.248 ; - RECT 0.216 7.920 9.427 8.016 ; - RECT 0.216 8.688 9.427 8.784 ; - RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 0.240 17.361 0.336 ; + RECT 0.216 1.008 17.361 1.104 ; + RECT 0.216 1.776 17.361 1.872 ; + RECT 0.216 2.544 17.361 2.640 ; + RECT 0.216 3.312 17.361 3.408 ; + RECT 0.216 4.080 17.361 4.176 ; + RECT 0.216 4.848 17.361 4.944 ; + RECT 0.216 5.616 17.361 5.712 ; + RECT 0.216 6.384 17.361 6.480 ; + RECT 0.216 7.152 17.361 7.248 ; + RECT 0.216 7.920 17.361 8.016 ; + RECT 0.216 8.688 17.361 8.784 ; + RECT 0.216 9.456 17.361 9.552 ; + RECT 0.216 10.224 17.361 10.320 ; + RECT 0.216 10.992 17.361 11.088 ; + RECT 0.216 11.760 17.361 11.856 ; + RECT 0.216 12.528 17.361 12.624 ; + RECT 0.216 13.296 17.361 13.392 ; + RECT 0.216 14.064 17.361 14.160 ; + RECT 0.216 14.832 17.361 14.928 ; + RECT 0.216 15.600 17.361 15.696 ; + RECT 0.216 16.368 17.361 16.464 ; END END VDD OBS LAYER M1 ; - RECT 0 0 9.643 9.643 ; + RECT 0 0 17.577 16.741 ; LAYER M2 ; - RECT 0 0 9.643 9.643 ; + RECT 0 0 17.577 16.741 ; LAYER M3 ; - RECT 0 0 9.643 9.643 ; + RECT 0 0 17.577 16.741 ; LAYER M4 ; - RECT 0 0 9.643 9.643 ; + RECT 0 0 17.577 16.741 ; END END fakeram_21x32_1r1w diff --git a/designs/asap7/eyeriss/sram/lef/fakeram_21x512_1r1w.lef b/designs/asap7/eyeriss/sram/lef/fakeram_21x512_1r1w.lef index 36a02546..1bab08ab 100644 --- a/designs/asap7/eyeriss/sram/lef/fakeram_21x512_1r1w.lef +++ b/designs/asap7/eyeriss/sram/lef/fakeram_21x512_1r1w.lef @@ -3,7 +3,7 @@ BUSBITCHARS "[]" ; MACRO fakeram_21x512_1r1w FOREIGN fakeram_21x512_1r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 9.643 BY 12.472 ; + SIZE 17.577 BY 33.481 ; CLASS BLOCK ; PIN w0_wd_in[0] DIRECTION INPUT ; @@ -20,7 +20,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.236 0.072 1.260 ; + RECT 0.000 3.012 0.072 3.036 ; END END w0_wd_in[1] PIN w0_wd_in[2] @@ -29,7 +29,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.196 0.072 2.220 ; + RECT 0.000 5.748 0.072 5.772 ; END END w0_wd_in[2] PIN w0_wd_in[3] @@ -38,7 +38,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.156 0.072 3.180 ; + RECT 0.000 8.484 0.072 8.508 ; END END w0_wd_in[3] PIN w0_wd_in[4] @@ -47,7 +47,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.116 0.072 4.140 ; + RECT 0.000 11.220 0.072 11.244 ; END END w0_wd_in[4] PIN w0_wd_in[5] @@ -56,7 +56,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 5.076 0.072 5.100 ; + RECT 0.000 13.956 0.072 13.980 ; END END w0_wd_in[5] PIN w0_wd_in[6] @@ -65,7 +65,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 0.276 9.643 0.300 ; + RECT 17.505 0.276 17.577 0.300 ; END END w0_wd_in[6] PIN w0_wd_in[7] @@ -74,7 +74,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 1.236 9.643 1.260 ; + RECT 17.505 3.012 17.577 3.036 ; END END w0_wd_in[7] PIN w0_wd_in[8] @@ -83,7 +83,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 2.196 9.643 2.220 ; + RECT 17.505 5.748 17.577 5.772 ; END END w0_wd_in[8] PIN w0_wd_in[9] @@ -92,7 +92,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 3.156 9.643 3.180 ; + RECT 17.505 8.484 17.577 8.508 ; END END w0_wd_in[9] PIN w0_wd_in[10] @@ -101,11 +101,11 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 4.116 9.643 4.140 ; + RECT 17.505 11.220 17.577 11.244 ; END END w0_wd_in[10] PIN w0_wd_in[11] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -114,84 +114,84 @@ MACRO fakeram_21x512_1r1w END END w0_wd_in[11] PIN w0_wd_in[12] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.603 0.000 0.621 0.054 ; + RECT 0.963 0.000 0.981 0.054 ; END END w0_wd_in[12] PIN w0_wd_in[13] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.999 0.000 1.017 0.054 ; + RECT 1.719 0.000 1.737 0.054 ; END END w0_wd_in[13] PIN w0_wd_in[14] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.395 0.000 1.413 0.054 ; + RECT 2.475 0.000 2.493 0.054 ; END END w0_wd_in[14] PIN w0_wd_in[15] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.791 0.000 1.809 0.054 ; + RECT 3.231 0.000 3.249 0.054 ; END END w0_wd_in[15] PIN w0_wd_in[16] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.187 0.000 2.205 0.054 ; + RECT 3.987 0.000 4.005 0.054 ; END END w0_wd_in[16] PIN w0_wd_in[17] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.583 0.000 2.601 0.054 ; + RECT 4.743 0.000 4.761 0.054 ; END END w0_wd_in[17] PIN w0_wd_in[18] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.979 0.000 2.997 0.054 ; + RECT 5.499 0.000 5.517 0.054 ; END END w0_wd_in[18] PIN w0_wd_in[19] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.375 0.000 3.393 0.054 ; + RECT 6.255 0.000 6.273 0.054 ; END END w0_wd_in[19] PIN w0_wd_in[20] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.771 0.000 3.789 0.054 ; + RECT 7.011 0.000 7.029 0.054 ; END END w0_wd_in[20] PIN r0_rd_out[0] @@ -200,7 +200,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.167 0.000 4.185 0.054 ; + RECT 7.767 0.000 7.785 0.054 ; END END r0_rd_out[0] PIN r0_rd_out[1] @@ -209,7 +209,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.563 0.000 4.581 0.054 ; + RECT 8.523 0.000 8.541 0.054 ; END END r0_rd_out[1] PIN r0_rd_out[2] @@ -218,7 +218,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.959 0.000 4.977 0.054 ; + RECT 9.279 0.000 9.297 0.054 ; END END r0_rd_out[2] PIN r0_rd_out[3] @@ -227,7 +227,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.355 0.000 5.373 0.054 ; + RECT 10.035 0.000 10.053 0.054 ; END END r0_rd_out[3] PIN r0_rd_out[4] @@ -236,7 +236,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.751 0.000 5.769 0.054 ; + RECT 10.791 0.000 10.809 0.054 ; END END r0_rd_out[4] PIN r0_rd_out[5] @@ -245,7 +245,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.147 0.000 6.165 0.054 ; + RECT 11.547 0.000 11.565 0.054 ; END END r0_rd_out[5] PIN r0_rd_out[6] @@ -254,7 +254,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.543 0.000 6.561 0.054 ; + RECT 12.303 0.000 12.321 0.054 ; END END r0_rd_out[6] PIN r0_rd_out[7] @@ -263,7 +263,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.939 0.000 6.957 0.054 ; + RECT 13.059 0.000 13.077 0.054 ; END END r0_rd_out[7] PIN r0_rd_out[8] @@ -272,7 +272,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.335 0.000 7.353 0.054 ; + RECT 13.815 0.000 13.833 0.054 ; END END r0_rd_out[8] PIN r0_rd_out[9] @@ -281,7 +281,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.731 0.000 7.749 0.054 ; + RECT 14.571 0.000 14.589 0.054 ; END END r0_rd_out[9] PIN r0_rd_out[10] @@ -290,7 +290,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.127 0.000 8.145 0.054 ; + RECT 15.327 0.000 15.345 0.054 ; END END r0_rd_out[10] PIN r0_rd_out[11] @@ -299,7 +299,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 12.418 0.225 12.472 ; + RECT 0.207 33.427 0.225 33.481 ; END END r0_rd_out[11] PIN r0_rd_out[12] @@ -308,7 +308,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.747 12.418 0.765 12.472 ; + RECT 1.251 33.427 1.269 33.481 ; END END r0_rd_out[12] PIN r0_rd_out[13] @@ -317,7 +317,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.287 12.418 1.305 12.472 ; + RECT 2.295 33.427 2.313 33.481 ; END END r0_rd_out[13] PIN r0_rd_out[14] @@ -326,7 +326,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.827 12.418 1.845 12.472 ; + RECT 3.339 33.427 3.357 33.481 ; END END r0_rd_out[14] PIN r0_rd_out[15] @@ -335,7 +335,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.367 12.418 2.385 12.472 ; + RECT 4.383 33.427 4.401 33.481 ; END END r0_rd_out[15] PIN r0_rd_out[16] @@ -344,7 +344,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.907 12.418 2.925 12.472 ; + RECT 5.427 33.427 5.445 33.481 ; END END r0_rd_out[16] PIN r0_rd_out[17] @@ -353,7 +353,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.447 12.418 3.465 12.472 ; + RECT 6.471 33.427 6.489 33.481 ; END END r0_rd_out[17] PIN r0_rd_out[18] @@ -362,7 +362,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.987 12.418 4.005 12.472 ; + RECT 7.515 33.427 7.533 33.481 ; END END r0_rd_out[18] PIN r0_rd_out[19] @@ -371,7 +371,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.527 12.418 4.545 12.472 ; + RECT 8.559 33.427 8.577 33.481 ; END END r0_rd_out[19] PIN r0_rd_out[20] @@ -380,7 +380,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.067 12.418 5.085 12.472 ; + RECT 9.603 33.427 9.621 33.481 ; END END r0_rd_out[20] PIN w0_addr_in[0] @@ -389,7 +389,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 6.036 0.072 6.060 ; + RECT 0.000 16.692 0.072 16.716 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -398,7 +398,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 6.996 0.072 7.020 ; + RECT 0.000 19.428 0.072 19.452 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -407,7 +407,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 7.956 0.072 7.980 ; + RECT 0.000 22.164 0.072 22.188 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -416,7 +416,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 5.076 9.643 5.100 ; + RECT 17.505 13.956 17.577 13.980 ; END END w0_addr_in[3] PIN w0_addr_in[4] @@ -425,7 +425,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 6.036 9.643 6.060 ; + RECT 17.505 16.692 17.577 16.716 ; END END w0_addr_in[4] PIN w0_addr_in[5] @@ -434,7 +434,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 6.996 9.643 7.020 ; + RECT 17.505 19.428 17.577 19.452 ; END END w0_addr_in[5] PIN r0_addr_in[0] @@ -443,7 +443,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 8.916 0.072 8.940 ; + RECT 0.000 24.900 0.072 24.924 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -452,7 +452,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 9.876 0.072 9.900 ; + RECT 0.000 27.636 0.072 27.660 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -461,7 +461,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 10.836 0.072 10.860 ; + RECT 0.000 30.372 0.072 30.396 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -470,7 +470,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 7.956 9.643 7.980 ; + RECT 17.505 22.164 17.577 22.188 ; END END r0_addr_in[3] PIN r0_addr_in[4] @@ -479,7 +479,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 8.916 9.643 8.940 ; + RECT 17.505 24.900 17.577 24.924 ; END END r0_addr_in[4] PIN r0_addr_in[5] @@ -488,7 +488,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 9.876 9.643 9.900 ; + RECT 17.505 27.636 17.577 27.660 ; END END r0_addr_in[5] PIN w0_we_in @@ -497,7 +497,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.607 12.418 5.625 12.472 ; + RECT 10.647 33.427 10.665 33.481 ; END END w0_we_in PIN w0_ce_in @@ -506,7 +506,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.147 12.418 6.165 12.472 ; + RECT 11.691 33.427 11.709 33.481 ; END END w0_ce_in PIN w0_clk @@ -515,7 +515,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.687 12.418 6.705 12.472 ; + RECT 12.735 33.427 12.753 33.481 ; END END w0_clk PIN r0_ce_in @@ -524,7 +524,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.227 12.418 7.245 12.472 ; + RECT 13.779 33.427 13.797 33.481 ; END END r0_ce_in PIN r0_clk @@ -533,7 +533,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.767 12.418 7.785 12.472 ; + RECT 14.823 33.427 14.841 33.481 ; END END r0_clk PIN VSS @@ -541,22 +541,50 @@ MACRO fakeram_21x512_1r1w USE GROUND ; PORT LAYER M4 ; - RECT 0.216 0.240 9.427 0.336 ; - RECT 0.216 1.008 9.427 1.104 ; - RECT 0.216 1.776 9.427 1.872 ; - RECT 0.216 2.544 9.427 2.640 ; - RECT 0.216 3.312 9.427 3.408 ; - RECT 0.216 4.080 9.427 4.176 ; - RECT 0.216 4.848 9.427 4.944 ; - RECT 0.216 5.616 9.427 5.712 ; - RECT 0.216 6.384 9.427 6.480 ; - RECT 0.216 7.152 9.427 7.248 ; - RECT 0.216 7.920 9.427 8.016 ; - RECT 0.216 8.688 9.427 8.784 ; - RECT 0.216 9.456 9.427 9.552 ; - RECT 0.216 10.224 9.427 10.320 ; - RECT 0.216 10.992 9.427 11.088 ; - RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 0.240 17.361 0.336 ; + RECT 0.216 1.008 17.361 1.104 ; + RECT 0.216 1.776 17.361 1.872 ; + RECT 0.216 2.544 17.361 2.640 ; + RECT 0.216 3.312 17.361 3.408 ; + RECT 0.216 4.080 17.361 4.176 ; + RECT 0.216 4.848 17.361 4.944 ; + RECT 0.216 5.616 17.361 5.712 ; + RECT 0.216 6.384 17.361 6.480 ; + RECT 0.216 7.152 17.361 7.248 ; + RECT 0.216 7.920 17.361 8.016 ; + RECT 0.216 8.688 17.361 8.784 ; + RECT 0.216 9.456 17.361 9.552 ; + RECT 0.216 10.224 17.361 10.320 ; + RECT 0.216 10.992 17.361 11.088 ; + RECT 0.216 11.760 17.361 11.856 ; + RECT 0.216 12.528 17.361 12.624 ; + RECT 0.216 13.296 17.361 13.392 ; + RECT 0.216 14.064 17.361 14.160 ; + RECT 0.216 14.832 17.361 14.928 ; + RECT 0.216 15.600 17.361 15.696 ; + RECT 0.216 16.368 17.361 16.464 ; + RECT 0.216 17.136 17.361 17.232 ; + RECT 0.216 17.904 17.361 18.000 ; + RECT 0.216 18.672 17.361 18.768 ; + RECT 0.216 19.440 17.361 19.536 ; + RECT 0.216 20.208 17.361 20.304 ; + RECT 0.216 20.976 17.361 21.072 ; + RECT 0.216 21.744 17.361 21.840 ; + RECT 0.216 22.512 17.361 22.608 ; + RECT 0.216 23.280 17.361 23.376 ; + RECT 0.216 24.048 17.361 24.144 ; + RECT 0.216 24.816 17.361 24.912 ; + RECT 0.216 25.584 17.361 25.680 ; + RECT 0.216 26.352 17.361 26.448 ; + RECT 0.216 27.120 17.361 27.216 ; + RECT 0.216 27.888 17.361 27.984 ; + RECT 0.216 28.656 17.361 28.752 ; + RECT 0.216 29.424 17.361 29.520 ; + RECT 0.216 30.192 17.361 30.288 ; + RECT 0.216 30.960 17.361 31.056 ; + RECT 0.216 31.728 17.361 31.824 ; + RECT 0.216 32.496 17.361 32.592 ; + RECT 0.216 33.264 17.361 33.360 ; END END VSS PIN VDD @@ -564,33 +592,61 @@ MACRO fakeram_21x512_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.216 0.240 9.427 0.336 ; - RECT 0.216 1.008 9.427 1.104 ; - RECT 0.216 1.776 9.427 1.872 ; - RECT 0.216 2.544 9.427 2.640 ; - RECT 0.216 3.312 9.427 3.408 ; - RECT 0.216 4.080 9.427 4.176 ; - RECT 0.216 4.848 9.427 4.944 ; - RECT 0.216 5.616 9.427 5.712 ; - RECT 0.216 6.384 9.427 6.480 ; - RECT 0.216 7.152 9.427 7.248 ; - RECT 0.216 7.920 9.427 8.016 ; - RECT 0.216 8.688 9.427 8.784 ; - RECT 0.216 9.456 9.427 9.552 ; - RECT 0.216 10.224 9.427 10.320 ; - RECT 0.216 10.992 9.427 11.088 ; - RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 0.240 17.361 0.336 ; + RECT 0.216 1.008 17.361 1.104 ; + RECT 0.216 1.776 17.361 1.872 ; + RECT 0.216 2.544 17.361 2.640 ; + RECT 0.216 3.312 17.361 3.408 ; + RECT 0.216 4.080 17.361 4.176 ; + RECT 0.216 4.848 17.361 4.944 ; + RECT 0.216 5.616 17.361 5.712 ; + RECT 0.216 6.384 17.361 6.480 ; + RECT 0.216 7.152 17.361 7.248 ; + RECT 0.216 7.920 17.361 8.016 ; + RECT 0.216 8.688 17.361 8.784 ; + RECT 0.216 9.456 17.361 9.552 ; + RECT 0.216 10.224 17.361 10.320 ; + RECT 0.216 10.992 17.361 11.088 ; + RECT 0.216 11.760 17.361 11.856 ; + RECT 0.216 12.528 17.361 12.624 ; + RECT 0.216 13.296 17.361 13.392 ; + RECT 0.216 14.064 17.361 14.160 ; + RECT 0.216 14.832 17.361 14.928 ; + RECT 0.216 15.600 17.361 15.696 ; + RECT 0.216 16.368 17.361 16.464 ; + RECT 0.216 17.136 17.361 17.232 ; + RECT 0.216 17.904 17.361 18.000 ; + RECT 0.216 18.672 17.361 18.768 ; + RECT 0.216 19.440 17.361 19.536 ; + RECT 0.216 20.208 17.361 20.304 ; + RECT 0.216 20.976 17.361 21.072 ; + RECT 0.216 21.744 17.361 21.840 ; + RECT 0.216 22.512 17.361 22.608 ; + RECT 0.216 23.280 17.361 23.376 ; + RECT 0.216 24.048 17.361 24.144 ; + RECT 0.216 24.816 17.361 24.912 ; + RECT 0.216 25.584 17.361 25.680 ; + RECT 0.216 26.352 17.361 26.448 ; + RECT 0.216 27.120 17.361 27.216 ; + RECT 0.216 27.888 17.361 27.984 ; + RECT 0.216 28.656 17.361 28.752 ; + RECT 0.216 29.424 17.361 29.520 ; + RECT 0.216 30.192 17.361 30.288 ; + RECT 0.216 30.960 17.361 31.056 ; + RECT 0.216 31.728 17.361 31.824 ; + RECT 0.216 32.496 17.361 32.592 ; + RECT 0.216 33.264 17.361 33.360 ; END END VDD OBS LAYER M1 ; - RECT 0 0 9.643 12.472 ; + RECT 0 0 17.577 33.481 ; LAYER M2 ; - RECT 0 0 9.643 12.472 ; + RECT 0 0 17.577 33.481 ; LAYER M3 ; - RECT 0 0 9.643 12.472 ; + RECT 0 0 17.577 33.481 ; LAYER M4 ; - RECT 0 0 9.643 12.472 ; + RECT 0 0 17.577 33.481 ; END END fakeram_21x512_1r1w diff --git a/designs/asap7/eyeriss/sram/lef/fakeram_7x512_1r1w.lef b/designs/asap7/eyeriss/sram/lef/fakeram_7x512_1r1w.lef index 9720fd91..45282020 100644 --- a/designs/asap7/eyeriss/sram/lef/fakeram_7x512_1r1w.lef +++ b/designs/asap7/eyeriss/sram/lef/fakeram_7x512_1r1w.lef @@ -3,7 +3,7 @@ BUSBITCHARS "[]" ; MACRO fakeram_7x512_1r1w FOREIGN fakeram_7x512_1r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 9.643 BY 11.300 ; + SIZE 11.719 BY 16.741 ; CLASS BLOCK ; PIN w0_wd_in[0] DIRECTION INPUT ; @@ -20,7 +20,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.572 0.072 1.596 ; + RECT 0.000 2.244 0.072 2.268 ; END END w0_wd_in[1] PIN w0_wd_in[2] @@ -29,7 +29,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 0.276 9.643 0.300 ; + RECT 11.647 0.276 11.719 0.300 ; END END w0_wd_in[2] PIN w0_wd_in[3] @@ -38,11 +38,11 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 1.572 9.643 1.596 ; + RECT 11.647 2.244 11.719 2.268 ; END END w0_wd_in[3] PIN w0_wd_in[4] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -51,21 +51,21 @@ MACRO fakeram_7x512_1r1w END END w0_wd_in[4] PIN w0_wd_in[5] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.323 0.000 1.341 0.054 ; + RECT 1.611 0.000 1.629 0.054 ; END END w0_wd_in[5] PIN w0_wd_in[6] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.439 0.000 2.457 0.054 ; + RECT 3.015 0.000 3.033 0.054 ; END END w0_wd_in[6] PIN r0_rd_out[0] @@ -74,7 +74,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.555 0.000 3.573 0.054 ; + RECT 4.419 0.000 4.437 0.054 ; END END r0_rd_out[0] PIN r0_rd_out[1] @@ -83,7 +83,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.671 0.000 4.689 0.054 ; + RECT 5.823 0.000 5.841 0.054 ; END END r0_rd_out[1] PIN r0_rd_out[2] @@ -92,7 +92,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.787 0.000 5.805 0.054 ; + RECT 7.227 0.000 7.245 0.054 ; END END r0_rd_out[2] PIN r0_rd_out[3] @@ -101,7 +101,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.903 0.000 6.921 0.054 ; + RECT 8.631 0.000 8.649 0.054 ; END END r0_rd_out[3] PIN r0_rd_out[4] @@ -110,7 +110,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 11.246 0.225 11.300 ; + RECT 0.207 16.687 0.225 16.741 ; END END r0_rd_out[4] PIN r0_rd_out[5] @@ -119,7 +119,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.215 11.246 1.233 11.300 ; + RECT 1.431 16.687 1.449 16.741 ; END END r0_rd_out[5] PIN r0_rd_out[6] @@ -128,7 +128,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.223 11.246 2.241 11.300 ; + RECT 2.655 16.687 2.673 16.741 ; END END r0_rd_out[6] PIN w0_addr_in[0] @@ -137,7 +137,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.868 0.072 2.892 ; + RECT 0.000 4.212 0.072 4.236 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -146,7 +146,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.164 0.072 4.188 ; + RECT 0.000 6.180 0.072 6.204 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -155,7 +155,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 5.460 0.072 5.484 ; + RECT 0.000 8.148 0.072 8.172 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -164,7 +164,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 2.868 9.643 2.892 ; + RECT 11.647 4.212 11.719 4.236 ; END END w0_addr_in[3] PIN w0_addr_in[4] @@ -173,7 +173,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 4.164 9.643 4.188 ; + RECT 11.647 6.180 11.719 6.204 ; END END w0_addr_in[4] PIN w0_addr_in[5] @@ -182,7 +182,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 5.460 9.643 5.484 ; + RECT 11.647 8.148 11.719 8.172 ; END END w0_addr_in[5] PIN r0_addr_in[0] @@ -191,7 +191,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 6.756 0.072 6.780 ; + RECT 0.000 10.116 0.072 10.140 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -200,7 +200,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 8.052 0.072 8.076 ; + RECT 0.000 12.084 0.072 12.108 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -209,7 +209,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 9.348 0.072 9.372 ; + RECT 0.000 14.052 0.072 14.076 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -218,7 +218,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 6.756 9.643 6.780 ; + RECT 11.647 10.116 11.719 10.140 ; END END r0_addr_in[3] PIN r0_addr_in[4] @@ -227,7 +227,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 8.052 9.643 8.076 ; + RECT 11.647 12.084 11.719 12.108 ; END END r0_addr_in[4] PIN r0_addr_in[5] @@ -236,7 +236,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 9.348 9.643 9.372 ; + RECT 11.647 14.052 11.719 14.076 ; END END r0_addr_in[5] PIN w0_we_in @@ -245,7 +245,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.231 11.246 3.249 11.300 ; + RECT 3.879 16.687 3.897 16.741 ; END END w0_we_in PIN w0_ce_in @@ -254,7 +254,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.239 11.246 4.257 11.300 ; + RECT 5.103 16.687 5.121 16.741 ; END END w0_ce_in PIN w0_clk @@ -263,7 +263,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.247 11.246 5.265 11.300 ; + RECT 6.327 16.687 6.345 16.741 ; END END w0_clk PIN r0_ce_in @@ -272,7 +272,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.255 11.246 6.273 11.300 ; + RECT 7.551 16.687 7.569 16.741 ; END END r0_ce_in PIN r0_clk @@ -281,7 +281,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.263 11.246 7.281 11.300 ; + RECT 8.775 16.687 8.793 16.741 ; END END r0_clk PIN VSS @@ -289,21 +289,28 @@ MACRO fakeram_7x512_1r1w USE GROUND ; PORT LAYER M4 ; - RECT 0.216 0.240 9.427 0.336 ; - RECT 0.216 1.008 9.427 1.104 ; - RECT 0.216 1.776 9.427 1.872 ; - RECT 0.216 2.544 9.427 2.640 ; - RECT 0.216 3.312 9.427 3.408 ; - RECT 0.216 4.080 9.427 4.176 ; - RECT 0.216 4.848 9.427 4.944 ; - RECT 0.216 5.616 9.427 5.712 ; - RECT 0.216 6.384 9.427 6.480 ; - RECT 0.216 7.152 9.427 7.248 ; - RECT 0.216 7.920 9.427 8.016 ; - RECT 0.216 8.688 9.427 8.784 ; - RECT 0.216 9.456 9.427 9.552 ; - RECT 0.216 10.224 9.427 10.320 ; - RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 0.240 11.503 0.336 ; + RECT 0.216 1.008 11.503 1.104 ; + RECT 0.216 1.776 11.503 1.872 ; + RECT 0.216 2.544 11.503 2.640 ; + RECT 0.216 3.312 11.503 3.408 ; + RECT 0.216 4.080 11.503 4.176 ; + RECT 0.216 4.848 11.503 4.944 ; + RECT 0.216 5.616 11.503 5.712 ; + RECT 0.216 6.384 11.503 6.480 ; + RECT 0.216 7.152 11.503 7.248 ; + RECT 0.216 7.920 11.503 8.016 ; + RECT 0.216 8.688 11.503 8.784 ; + RECT 0.216 9.456 11.503 9.552 ; + RECT 0.216 10.224 11.503 10.320 ; + RECT 0.216 10.992 11.503 11.088 ; + RECT 0.216 11.760 11.503 11.856 ; + RECT 0.216 12.528 11.503 12.624 ; + RECT 0.216 13.296 11.503 13.392 ; + RECT 0.216 14.064 11.503 14.160 ; + RECT 0.216 14.832 11.503 14.928 ; + RECT 0.216 15.600 11.503 15.696 ; + RECT 0.216 16.368 11.503 16.464 ; END END VSS PIN VDD @@ -311,32 +318,39 @@ MACRO fakeram_7x512_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.216 0.240 9.427 0.336 ; - RECT 0.216 1.008 9.427 1.104 ; - RECT 0.216 1.776 9.427 1.872 ; - RECT 0.216 2.544 9.427 2.640 ; - RECT 0.216 3.312 9.427 3.408 ; - RECT 0.216 4.080 9.427 4.176 ; - RECT 0.216 4.848 9.427 4.944 ; - RECT 0.216 5.616 9.427 5.712 ; - RECT 0.216 6.384 9.427 6.480 ; - RECT 0.216 7.152 9.427 7.248 ; - RECT 0.216 7.920 9.427 8.016 ; - RECT 0.216 8.688 9.427 8.784 ; - RECT 0.216 9.456 9.427 9.552 ; - RECT 0.216 10.224 9.427 10.320 ; - RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 0.240 11.503 0.336 ; + RECT 0.216 1.008 11.503 1.104 ; + RECT 0.216 1.776 11.503 1.872 ; + RECT 0.216 2.544 11.503 2.640 ; + RECT 0.216 3.312 11.503 3.408 ; + RECT 0.216 4.080 11.503 4.176 ; + RECT 0.216 4.848 11.503 4.944 ; + RECT 0.216 5.616 11.503 5.712 ; + RECT 0.216 6.384 11.503 6.480 ; + RECT 0.216 7.152 11.503 7.248 ; + RECT 0.216 7.920 11.503 8.016 ; + RECT 0.216 8.688 11.503 8.784 ; + RECT 0.216 9.456 11.503 9.552 ; + RECT 0.216 10.224 11.503 10.320 ; + RECT 0.216 10.992 11.503 11.088 ; + RECT 0.216 11.760 11.503 11.856 ; + RECT 0.216 12.528 11.503 12.624 ; + RECT 0.216 13.296 11.503 13.392 ; + RECT 0.216 14.064 11.503 14.160 ; + RECT 0.216 14.832 11.503 14.928 ; + RECT 0.216 15.600 11.503 15.696 ; + RECT 0.216 16.368 11.503 16.464 ; END END VDD OBS LAYER M1 ; - RECT 0 0 9.643 11.300 ; + RECT 0 0 11.719 16.741 ; LAYER M2 ; - RECT 0 0 9.643 11.300 ; + RECT 0 0 11.719 16.741 ; LAYER M3 ; - RECT 0 0 9.643 11.300 ; + RECT 0 0 11.719 16.741 ; LAYER M4 ; - RECT 0 0 9.643 11.300 ; + RECT 0 0 11.719 16.741 ; END END fakeram_7x512_1r1w diff --git a/designs/asap7/eyeriss/sram/lef/fakeram_8x4096_1r1w.lef b/designs/asap7/eyeriss/sram/lef/fakeram_8x4096_1r1w.lef index 0890a792..5ac51b9b 100644 --- a/designs/asap7/eyeriss/sram/lef/fakeram_8x4096_1r1w.lef +++ b/designs/asap7/eyeriss/sram/lef/fakeram_8x4096_1r1w.lef @@ -3,7 +3,7 @@ BUSBITCHARS "[]" ; MACRO fakeram_8x4096_1r1w FOREIGN fakeram_8x4096_1r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 9.643 BY 86.379 ; + SIZE 53.569 BY 33.481 ; CLASS BLOCK ; PIN w0_wd_in[0] DIRECTION INPUT ; @@ -20,7 +20,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 8.052 0.072 8.076 ; + RECT 0.000 3.252 0.072 3.276 ; END END w0_wd_in[1] PIN w0_wd_in[2] @@ -29,7 +29,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 0.276 9.643 0.300 ; + RECT 53.497 0.276 53.569 0.300 ; END END w0_wd_in[2] PIN w0_wd_in[3] @@ -38,11 +38,11 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 8.052 9.643 8.076 ; + RECT 53.497 3.252 53.569 3.276 ; END END w0_wd_in[3] PIN w0_wd_in[4] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -51,30 +51,30 @@ MACRO fakeram_8x4096_1r1w END END w0_wd_in[4] PIN w0_wd_in[5] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.323 0.000 1.341 0.054 ; + RECT 6.831 0.000 6.849 0.054 ; END END w0_wd_in[5] PIN w0_wd_in[6] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.439 0.000 2.457 0.054 ; + RECT 13.455 0.000 13.473 0.054 ; END END w0_wd_in[6] PIN w0_wd_in[7] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.555 0.000 3.573 0.054 ; + RECT 20.079 0.000 20.097 0.054 ; END END w0_wd_in[7] PIN r0_rd_out[0] @@ -83,7 +83,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.671 0.000 4.689 0.054 ; + RECT 26.703 0.000 26.721 0.054 ; END END r0_rd_out[0] PIN r0_rd_out[1] @@ -92,7 +92,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.787 0.000 5.805 0.054 ; + RECT 33.327 0.000 33.345 0.054 ; END END r0_rd_out[1] PIN r0_rd_out[2] @@ -101,7 +101,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.903 0.000 6.921 0.054 ; + RECT 39.951 0.000 39.969 0.054 ; END END r0_rd_out[2] PIN r0_rd_out[3] @@ -110,7 +110,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.019 0.000 8.037 0.054 ; + RECT 46.575 0.000 46.593 0.054 ; END END r0_rd_out[3] PIN r0_rd_out[4] @@ -119,7 +119,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 86.325 0.225 86.379 ; + RECT 0.207 33.427 0.225 33.481 ; END END r0_rd_out[4] PIN r0_rd_out[5] @@ -128,7 +128,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.215 86.325 1.233 86.379 ; + RECT 6.075 33.427 6.093 33.481 ; END END r0_rd_out[5] PIN r0_rd_out[6] @@ -137,7 +137,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.223 86.325 2.241 86.379 ; + RECT 11.943 33.427 11.961 33.481 ; END END r0_rd_out[6] PIN r0_rd_out[7] @@ -146,7 +146,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.231 86.325 3.249 86.379 ; + RECT 17.811 33.427 17.829 33.481 ; END END r0_rd_out[7] PIN w0_addr_in[0] @@ -155,7 +155,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 15.828 0.072 15.852 ; + RECT 0.000 6.228 0.072 6.252 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -164,7 +164,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 23.604 0.072 23.628 ; + RECT 0.000 9.204 0.072 9.228 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -173,7 +173,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 31.380 0.072 31.404 ; + RECT 0.000 12.180 0.072 12.204 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -182,7 +182,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 39.156 0.072 39.180 ; + RECT 0.000 15.156 0.072 15.180 ; END END w0_addr_in[3] PIN w0_addr_in[4] @@ -191,7 +191,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 46.932 0.072 46.956 ; + RECT 0.000 18.132 0.072 18.156 ; END END w0_addr_in[4] PIN w0_addr_in[5] @@ -200,7 +200,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 15.828 9.643 15.852 ; + RECT 53.497 6.228 53.569 6.252 ; END END w0_addr_in[5] PIN w0_addr_in[6] @@ -209,7 +209,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 23.604 9.643 23.628 ; + RECT 53.497 9.204 53.569 9.228 ; END END w0_addr_in[6] PIN w0_addr_in[7] @@ -218,7 +218,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 31.380 9.643 31.404 ; + RECT 53.497 12.180 53.569 12.204 ; END END w0_addr_in[7] PIN w0_addr_in[8] @@ -227,7 +227,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 39.156 9.643 39.180 ; + RECT 53.497 15.156 53.569 15.180 ; END END w0_addr_in[8] PIN r0_addr_in[0] @@ -236,7 +236,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 54.708 0.072 54.732 ; + RECT 0.000 21.108 0.072 21.132 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -245,7 +245,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 62.484 0.072 62.508 ; + RECT 0.000 24.084 0.072 24.108 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -254,7 +254,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 70.260 0.072 70.284 ; + RECT 0.000 27.060 0.072 27.084 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -263,7 +263,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 78.036 0.072 78.060 ; + RECT 0.000 30.036 0.072 30.060 ; END END r0_addr_in[3] PIN r0_addr_in[4] @@ -272,7 +272,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 85.812 0.072 85.836 ; + RECT 0.000 33.012 0.072 33.036 ; END END r0_addr_in[4] PIN r0_addr_in[5] @@ -281,7 +281,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 46.932 9.643 46.956 ; + RECT 53.497 18.132 53.569 18.156 ; END END r0_addr_in[5] PIN r0_addr_in[6] @@ -290,7 +290,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 54.708 9.643 54.732 ; + RECT 53.497 21.108 53.569 21.132 ; END END r0_addr_in[6] PIN r0_addr_in[7] @@ -299,7 +299,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 62.484 9.643 62.508 ; + RECT 53.497 24.084 53.569 24.108 ; END END r0_addr_in[7] PIN r0_addr_in[8] @@ -308,7 +308,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.571 70.260 9.643 70.284 ; + RECT 53.497 27.060 53.569 27.084 ; END END r0_addr_in[8] PIN w0_we_in @@ -317,7 +317,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.239 86.325 4.257 86.379 ; + RECT 23.679 33.427 23.697 33.481 ; END END w0_we_in PIN w0_ce_in @@ -326,7 +326,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.247 86.325 5.265 86.379 ; + RECT 29.547 33.427 29.565 33.481 ; END END w0_ce_in PIN w0_clk @@ -335,7 +335,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.255 86.325 6.273 86.379 ; + RECT 35.415 33.427 35.433 33.481 ; END END w0_clk PIN r0_ce_in @@ -344,7 +344,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.263 86.325 7.281 86.379 ; + RECT 41.283 33.427 41.301 33.481 ; END END r0_ce_in PIN r0_clk @@ -353,7 +353,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.271 86.325 8.289 86.379 ; + RECT 47.151 33.427 47.169 33.481 ; END END r0_clk PIN VSS @@ -361,119 +361,50 @@ MACRO fakeram_8x4096_1r1w USE GROUND ; PORT LAYER M4 ; - RECT 0.216 0.240 9.427 0.336 ; - RECT 0.216 1.008 9.427 1.104 ; - RECT 0.216 1.776 9.427 1.872 ; - RECT 0.216 2.544 9.427 2.640 ; - RECT 0.216 3.312 9.427 3.408 ; - RECT 0.216 4.080 9.427 4.176 ; - RECT 0.216 4.848 9.427 4.944 ; - RECT 0.216 5.616 9.427 5.712 ; - RECT 0.216 6.384 9.427 6.480 ; - RECT 0.216 7.152 9.427 7.248 ; - RECT 0.216 7.920 9.427 8.016 ; - RECT 0.216 8.688 9.427 8.784 ; - RECT 0.216 9.456 9.427 9.552 ; - RECT 0.216 10.224 9.427 10.320 ; - RECT 0.216 10.992 9.427 11.088 ; - RECT 0.216 11.760 9.427 11.856 ; - RECT 0.216 12.528 9.427 12.624 ; - RECT 0.216 13.296 9.427 13.392 ; - RECT 0.216 14.064 9.427 14.160 ; - RECT 0.216 14.832 9.427 14.928 ; - RECT 0.216 15.600 9.427 15.696 ; - RECT 0.216 16.368 9.427 16.464 ; - RECT 0.216 17.136 9.427 17.232 ; - RECT 0.216 17.904 9.427 18.000 ; - RECT 0.216 18.672 9.427 18.768 ; - RECT 0.216 19.440 9.427 19.536 ; - RECT 0.216 20.208 9.427 20.304 ; - RECT 0.216 20.976 9.427 21.072 ; - RECT 0.216 21.744 9.427 21.840 ; - RECT 0.216 22.512 9.427 22.608 ; - RECT 0.216 23.280 9.427 23.376 ; - RECT 0.216 24.048 9.427 24.144 ; - RECT 0.216 24.816 9.427 24.912 ; - RECT 0.216 25.584 9.427 25.680 ; - RECT 0.216 26.352 9.427 26.448 ; - RECT 0.216 27.120 9.427 27.216 ; - RECT 0.216 27.888 9.427 27.984 ; - RECT 0.216 28.656 9.427 28.752 ; - RECT 0.216 29.424 9.427 29.520 ; - RECT 0.216 30.192 9.427 30.288 ; - RECT 0.216 30.960 9.427 31.056 ; - RECT 0.216 31.728 9.427 31.824 ; - RECT 0.216 32.496 9.427 32.592 ; - RECT 0.216 33.264 9.427 33.360 ; - RECT 0.216 34.032 9.427 34.128 ; - RECT 0.216 34.800 9.427 34.896 ; - RECT 0.216 35.568 9.427 35.664 ; - RECT 0.216 36.336 9.427 36.432 ; - RECT 0.216 37.104 9.427 37.200 ; - RECT 0.216 37.872 9.427 37.968 ; - RECT 0.216 38.640 9.427 38.736 ; - RECT 0.216 39.408 9.427 39.504 ; - RECT 0.216 40.176 9.427 40.272 ; - RECT 0.216 40.944 9.427 41.040 ; - RECT 0.216 41.712 9.427 41.808 ; - RECT 0.216 42.480 9.427 42.576 ; - RECT 0.216 43.248 9.427 43.344 ; - RECT 0.216 44.016 9.427 44.112 ; - RECT 0.216 44.784 9.427 44.880 ; - RECT 0.216 45.552 9.427 45.648 ; - RECT 0.216 46.320 9.427 46.416 ; - RECT 0.216 47.088 9.427 47.184 ; - RECT 0.216 47.856 9.427 47.952 ; - RECT 0.216 48.624 9.427 48.720 ; - RECT 0.216 49.392 9.427 49.488 ; - RECT 0.216 50.160 9.427 50.256 ; - RECT 0.216 50.928 9.427 51.024 ; - RECT 0.216 51.696 9.427 51.792 ; - RECT 0.216 52.464 9.427 52.560 ; - RECT 0.216 53.232 9.427 53.328 ; - RECT 0.216 54.000 9.427 54.096 ; - RECT 0.216 54.768 9.427 54.864 ; - RECT 0.216 55.536 9.427 55.632 ; - RECT 0.216 56.304 9.427 56.400 ; - RECT 0.216 57.072 9.427 57.168 ; - RECT 0.216 57.840 9.427 57.936 ; - RECT 0.216 58.608 9.427 58.704 ; - RECT 0.216 59.376 9.427 59.472 ; - RECT 0.216 60.144 9.427 60.240 ; - RECT 0.216 60.912 9.427 61.008 ; - RECT 0.216 61.680 9.427 61.776 ; - RECT 0.216 62.448 9.427 62.544 ; - RECT 0.216 63.216 9.427 63.312 ; - RECT 0.216 63.984 9.427 64.080 ; - RECT 0.216 64.752 9.427 64.848 ; - RECT 0.216 65.520 9.427 65.616 ; - RECT 0.216 66.288 9.427 66.384 ; - RECT 0.216 67.056 9.427 67.152 ; - RECT 0.216 67.824 9.427 67.920 ; - RECT 0.216 68.592 9.427 68.688 ; - RECT 0.216 69.360 9.427 69.456 ; - RECT 0.216 70.128 9.427 70.224 ; - RECT 0.216 70.896 9.427 70.992 ; - RECT 0.216 71.664 9.427 71.760 ; - RECT 0.216 72.432 9.427 72.528 ; - RECT 0.216 73.200 9.427 73.296 ; - RECT 0.216 73.968 9.427 74.064 ; - RECT 0.216 74.736 9.427 74.832 ; - RECT 0.216 75.504 9.427 75.600 ; - RECT 0.216 76.272 9.427 76.368 ; - RECT 0.216 77.040 9.427 77.136 ; - RECT 0.216 77.808 9.427 77.904 ; - RECT 0.216 78.576 9.427 78.672 ; - RECT 0.216 79.344 9.427 79.440 ; - RECT 0.216 80.112 9.427 80.208 ; - RECT 0.216 80.880 9.427 80.976 ; - RECT 0.216 81.648 9.427 81.744 ; - RECT 0.216 82.416 9.427 82.512 ; - RECT 0.216 83.184 9.427 83.280 ; - RECT 0.216 83.952 9.427 84.048 ; - RECT 0.216 84.720 9.427 84.816 ; - RECT 0.216 85.488 9.427 85.584 ; - RECT 0.216 86.256 9.427 86.352 ; + RECT 0.216 0.240 53.353 0.336 ; + RECT 0.216 1.008 53.353 1.104 ; + RECT 0.216 1.776 53.353 1.872 ; + RECT 0.216 2.544 53.353 2.640 ; + RECT 0.216 3.312 53.353 3.408 ; + RECT 0.216 4.080 53.353 4.176 ; + RECT 0.216 4.848 53.353 4.944 ; + RECT 0.216 5.616 53.353 5.712 ; + RECT 0.216 6.384 53.353 6.480 ; + RECT 0.216 7.152 53.353 7.248 ; + RECT 0.216 7.920 53.353 8.016 ; + RECT 0.216 8.688 53.353 8.784 ; + RECT 0.216 9.456 53.353 9.552 ; + RECT 0.216 10.224 53.353 10.320 ; + RECT 0.216 10.992 53.353 11.088 ; + RECT 0.216 11.760 53.353 11.856 ; + RECT 0.216 12.528 53.353 12.624 ; + RECT 0.216 13.296 53.353 13.392 ; + RECT 0.216 14.064 53.353 14.160 ; + RECT 0.216 14.832 53.353 14.928 ; + RECT 0.216 15.600 53.353 15.696 ; + RECT 0.216 16.368 53.353 16.464 ; + RECT 0.216 17.136 53.353 17.232 ; + RECT 0.216 17.904 53.353 18.000 ; + RECT 0.216 18.672 53.353 18.768 ; + RECT 0.216 19.440 53.353 19.536 ; + RECT 0.216 20.208 53.353 20.304 ; + RECT 0.216 20.976 53.353 21.072 ; + RECT 0.216 21.744 53.353 21.840 ; + RECT 0.216 22.512 53.353 22.608 ; + RECT 0.216 23.280 53.353 23.376 ; + RECT 0.216 24.048 53.353 24.144 ; + RECT 0.216 24.816 53.353 24.912 ; + RECT 0.216 25.584 53.353 25.680 ; + RECT 0.216 26.352 53.353 26.448 ; + RECT 0.216 27.120 53.353 27.216 ; + RECT 0.216 27.888 53.353 27.984 ; + RECT 0.216 28.656 53.353 28.752 ; + RECT 0.216 29.424 53.353 29.520 ; + RECT 0.216 30.192 53.353 30.288 ; + RECT 0.216 30.960 53.353 31.056 ; + RECT 0.216 31.728 53.353 31.824 ; + RECT 0.216 32.496 53.353 32.592 ; + RECT 0.216 33.264 53.353 33.360 ; END END VSS PIN VDD @@ -481,130 +412,61 @@ MACRO fakeram_8x4096_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.216 0.240 9.427 0.336 ; - RECT 0.216 1.008 9.427 1.104 ; - RECT 0.216 1.776 9.427 1.872 ; - RECT 0.216 2.544 9.427 2.640 ; - RECT 0.216 3.312 9.427 3.408 ; - RECT 0.216 4.080 9.427 4.176 ; - RECT 0.216 4.848 9.427 4.944 ; - RECT 0.216 5.616 9.427 5.712 ; - RECT 0.216 6.384 9.427 6.480 ; - RECT 0.216 7.152 9.427 7.248 ; - RECT 0.216 7.920 9.427 8.016 ; - RECT 0.216 8.688 9.427 8.784 ; - RECT 0.216 9.456 9.427 9.552 ; - RECT 0.216 10.224 9.427 10.320 ; - RECT 0.216 10.992 9.427 11.088 ; - RECT 0.216 11.760 9.427 11.856 ; - RECT 0.216 12.528 9.427 12.624 ; - RECT 0.216 13.296 9.427 13.392 ; - RECT 0.216 14.064 9.427 14.160 ; - RECT 0.216 14.832 9.427 14.928 ; - RECT 0.216 15.600 9.427 15.696 ; - RECT 0.216 16.368 9.427 16.464 ; - RECT 0.216 17.136 9.427 17.232 ; - RECT 0.216 17.904 9.427 18.000 ; - RECT 0.216 18.672 9.427 18.768 ; - RECT 0.216 19.440 9.427 19.536 ; - RECT 0.216 20.208 9.427 20.304 ; - RECT 0.216 20.976 9.427 21.072 ; - RECT 0.216 21.744 9.427 21.840 ; - RECT 0.216 22.512 9.427 22.608 ; - RECT 0.216 23.280 9.427 23.376 ; - RECT 0.216 24.048 9.427 24.144 ; - RECT 0.216 24.816 9.427 24.912 ; - RECT 0.216 25.584 9.427 25.680 ; - RECT 0.216 26.352 9.427 26.448 ; - RECT 0.216 27.120 9.427 27.216 ; - RECT 0.216 27.888 9.427 27.984 ; - RECT 0.216 28.656 9.427 28.752 ; - RECT 0.216 29.424 9.427 29.520 ; - RECT 0.216 30.192 9.427 30.288 ; - RECT 0.216 30.960 9.427 31.056 ; - RECT 0.216 31.728 9.427 31.824 ; - RECT 0.216 32.496 9.427 32.592 ; - RECT 0.216 33.264 9.427 33.360 ; - RECT 0.216 34.032 9.427 34.128 ; - RECT 0.216 34.800 9.427 34.896 ; - RECT 0.216 35.568 9.427 35.664 ; - RECT 0.216 36.336 9.427 36.432 ; - RECT 0.216 37.104 9.427 37.200 ; - RECT 0.216 37.872 9.427 37.968 ; - RECT 0.216 38.640 9.427 38.736 ; - RECT 0.216 39.408 9.427 39.504 ; - RECT 0.216 40.176 9.427 40.272 ; - RECT 0.216 40.944 9.427 41.040 ; - RECT 0.216 41.712 9.427 41.808 ; - RECT 0.216 42.480 9.427 42.576 ; - RECT 0.216 43.248 9.427 43.344 ; - RECT 0.216 44.016 9.427 44.112 ; - RECT 0.216 44.784 9.427 44.880 ; - RECT 0.216 45.552 9.427 45.648 ; - RECT 0.216 46.320 9.427 46.416 ; - RECT 0.216 47.088 9.427 47.184 ; - RECT 0.216 47.856 9.427 47.952 ; - RECT 0.216 48.624 9.427 48.720 ; - RECT 0.216 49.392 9.427 49.488 ; - RECT 0.216 50.160 9.427 50.256 ; - RECT 0.216 50.928 9.427 51.024 ; - RECT 0.216 51.696 9.427 51.792 ; - RECT 0.216 52.464 9.427 52.560 ; - RECT 0.216 53.232 9.427 53.328 ; - RECT 0.216 54.000 9.427 54.096 ; - RECT 0.216 54.768 9.427 54.864 ; - RECT 0.216 55.536 9.427 55.632 ; - RECT 0.216 56.304 9.427 56.400 ; - RECT 0.216 57.072 9.427 57.168 ; - RECT 0.216 57.840 9.427 57.936 ; - RECT 0.216 58.608 9.427 58.704 ; - RECT 0.216 59.376 9.427 59.472 ; - RECT 0.216 60.144 9.427 60.240 ; - RECT 0.216 60.912 9.427 61.008 ; - RECT 0.216 61.680 9.427 61.776 ; - RECT 0.216 62.448 9.427 62.544 ; - RECT 0.216 63.216 9.427 63.312 ; - RECT 0.216 63.984 9.427 64.080 ; - RECT 0.216 64.752 9.427 64.848 ; - RECT 0.216 65.520 9.427 65.616 ; - RECT 0.216 66.288 9.427 66.384 ; - RECT 0.216 67.056 9.427 67.152 ; - RECT 0.216 67.824 9.427 67.920 ; - RECT 0.216 68.592 9.427 68.688 ; - RECT 0.216 69.360 9.427 69.456 ; - RECT 0.216 70.128 9.427 70.224 ; - RECT 0.216 70.896 9.427 70.992 ; - RECT 0.216 71.664 9.427 71.760 ; - RECT 0.216 72.432 9.427 72.528 ; - RECT 0.216 73.200 9.427 73.296 ; - RECT 0.216 73.968 9.427 74.064 ; - RECT 0.216 74.736 9.427 74.832 ; - RECT 0.216 75.504 9.427 75.600 ; - RECT 0.216 76.272 9.427 76.368 ; - RECT 0.216 77.040 9.427 77.136 ; - RECT 0.216 77.808 9.427 77.904 ; - RECT 0.216 78.576 9.427 78.672 ; - RECT 0.216 79.344 9.427 79.440 ; - RECT 0.216 80.112 9.427 80.208 ; - RECT 0.216 80.880 9.427 80.976 ; - RECT 0.216 81.648 9.427 81.744 ; - RECT 0.216 82.416 9.427 82.512 ; - RECT 0.216 83.184 9.427 83.280 ; - RECT 0.216 83.952 9.427 84.048 ; - RECT 0.216 84.720 9.427 84.816 ; - RECT 0.216 85.488 9.427 85.584 ; - RECT 0.216 86.256 9.427 86.352 ; + RECT 0.216 0.240 53.353 0.336 ; + RECT 0.216 1.008 53.353 1.104 ; + RECT 0.216 1.776 53.353 1.872 ; + RECT 0.216 2.544 53.353 2.640 ; + RECT 0.216 3.312 53.353 3.408 ; + RECT 0.216 4.080 53.353 4.176 ; + RECT 0.216 4.848 53.353 4.944 ; + RECT 0.216 5.616 53.353 5.712 ; + RECT 0.216 6.384 53.353 6.480 ; + RECT 0.216 7.152 53.353 7.248 ; + RECT 0.216 7.920 53.353 8.016 ; + RECT 0.216 8.688 53.353 8.784 ; + RECT 0.216 9.456 53.353 9.552 ; + RECT 0.216 10.224 53.353 10.320 ; + RECT 0.216 10.992 53.353 11.088 ; + RECT 0.216 11.760 53.353 11.856 ; + RECT 0.216 12.528 53.353 12.624 ; + RECT 0.216 13.296 53.353 13.392 ; + RECT 0.216 14.064 53.353 14.160 ; + RECT 0.216 14.832 53.353 14.928 ; + RECT 0.216 15.600 53.353 15.696 ; + RECT 0.216 16.368 53.353 16.464 ; + RECT 0.216 17.136 53.353 17.232 ; + RECT 0.216 17.904 53.353 18.000 ; + RECT 0.216 18.672 53.353 18.768 ; + RECT 0.216 19.440 53.353 19.536 ; + RECT 0.216 20.208 53.353 20.304 ; + RECT 0.216 20.976 53.353 21.072 ; + RECT 0.216 21.744 53.353 21.840 ; + RECT 0.216 22.512 53.353 22.608 ; + RECT 0.216 23.280 53.353 23.376 ; + RECT 0.216 24.048 53.353 24.144 ; + RECT 0.216 24.816 53.353 24.912 ; + RECT 0.216 25.584 53.353 25.680 ; + RECT 0.216 26.352 53.353 26.448 ; + RECT 0.216 27.120 53.353 27.216 ; + RECT 0.216 27.888 53.353 27.984 ; + RECT 0.216 28.656 53.353 28.752 ; + RECT 0.216 29.424 53.353 29.520 ; + RECT 0.216 30.192 53.353 30.288 ; + RECT 0.216 30.960 53.353 31.056 ; + RECT 0.216 31.728 53.353 31.824 ; + RECT 0.216 32.496 53.353 32.592 ; + RECT 0.216 33.264 53.353 33.360 ; END END VDD OBS LAYER M1 ; - RECT 0 0 9.643 86.379 ; + RECT 0 0 53.569 33.481 ; LAYER M2 ; - RECT 0 0 9.643 86.379 ; + RECT 0 0 53.569 33.481 ; LAYER M3 ; - RECT 0 0 9.643 86.379 ; + RECT 0 0 53.569 33.481 ; LAYER M4 ; - RECT 0 0 9.643 86.379 ; + RECT 0 0 53.569 33.481 ; END END fakeram_8x4096_1r1w diff --git a/designs/asap7/eyeriss/sram/lib/fakeram_12x128_1rw.lib b/designs/asap7/eyeriss/sram/lib/fakeram_12x128_1rw.lib index cab1d187..822c0991 100644 --- a/designs/asap7/eyeriss/sram/lib/fakeram_12x128_1rw.lib +++ b/designs/asap7/eyeriss/sram/lib/fakeram_12x128_1rw.lib @@ -2,7 +2,7 @@ library(fakeram_12x128_1rw) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-05-11 03:52:59Z"; + date : "2026-08-13 14:43:13Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -88,7 +88,7 @@ library(fakeram_12x128_1rw) { downto : true ; } cell(fakeram_12x128_1rw) { - area : 90.030; + area : 279.936; interface_timing : true; memory() { type : ram; diff --git a/designs/asap7/eyeriss/sram/lib/fakeram_12x2048_1r1w.lib b/designs/asap7/eyeriss/sram/lib/fakeram_12x2048_1r1w.lib index 5a41acf6..358429aa 100644 --- a/designs/asap7/eyeriss/sram/lib/fakeram_12x2048_1r1w.lib +++ b/designs/asap7/eyeriss/sram/lib/fakeram_12x2048_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_12x2048_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-05-20 13:24:21Z"; + date : "2026-08-13 14:43:13Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -88,7 +88,7 @@ library(fakeram_12x2048_1r1w) { downto : true ; } cell(fakeram_12x2048_1r1w) { - area : 422.932; + area : 1345.133; interface_timing : true; memory() { type : ram; diff --git a/designs/asap7/eyeriss/sram/lib/fakeram_13x256_1rw.lib b/designs/asap7/eyeriss/sram/lib/fakeram_13x256_1rw.lib index 1c8c80c7..8f590db0 100644 --- a/designs/asap7/eyeriss/sram/lib/fakeram_13x256_1rw.lib +++ b/designs/asap7/eyeriss/sram/lib/fakeram_13x256_1rw.lib @@ -2,7 +2,7 @@ library(fakeram_13x256_1rw) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-05-20 13:24:21Z"; + date : "2026-08-13 14:43:13Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -88,7 +88,7 @@ library(fakeram_13x256_1rw) { downto : true ; } cell(fakeram_13x256_1rw) { - area : 38.701; + area : 75.816; interface_timing : true; memory() { type : ram; diff --git a/designs/asap7/eyeriss/sram/lib/fakeram_21x32_1r1w.lib b/designs/asap7/eyeriss/sram/lib/fakeram_21x32_1r1w.lib index f77badb3..6c4145e9 100644 --- a/designs/asap7/eyeriss/sram/lib/fakeram_21x32_1r1w.lib +++ b/designs/asap7/eyeriss/sram/lib/fakeram_21x32_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_21x32_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-05-11 03:52:59Z"; + date : "2026-08-13 14:43:13Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -88,7 +88,7 @@ library(fakeram_21x32_1r1w) { downto : true ; } cell(fakeram_21x32_1r1w) { - area : 92.987; + area : 294.257; interface_timing : true; memory() { type : ram; diff --git a/designs/asap7/eyeriss/sram/lib/fakeram_21x512_1r1w.lib b/designs/asap7/eyeriss/sram/lib/fakeram_21x512_1r1w.lib index 1dc9a474..f6c0b621 100644 --- a/designs/asap7/eyeriss/sram/lib/fakeram_21x512_1r1w.lib +++ b/designs/asap7/eyeriss/sram/lib/fakeram_21x512_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_21x512_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-05-20 13:24:21Z"; + date : "2026-08-13 14:43:13Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -88,7 +88,7 @@ library(fakeram_21x512_1r1w) { downto : true ; } cell(fakeram_21x512_1r1w) { - area : 120.267; + area : 588.496; interface_timing : true; memory() { type : ram; diff --git a/designs/asap7/eyeriss/sram/lib/fakeram_7x512_1r1w.lib b/designs/asap7/eyeriss/sram/lib/fakeram_7x512_1r1w.lib index a0175777..81792860 100644 --- a/designs/asap7/eyeriss/sram/lib/fakeram_7x512_1r1w.lib +++ b/designs/asap7/eyeriss/sram/lib/fakeram_7x512_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_7x512_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-05-20 13:24:21Z"; + date : "2026-08-13 14:43:13Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -88,7 +88,7 @@ library(fakeram_7x512_1r1w) { downto : true ; } cell(fakeram_7x512_1r1w) { - area : 108.966; + area : 196.188; interface_timing : true; memory() { type : ram; diff --git a/designs/asap7/eyeriss/sram/lib/fakeram_8x4096_1r1w.lib b/designs/asap7/eyeriss/sram/lib/fakeram_8x4096_1r1w.lib index 6d35de6c..1b2f6919 100644 --- a/designs/asap7/eyeriss/sram/lib/fakeram_8x4096_1r1w.lib +++ b/designs/asap7/eyeriss/sram/lib/fakeram_8x4096_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_8x4096_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-05-11 03:52:59Z"; + date : "2026-08-13 14:43:13Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -88,7 +88,7 @@ library(fakeram_8x4096_1r1w) { downto : true ; } cell(fakeram_8x4096_1r1w) { - area : 832.953; + area : 1793.544; interface_timing : true; memory() { type : ram; diff --git a/designs/nangate45/eyeriss/BUILD.bazel b/designs/nangate45/eyeriss/BUILD.bazel index 78d993c9..12a06e9b 100644 --- a/designs/nangate45/eyeriss/BUILD.bazel +++ b/designs/nangate45/eyeriss/BUILD.bazel @@ -12,7 +12,7 @@ filegroup( # Eyeriss v2 sparse-CNN accelerator on nangate45. Same RTL as asap7 — 2x2 # cluster group array with 9 PEs per cluster — but FakeRAMs are regenerated -# for the 45nm metal stack via designs/nangate45/eyeriss/sram/fakeram_nangate45.cfg. +# for the 45nm metal stack via designs/src/eyeriss/dev/generated/fakeram_nangate45.cfg. hightide_design( name = "eyeriss", top = "TOP", diff --git a/designs/nangate45/eyeriss/sram/lef/fakeram_12x128_1rw.lef b/designs/nangate45/eyeriss/sram/lef/fakeram_12x128_1rw.lef index f070983d..51f20012 100644 --- a/designs/nangate45/eyeriss/sram/lef/fakeram_12x128_1rw.lef +++ b/designs/nangate45/eyeriss/sram/lef/fakeram_12x128_1rw.lef @@ -60,7 +60,7 @@ MACRO fakeram_12x128_1rw END END rw0_wd_in[5] PIN rw0_wd_in[6] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -69,7 +69,7 @@ MACRO fakeram_12x128_1rw END END rw0_wd_in[6] PIN rw0_wd_in[7] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -78,7 +78,7 @@ MACRO fakeram_12x128_1rw END END rw0_wd_in[7] PIN rw0_wd_in[8] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -87,7 +87,7 @@ MACRO fakeram_12x128_1rw END END rw0_wd_in[8] PIN rw0_wd_in[9] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -96,7 +96,7 @@ MACRO fakeram_12x128_1rw END END rw0_wd_in[9] PIN rw0_wd_in[10] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -105,7 +105,7 @@ MACRO fakeram_12x128_1rw END END rw0_wd_in[10] PIN rw0_wd_in[11] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT diff --git a/designs/nangate45/eyeriss/sram/lef/fakeram_12x2048_1r1w.lef b/designs/nangate45/eyeriss/sram/lef/fakeram_12x2048_1r1w.lef index 80194775..50920671 100644 --- a/designs/nangate45/eyeriss/sram/lef/fakeram_12x2048_1r1w.lef +++ b/designs/nangate45/eyeriss/sram/lef/fakeram_12x2048_1r1w.lef @@ -60,7 +60,7 @@ MACRO fakeram_12x2048_1r1w END END w0_wd_in[5] PIN w0_wd_in[6] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -69,7 +69,7 @@ MACRO fakeram_12x2048_1r1w END END w0_wd_in[6] PIN w0_wd_in[7] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -78,7 +78,7 @@ MACRO fakeram_12x2048_1r1w END END w0_wd_in[7] PIN w0_wd_in[8] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -87,7 +87,7 @@ MACRO fakeram_12x2048_1r1w END END w0_wd_in[8] PIN w0_wd_in[9] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -96,7 +96,7 @@ MACRO fakeram_12x2048_1r1w END END w0_wd_in[9] PIN w0_wd_in[10] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -105,7 +105,7 @@ MACRO fakeram_12x2048_1r1w END END w0_wd_in[10] PIN w0_wd_in[11] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT diff --git a/designs/nangate45/eyeriss/sram/lef/fakeram_13x256_1rw.lef b/designs/nangate45/eyeriss/sram/lef/fakeram_13x256_1rw.lef index 8bfd73da..ca0f1f7f 100644 --- a/designs/nangate45/eyeriss/sram/lef/fakeram_13x256_1rw.lef +++ b/designs/nangate45/eyeriss/sram/lef/fakeram_13x256_1rw.lef @@ -69,7 +69,7 @@ MACRO fakeram_13x256_1rw END END rw0_wd_in[6] PIN rw0_wd_in[7] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -78,7 +78,7 @@ MACRO fakeram_13x256_1rw END END rw0_wd_in[7] PIN rw0_wd_in[8] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -87,7 +87,7 @@ MACRO fakeram_13x256_1rw END END rw0_wd_in[8] PIN rw0_wd_in[9] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -96,7 +96,7 @@ MACRO fakeram_13x256_1rw END END rw0_wd_in[9] PIN rw0_wd_in[10] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -105,7 +105,7 @@ MACRO fakeram_13x256_1rw END END rw0_wd_in[10] PIN rw0_wd_in[11] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -114,7 +114,7 @@ MACRO fakeram_13x256_1rw END END rw0_wd_in[11] PIN rw0_wd_in[12] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT diff --git a/designs/nangate45/eyeriss/sram/lef/fakeram_21x32_1r1w.lef b/designs/nangate45/eyeriss/sram/lef/fakeram_21x32_1r1w.lef index 4cae7134..54755b5a 100644 --- a/designs/nangate45/eyeriss/sram/lef/fakeram_21x32_1r1w.lef +++ b/designs/nangate45/eyeriss/sram/lef/fakeram_21x32_1r1w.lef @@ -105,7 +105,7 @@ MACRO fakeram_21x32_1r1w END END w0_wd_in[10] PIN w0_wd_in[11] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -114,7 +114,7 @@ MACRO fakeram_21x32_1r1w END END w0_wd_in[11] PIN w0_wd_in[12] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -123,7 +123,7 @@ MACRO fakeram_21x32_1r1w END END w0_wd_in[12] PIN w0_wd_in[13] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -132,7 +132,7 @@ MACRO fakeram_21x32_1r1w END END w0_wd_in[13] PIN w0_wd_in[14] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -141,7 +141,7 @@ MACRO fakeram_21x32_1r1w END END w0_wd_in[14] PIN w0_wd_in[15] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -150,7 +150,7 @@ MACRO fakeram_21x32_1r1w END END w0_wd_in[15] PIN w0_wd_in[16] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -159,7 +159,7 @@ MACRO fakeram_21x32_1r1w END END w0_wd_in[16] PIN w0_wd_in[17] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -168,7 +168,7 @@ MACRO fakeram_21x32_1r1w END END w0_wd_in[17] PIN w0_wd_in[18] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -177,7 +177,7 @@ MACRO fakeram_21x32_1r1w END END w0_wd_in[18] PIN w0_wd_in[19] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -186,7 +186,7 @@ MACRO fakeram_21x32_1r1w END END w0_wd_in[19] PIN w0_wd_in[20] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT diff --git a/designs/nangate45/eyeriss/sram/lef/fakeram_21x512_1r1w.lef b/designs/nangate45/eyeriss/sram/lef/fakeram_21x512_1r1w.lef index 5f3f14dc..962a3542 100644 --- a/designs/nangate45/eyeriss/sram/lef/fakeram_21x512_1r1w.lef +++ b/designs/nangate45/eyeriss/sram/lef/fakeram_21x512_1r1w.lef @@ -105,7 +105,7 @@ MACRO fakeram_21x512_1r1w END END w0_wd_in[10] PIN w0_wd_in[11] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -114,7 +114,7 @@ MACRO fakeram_21x512_1r1w END END w0_wd_in[11] PIN w0_wd_in[12] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -123,7 +123,7 @@ MACRO fakeram_21x512_1r1w END END w0_wd_in[12] PIN w0_wd_in[13] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -132,7 +132,7 @@ MACRO fakeram_21x512_1r1w END END w0_wd_in[13] PIN w0_wd_in[14] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -141,7 +141,7 @@ MACRO fakeram_21x512_1r1w END END w0_wd_in[14] PIN w0_wd_in[15] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -150,7 +150,7 @@ MACRO fakeram_21x512_1r1w END END w0_wd_in[15] PIN w0_wd_in[16] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -159,7 +159,7 @@ MACRO fakeram_21x512_1r1w END END w0_wd_in[16] PIN w0_wd_in[17] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -168,7 +168,7 @@ MACRO fakeram_21x512_1r1w END END w0_wd_in[17] PIN w0_wd_in[18] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -177,7 +177,7 @@ MACRO fakeram_21x512_1r1w END END w0_wd_in[18] PIN w0_wd_in[19] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -186,7 +186,7 @@ MACRO fakeram_21x512_1r1w END END w0_wd_in[19] PIN w0_wd_in[20] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT diff --git a/designs/nangate45/eyeriss/sram/lef/fakeram_7x512_1r1w.lef b/designs/nangate45/eyeriss/sram/lef/fakeram_7x512_1r1w.lef index da89d2d8..375c9dfa 100644 --- a/designs/nangate45/eyeriss/sram/lef/fakeram_7x512_1r1w.lef +++ b/designs/nangate45/eyeriss/sram/lef/fakeram_7x512_1r1w.lef @@ -42,7 +42,7 @@ MACRO fakeram_7x512_1r1w END END w0_wd_in[3] PIN w0_wd_in[4] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -51,7 +51,7 @@ MACRO fakeram_7x512_1r1w END END w0_wd_in[4] PIN w0_wd_in[5] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -60,7 +60,7 @@ MACRO fakeram_7x512_1r1w END END w0_wd_in[5] PIN w0_wd_in[6] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT diff --git a/designs/nangate45/eyeriss/sram/lef/fakeram_8x4096_1r1w.lef b/designs/nangate45/eyeriss/sram/lef/fakeram_8x4096_1r1w.lef index e6dabfdc..16836208 100644 --- a/designs/nangate45/eyeriss/sram/lef/fakeram_8x4096_1r1w.lef +++ b/designs/nangate45/eyeriss/sram/lef/fakeram_8x4096_1r1w.lef @@ -42,7 +42,7 @@ MACRO fakeram_8x4096_1r1w END END w0_wd_in[3] PIN w0_wd_in[4] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -51,7 +51,7 @@ MACRO fakeram_8x4096_1r1w END END w0_wd_in[4] PIN w0_wd_in[5] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -60,7 +60,7 @@ MACRO fakeram_8x4096_1r1w END END w0_wd_in[5] PIN w0_wd_in[6] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -69,7 +69,7 @@ MACRO fakeram_8x4096_1r1w END END w0_wd_in[6] PIN w0_wd_in[7] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT diff --git a/designs/nangate45/eyeriss/sram/lib/fakeram_12x128_1rw.lib b/designs/nangate45/eyeriss/sram/lib/fakeram_12x128_1rw.lib index 97c9210e..2140266d 100644 --- a/designs/nangate45/eyeriss/sram/lib/fakeram_12x128_1rw.lib +++ b/designs/nangate45/eyeriss/sram/lib/fakeram_12x128_1rw.lib @@ -2,7 +2,7 @@ library(fakeram_12x128_1rw) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-05-11 03:57:02Z"; + date : "2026-08-13 14:43:17Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; diff --git a/designs/nangate45/eyeriss/sram/lib/fakeram_12x2048_1r1w.lib b/designs/nangate45/eyeriss/sram/lib/fakeram_12x2048_1r1w.lib index dff8406b..fbe701d1 100644 --- a/designs/nangate45/eyeriss/sram/lib/fakeram_12x2048_1r1w.lib +++ b/designs/nangate45/eyeriss/sram/lib/fakeram_12x2048_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_12x2048_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-05-11 03:57:00Z"; + date : "2026-08-13 14:43:14Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; diff --git a/designs/nangate45/eyeriss/sram/lib/fakeram_13x256_1rw.lib b/designs/nangate45/eyeriss/sram/lib/fakeram_13x256_1rw.lib index 58e06de8..d96bd597 100644 --- a/designs/nangate45/eyeriss/sram/lib/fakeram_13x256_1rw.lib +++ b/designs/nangate45/eyeriss/sram/lib/fakeram_13x256_1rw.lib @@ -2,7 +2,7 @@ library(fakeram_13x256_1rw) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-05-11 03:57:02Z"; + date : "2026-08-13 14:43:16Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; diff --git a/designs/nangate45/eyeriss/sram/lib/fakeram_21x32_1r1w.lib b/designs/nangate45/eyeriss/sram/lib/fakeram_21x32_1r1w.lib index bf889fca..3f43a3d3 100644 --- a/designs/nangate45/eyeriss/sram/lib/fakeram_21x32_1r1w.lib +++ b/designs/nangate45/eyeriss/sram/lib/fakeram_21x32_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_21x32_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-05-11 03:57:04Z"; + date : "2026-08-13 14:43:18Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; diff --git a/designs/nangate45/eyeriss/sram/lib/fakeram_21x512_1r1w.lib b/designs/nangate45/eyeriss/sram/lib/fakeram_21x512_1r1w.lib index 53284164..8813be44 100644 --- a/designs/nangate45/eyeriss/sram/lib/fakeram_21x512_1r1w.lib +++ b/designs/nangate45/eyeriss/sram/lib/fakeram_21x512_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_21x512_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-05-11 03:57:01Z"; + date : "2026-08-13 14:43:15Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; diff --git a/designs/nangate45/eyeriss/sram/lib/fakeram_7x512_1r1w.lib b/designs/nangate45/eyeriss/sram/lib/fakeram_7x512_1r1w.lib index 0d2e7d1d..1f9a80d9 100644 --- a/designs/nangate45/eyeriss/sram/lib/fakeram_7x512_1r1w.lib +++ b/designs/nangate45/eyeriss/sram/lib/fakeram_7x512_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_7x512_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-05-11 03:56:59Z"; + date : "2026-08-13 14:43:14Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; diff --git a/designs/nangate45/eyeriss/sram/lib/fakeram_8x4096_1r1w.lib b/designs/nangate45/eyeriss/sram/lib/fakeram_8x4096_1r1w.lib index cf6da938..4611e946 100644 --- a/designs/nangate45/eyeriss/sram/lib/fakeram_8x4096_1r1w.lib +++ b/designs/nangate45/eyeriss/sram/lib/fakeram_8x4096_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_8x4096_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-05-11 03:57:04Z"; + date : "2026-08-13 14:43:18Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; diff --git a/designs/sky130hd/eyeriss/BUILD.bazel b/designs/sky130hd/eyeriss/BUILD.bazel index 4c9bdb0e..4d248ac7 100644 --- a/designs/sky130hd/eyeriss/BUILD.bazel +++ b/designs/sky130hd/eyeriss/BUILD.bazel @@ -12,9 +12,9 @@ filegroup( # Eyeriss v2 sparse-CNN accelerator on sky130hd. Same RTL as asap7/nangate45 # but FakeRAMs regenerated for the 130nm metal stack via -# designs/sky130hd/eyeriss/sram/fakeram_sky130hd.cfg. The sky130hd memories -# are roughly 30x the asap7 area, so floorplan utilization is intentionally -# loose to give the placer room around ~157 macros. +# designs/src/eyeriss/dev/generated/fakeram_sky130hd.cfg. The sky130hd +# memories are still ~30x the asap7 area, so floorplan utilization is +# intentionally loose to give the placer room around ~157 macros. hightide_design( name = "eyeriss", top = "TOP", diff --git a/designs/sky130hd/eyeriss/sram/lef/fakeram_12x128_1rw.lef b/designs/sky130hd/eyeriss/sram/lef/fakeram_12x128_1rw.lef index 502d05d8..f068aee1 100644 --- a/designs/sky130hd/eyeriss/sram/lef/fakeram_12x128_1rw.lef +++ b/designs/sky130hd/eyeriss/sram/lef/fakeram_12x128_1rw.lef @@ -3,7 +3,7 @@ BUSBITCHARS "[]" ; MACRO fakeram_12x128_1rw FOREIGN fakeram_12x128_1rw 0 0 ; SYMMETRY X Y R90 ; - SIZE 164.220 BY 187.680 ; + SIZE 128.800 BY 141.440 ; CLASS BLOCK ; PIN rw0_wd_in[0] DIRECTION INPUT ; @@ -20,7 +20,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 29.090 0.900 29.390 ; + RECT 0.000 22.290 0.900 22.590 ; END END rw0_wd_in[1] PIN rw0_wd_in[2] @@ -29,7 +29,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 54.250 0.900 54.550 ; + RECT 0.000 40.650 0.900 40.950 ; END END rw0_wd_in[2] PIN rw0_wd_in[3] @@ -38,7 +38,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 163.320 3.930 164.220 4.230 ; + RECT 127.900 3.930 128.800 4.230 ; END END rw0_wd_in[3] PIN rw0_wd_in[4] @@ -47,7 +47,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 163.320 29.090 164.220 29.390 ; + RECT 127.900 22.290 128.800 22.590 ; END END rw0_wd_in[4] PIN rw0_wd_in[5] @@ -56,11 +56,11 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 163.320 54.250 164.220 54.550 ; + RECT 127.900 40.650 128.800 40.950 ; END END rw0_wd_in[5] PIN rw0_wd_in[6] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -69,48 +69,48 @@ MACRO fakeram_12x128_1rw END END rw0_wd_in[6] PIN rw0_wd_in[7] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 15.570 0.000 15.710 0.420 ; + RECT 12.810 0.000 12.950 0.420 ; END END rw0_wd_in[7] PIN rw0_wd_in[8] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 28.450 0.000 28.590 0.420 ; + RECT 22.930 0.000 23.070 0.420 ; END END rw0_wd_in[8] PIN rw0_wd_in[9] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 41.330 0.000 41.470 0.420 ; + RECT 33.050 0.000 33.190 0.420 ; END END rw0_wd_in[9] PIN rw0_wd_in[10] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 54.210 0.000 54.350 0.420 ; + RECT 43.170 0.000 43.310 0.420 ; END END rw0_wd_in[10] PIN rw0_wd_in[11] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 67.090 0.000 67.230 0.420 ; + RECT 53.290 0.000 53.430 0.420 ; END END rw0_wd_in[11] PIN rw0_rd_out[0] @@ -119,7 +119,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 79.970 0.000 80.110 0.420 ; + RECT 63.410 0.000 63.550 0.420 ; END END rw0_rd_out[0] PIN rw0_rd_out[1] @@ -128,7 +128,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 92.850 0.000 92.990 0.420 ; + RECT 73.530 0.000 73.670 0.420 ; END END rw0_rd_out[1] PIN rw0_rd_out[2] @@ -137,7 +137,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 105.730 0.000 105.870 0.420 ; + RECT 83.650 0.000 83.790 0.420 ; END END rw0_rd_out[2] PIN rw0_rd_out[3] @@ -146,7 +146,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 118.610 0.000 118.750 0.420 ; + RECT 93.770 0.000 93.910 0.420 ; END END rw0_rd_out[3] PIN rw0_rd_out[4] @@ -155,7 +155,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 131.490 0.000 131.630 0.420 ; + RECT 103.890 0.000 104.030 0.420 ; END END rw0_rd_out[4] PIN rw0_rd_out[5] @@ -164,7 +164,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 144.370 0.000 144.510 0.420 ; + RECT 114.010 0.000 114.150 0.420 ; END END rw0_rd_out[5] PIN rw0_rd_out[6] @@ -173,7 +173,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 2.690 187.260 2.830 187.680 ; + RECT 2.690 141.020 2.830 141.440 ; END END rw0_rd_out[6] PIN rw0_rd_out[7] @@ -182,7 +182,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 20.170 187.260 20.310 187.680 ; + RECT 16.030 141.020 16.170 141.440 ; END END rw0_rd_out[7] PIN rw0_rd_out[8] @@ -191,7 +191,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 37.650 187.260 37.790 187.680 ; + RECT 29.370 141.020 29.510 141.440 ; END END rw0_rd_out[8] PIN rw0_rd_out[9] @@ -200,7 +200,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 55.130 187.260 55.270 187.680 ; + RECT 42.710 141.020 42.850 141.440 ; END END rw0_rd_out[9] PIN rw0_rd_out[10] @@ -209,7 +209,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 72.610 187.260 72.750 187.680 ; + RECT 56.050 141.020 56.190 141.440 ; END END rw0_rd_out[10] PIN rw0_rd_out[11] @@ -218,7 +218,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 90.090 187.260 90.230 187.680 ; + RECT 69.390 141.020 69.530 141.440 ; END END rw0_rd_out[11] PIN rw0_addr_in[0] @@ -227,7 +227,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 79.410 0.900 79.710 ; + RECT 0.000 59.010 0.900 59.310 ; END END rw0_addr_in[0] PIN rw0_addr_in[1] @@ -236,7 +236,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 104.570 0.900 104.870 ; + RECT 0.000 77.370 0.900 77.670 ; END END rw0_addr_in[1] PIN rw0_addr_in[2] @@ -245,7 +245,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 129.730 0.900 130.030 ; + RECT 0.000 95.730 0.900 96.030 ; END END rw0_addr_in[2] PIN rw0_addr_in[3] @@ -254,7 +254,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 154.890 0.900 155.190 ; + RECT 0.000 114.090 0.900 114.390 ; END END rw0_addr_in[3] PIN rw0_addr_in[4] @@ -263,7 +263,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 163.320 79.410 164.220 79.710 ; + RECT 127.900 59.010 128.800 59.310 ; END END rw0_addr_in[4] PIN rw0_addr_in[5] @@ -272,7 +272,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 163.320 104.570 164.220 104.870 ; + RECT 127.900 77.370 128.800 77.670 ; END END rw0_addr_in[5] PIN rw0_addr_in[6] @@ -281,7 +281,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 163.320 129.730 164.220 130.030 ; + RECT 127.900 95.730 128.800 96.030 ; END END rw0_addr_in[6] PIN rw0_we_in @@ -290,7 +290,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 107.570 187.260 107.710 187.680 ; + RECT 82.730 141.020 82.870 141.440 ; END END rw0_we_in PIN rw0_ce_in @@ -299,7 +299,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 125.050 187.260 125.190 187.680 ; + RECT 96.070 141.020 96.210 141.440 ; END END rw0_ce_in PIN rw0_clk @@ -308,7 +308,7 @@ MACRO fakeram_12x128_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 142.530 187.260 142.670 187.680 ; + RECT 109.410 141.020 109.550 141.440 ; END END rw0_clk PIN VSS @@ -316,21 +316,18 @@ MACRO fakeram_12x128_1rw USE GROUND ; PORT LAYER met4 ; - RECT 2.160 4.080 3.360 183.600 ; - RECT 13.040 4.080 14.240 183.600 ; - RECT 23.920 4.080 25.120 183.600 ; - RECT 34.800 4.080 36.000 183.600 ; - RECT 45.680 4.080 46.880 183.600 ; - RECT 56.560 4.080 57.760 183.600 ; - RECT 67.440 4.080 68.640 183.600 ; - RECT 78.320 4.080 79.520 183.600 ; - RECT 89.200 4.080 90.400 183.600 ; - RECT 100.080 4.080 101.280 183.600 ; - RECT 110.960 4.080 112.160 183.600 ; - RECT 121.840 4.080 123.040 183.600 ; - RECT 132.720 4.080 133.920 183.600 ; - RECT 143.600 4.080 144.800 183.600 ; - RECT 154.480 4.080 155.680 183.600 ; + RECT 2.160 4.080 3.360 137.360 ; + RECT 13.040 4.080 14.240 137.360 ; + RECT 23.920 4.080 25.120 137.360 ; + RECT 34.800 4.080 36.000 137.360 ; + RECT 45.680 4.080 46.880 137.360 ; + RECT 56.560 4.080 57.760 137.360 ; + RECT 67.440 4.080 68.640 137.360 ; + RECT 78.320 4.080 79.520 137.360 ; + RECT 89.200 4.080 90.400 137.360 ; + RECT 100.080 4.080 101.280 137.360 ; + RECT 110.960 4.080 112.160 137.360 ; + RECT 121.840 4.080 123.040 137.360 ; END END VSS PIN VDD @@ -338,32 +335,29 @@ MACRO fakeram_12x128_1rw USE POWER ; PORT LAYER met4 ; - RECT 2.160 4.080 3.360 183.600 ; - RECT 13.040 4.080 14.240 183.600 ; - RECT 23.920 4.080 25.120 183.600 ; - RECT 34.800 4.080 36.000 183.600 ; - RECT 45.680 4.080 46.880 183.600 ; - RECT 56.560 4.080 57.760 183.600 ; - RECT 67.440 4.080 68.640 183.600 ; - RECT 78.320 4.080 79.520 183.600 ; - RECT 89.200 4.080 90.400 183.600 ; - RECT 100.080 4.080 101.280 183.600 ; - RECT 110.960 4.080 112.160 183.600 ; - RECT 121.840 4.080 123.040 183.600 ; - RECT 132.720 4.080 133.920 183.600 ; - RECT 143.600 4.080 144.800 183.600 ; - RECT 154.480 4.080 155.680 183.600 ; + RECT 2.160 4.080 3.360 137.360 ; + RECT 13.040 4.080 14.240 137.360 ; + RECT 23.920 4.080 25.120 137.360 ; + RECT 34.800 4.080 36.000 137.360 ; + RECT 45.680 4.080 46.880 137.360 ; + RECT 56.560 4.080 57.760 137.360 ; + RECT 67.440 4.080 68.640 137.360 ; + RECT 78.320 4.080 79.520 137.360 ; + RECT 89.200 4.080 90.400 137.360 ; + RECT 100.080 4.080 101.280 137.360 ; + RECT 110.960 4.080 112.160 137.360 ; + RECT 121.840 4.080 123.040 137.360 ; END END VDD OBS LAYER met1 ; - RECT 0 0 164.220 187.680 ; + RECT 0 0 128.800 141.440 ; LAYER met2 ; - RECT 0 0 164.220 187.680 ; + RECT 0 0 128.800 141.440 ; LAYER met3 ; - RECT 0 0 164.220 187.680 ; + RECT 0 0 128.800 141.440 ; LAYER met4 ; - RECT 0 0 164.220 187.680 ; + RECT 0 0 128.800 141.440 ; END END fakeram_12x128_1rw diff --git a/designs/sky130hd/eyeriss/sram/lef/fakeram_12x2048_1r1w.lef b/designs/sky130hd/eyeriss/sram/lef/fakeram_12x2048_1r1w.lef index 7abb9988..ecf712ef 100644 --- a/designs/sky130hd/eyeriss/sram/lef/fakeram_12x2048_1r1w.lef +++ b/designs/sky130hd/eyeriss/sram/lef/fakeram_12x2048_1r1w.lef @@ -3,7 +3,7 @@ BUSBITCHARS "[]" ; MACRO fakeram_12x2048_1r1w FOREIGN fakeram_12x2048_1r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 382.260 BY 288.320 ; + SIZE 398.360 BY 217.600 ; CLASS BLOCK ; PIN w0_wd_in[0] DIRECTION INPUT ; @@ -20,7 +20,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 29.090 0.900 29.390 ; + RECT 0.000 22.290 0.900 22.590 ; END END w0_wd_in[1] PIN w0_wd_in[2] @@ -29,7 +29,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 54.250 0.900 54.550 ; + RECT 0.000 40.650 0.900 40.950 ; END END w0_wd_in[2] PIN w0_wd_in[3] @@ -38,7 +38,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 381.360 3.930 382.260 4.230 ; + RECT 397.460 3.930 398.360 4.230 ; END END w0_wd_in[3] PIN w0_wd_in[4] @@ -47,7 +47,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 381.360 29.090 382.260 29.390 ; + RECT 397.460 22.290 398.360 22.590 ; END END w0_wd_in[4] PIN w0_wd_in[5] @@ -56,11 +56,11 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 381.360 54.250 382.260 54.550 ; + RECT 397.460 40.650 398.360 40.950 ; END END w0_wd_in[5] PIN w0_wd_in[6] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -69,48 +69,48 @@ MACRO fakeram_12x2048_1r1w END END w0_wd_in[6] PIN w0_wd_in[7] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 33.970 0.000 34.110 0.420 ; + RECT 35.350 0.000 35.490 0.420 ; END END w0_wd_in[7] PIN w0_wd_in[8] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 65.250 0.000 65.390 0.420 ; + RECT 68.010 0.000 68.150 0.420 ; END END w0_wd_in[8] PIN w0_wd_in[9] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 96.530 0.000 96.670 0.420 ; + RECT 100.670 0.000 100.810 0.420 ; END END w0_wd_in[9] PIN w0_wd_in[10] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 127.810 0.000 127.950 0.420 ; + RECT 133.330 0.000 133.470 0.420 ; END END w0_wd_in[10] PIN w0_wd_in[11] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 159.090 0.000 159.230 0.420 ; + RECT 165.990 0.000 166.130 0.420 ; END END w0_wd_in[11] PIN r0_rd_out[0] @@ -119,7 +119,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 190.370 0.000 190.510 0.420 ; + RECT 198.650 0.000 198.790 0.420 ; END END r0_rd_out[0] PIN r0_rd_out[1] @@ -128,7 +128,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 221.650 0.000 221.790 0.420 ; + RECT 231.310 0.000 231.450 0.420 ; END END r0_rd_out[1] PIN r0_rd_out[2] @@ -137,7 +137,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 252.930 0.000 253.070 0.420 ; + RECT 263.970 0.000 264.110 0.420 ; END END r0_rd_out[2] PIN r0_rd_out[3] @@ -146,7 +146,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 284.210 0.000 284.350 0.420 ; + RECT 296.630 0.000 296.770 0.420 ; END END r0_rd_out[3] PIN r0_rd_out[4] @@ -155,7 +155,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 315.490 0.000 315.630 0.420 ; + RECT 329.290 0.000 329.430 0.420 ; END END r0_rd_out[4] PIN r0_rd_out[5] @@ -164,7 +164,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 346.770 0.000 346.910 0.420 ; + RECT 361.950 0.000 362.090 0.420 ; END END r0_rd_out[5] PIN r0_rd_out[6] @@ -173,7 +173,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 2.690 287.900 2.830 288.320 ; + RECT 2.690 217.180 2.830 217.600 ; END END r0_rd_out[6] PIN r0_rd_out[7] @@ -182,7 +182,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 36.730 287.900 36.870 288.320 ; + RECT 38.110 217.180 38.250 217.600 ; END END r0_rd_out[7] PIN r0_rd_out[8] @@ -191,7 +191,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 70.770 287.900 70.910 288.320 ; + RECT 73.530 217.180 73.670 217.600 ; END END r0_rd_out[8] PIN r0_rd_out[9] @@ -200,7 +200,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 104.810 287.900 104.950 288.320 ; + RECT 108.950 217.180 109.090 217.600 ; END END r0_rd_out[9] PIN r0_rd_out[10] @@ -209,7 +209,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 138.850 287.900 138.990 288.320 ; + RECT 144.370 217.180 144.510 217.600 ; END END r0_rd_out[10] PIN r0_rd_out[11] @@ -218,7 +218,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 172.890 287.900 173.030 288.320 ; + RECT 179.790 217.180 179.930 217.600 ; END END r0_rd_out[11] PIN w0_addr_in[0] @@ -227,7 +227,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 79.410 0.900 79.710 ; + RECT 0.000 59.010 0.900 59.310 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -236,7 +236,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 104.570 0.900 104.870 ; + RECT 0.000 77.370 0.900 77.670 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -245,7 +245,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 129.730 0.900 130.030 ; + RECT 0.000 95.730 0.900 96.030 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -254,7 +254,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 154.890 0.900 155.190 ; + RECT 0.000 114.090 0.900 114.390 ; END END w0_addr_in[3] PIN w0_addr_in[4] @@ -263,7 +263,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 381.360 79.410 382.260 79.710 ; + RECT 397.460 59.010 398.360 59.310 ; END END w0_addr_in[4] PIN w0_addr_in[5] @@ -272,7 +272,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 381.360 104.570 382.260 104.870 ; + RECT 397.460 77.370 398.360 77.670 ; END END w0_addr_in[5] PIN w0_addr_in[6] @@ -281,7 +281,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 381.360 129.730 382.260 130.030 ; + RECT 397.460 95.730 398.360 96.030 ; END END w0_addr_in[6] PIN w0_addr_in[7] @@ -290,7 +290,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 381.360 154.890 382.260 155.190 ; + RECT 397.460 114.090 398.360 114.390 ; END END w0_addr_in[7] PIN r0_addr_in[0] @@ -299,7 +299,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 180.050 0.900 180.350 ; + RECT 0.000 132.450 0.900 132.750 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -308,7 +308,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 205.210 0.900 205.510 ; + RECT 0.000 150.810 0.900 151.110 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -317,7 +317,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 230.370 0.900 230.670 ; + RECT 0.000 169.170 0.900 169.470 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -326,7 +326,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 255.530 0.900 255.830 ; + RECT 0.000 187.530 0.900 187.830 ; END END r0_addr_in[3] PIN r0_addr_in[4] @@ -335,7 +335,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 381.360 180.050 382.260 180.350 ; + RECT 397.460 132.450 398.360 132.750 ; END END r0_addr_in[4] PIN r0_addr_in[5] @@ -344,7 +344,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 381.360 205.210 382.260 205.510 ; + RECT 397.460 150.810 398.360 151.110 ; END END r0_addr_in[5] PIN r0_addr_in[6] @@ -353,7 +353,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 381.360 230.370 382.260 230.670 ; + RECT 397.460 169.170 398.360 169.470 ; END END r0_addr_in[6] PIN r0_addr_in[7] @@ -362,7 +362,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 381.360 255.530 382.260 255.830 ; + RECT 397.460 187.530 398.360 187.830 ; END END r0_addr_in[7] PIN w0_we_in @@ -371,7 +371,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 206.930 287.900 207.070 288.320 ; + RECT 215.210 217.180 215.350 217.600 ; END END w0_we_in PIN w0_ce_in @@ -380,7 +380,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 240.970 287.900 241.110 288.320 ; + RECT 250.630 217.180 250.770 217.600 ; END END w0_ce_in PIN w0_clk @@ -389,7 +389,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 275.010 287.900 275.150 288.320 ; + RECT 286.050 217.180 286.190 217.600 ; END END w0_clk PIN r0_ce_in @@ -398,7 +398,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 309.050 287.900 309.190 288.320 ; + RECT 321.470 217.180 321.610 217.600 ; END END r0_ce_in PIN r0_clk @@ -407,7 +407,7 @@ MACRO fakeram_12x2048_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 343.090 287.900 343.230 288.320 ; + RECT 356.890 217.180 357.030 217.600 ; END END r0_clk PIN VSS @@ -415,41 +415,43 @@ MACRO fakeram_12x2048_1r1w USE GROUND ; PORT LAYER met4 ; - RECT 2.160 4.080 3.360 284.240 ; - RECT 13.040 4.080 14.240 284.240 ; - RECT 23.920 4.080 25.120 284.240 ; - RECT 34.800 4.080 36.000 284.240 ; - RECT 45.680 4.080 46.880 284.240 ; - RECT 56.560 4.080 57.760 284.240 ; - RECT 67.440 4.080 68.640 284.240 ; - RECT 78.320 4.080 79.520 284.240 ; - RECT 89.200 4.080 90.400 284.240 ; - RECT 100.080 4.080 101.280 284.240 ; - RECT 110.960 4.080 112.160 284.240 ; - RECT 121.840 4.080 123.040 284.240 ; - RECT 132.720 4.080 133.920 284.240 ; - RECT 143.600 4.080 144.800 284.240 ; - RECT 154.480 4.080 155.680 284.240 ; - RECT 165.360 4.080 166.560 284.240 ; - RECT 176.240 4.080 177.440 284.240 ; - RECT 187.120 4.080 188.320 284.240 ; - RECT 198.000 4.080 199.200 284.240 ; - RECT 208.880 4.080 210.080 284.240 ; - RECT 219.760 4.080 220.960 284.240 ; - RECT 230.640 4.080 231.840 284.240 ; - RECT 241.520 4.080 242.720 284.240 ; - RECT 252.400 4.080 253.600 284.240 ; - RECT 263.280 4.080 264.480 284.240 ; - RECT 274.160 4.080 275.360 284.240 ; - RECT 285.040 4.080 286.240 284.240 ; - RECT 295.920 4.080 297.120 284.240 ; - RECT 306.800 4.080 308.000 284.240 ; - RECT 317.680 4.080 318.880 284.240 ; - RECT 328.560 4.080 329.760 284.240 ; - RECT 339.440 4.080 340.640 284.240 ; - RECT 350.320 4.080 351.520 284.240 ; - RECT 361.200 4.080 362.400 284.240 ; - RECT 372.080 4.080 373.280 284.240 ; + RECT 2.160 4.080 3.360 213.520 ; + RECT 13.040 4.080 14.240 213.520 ; + RECT 23.920 4.080 25.120 213.520 ; + RECT 34.800 4.080 36.000 213.520 ; + RECT 45.680 4.080 46.880 213.520 ; + RECT 56.560 4.080 57.760 213.520 ; + RECT 67.440 4.080 68.640 213.520 ; + RECT 78.320 4.080 79.520 213.520 ; + RECT 89.200 4.080 90.400 213.520 ; + RECT 100.080 4.080 101.280 213.520 ; + RECT 110.960 4.080 112.160 213.520 ; + RECT 121.840 4.080 123.040 213.520 ; + RECT 132.720 4.080 133.920 213.520 ; + RECT 143.600 4.080 144.800 213.520 ; + RECT 154.480 4.080 155.680 213.520 ; + RECT 165.360 4.080 166.560 213.520 ; + RECT 176.240 4.080 177.440 213.520 ; + RECT 187.120 4.080 188.320 213.520 ; + RECT 198.000 4.080 199.200 213.520 ; + RECT 208.880 4.080 210.080 213.520 ; + RECT 219.760 4.080 220.960 213.520 ; + RECT 230.640 4.080 231.840 213.520 ; + RECT 241.520 4.080 242.720 213.520 ; + RECT 252.400 4.080 253.600 213.520 ; + RECT 263.280 4.080 264.480 213.520 ; + RECT 274.160 4.080 275.360 213.520 ; + RECT 285.040 4.080 286.240 213.520 ; + RECT 295.920 4.080 297.120 213.520 ; + RECT 306.800 4.080 308.000 213.520 ; + RECT 317.680 4.080 318.880 213.520 ; + RECT 328.560 4.080 329.760 213.520 ; + RECT 339.440 4.080 340.640 213.520 ; + RECT 350.320 4.080 351.520 213.520 ; + RECT 361.200 4.080 362.400 213.520 ; + RECT 372.080 4.080 373.280 213.520 ; + RECT 382.960 4.080 384.160 213.520 ; + RECT 393.840 4.080 395.040 213.520 ; END END VSS PIN VDD @@ -457,52 +459,54 @@ MACRO fakeram_12x2048_1r1w USE POWER ; PORT LAYER met4 ; - RECT 2.160 4.080 3.360 284.240 ; - RECT 13.040 4.080 14.240 284.240 ; - RECT 23.920 4.080 25.120 284.240 ; - RECT 34.800 4.080 36.000 284.240 ; - RECT 45.680 4.080 46.880 284.240 ; - RECT 56.560 4.080 57.760 284.240 ; - RECT 67.440 4.080 68.640 284.240 ; - RECT 78.320 4.080 79.520 284.240 ; - RECT 89.200 4.080 90.400 284.240 ; - RECT 100.080 4.080 101.280 284.240 ; - RECT 110.960 4.080 112.160 284.240 ; - RECT 121.840 4.080 123.040 284.240 ; - RECT 132.720 4.080 133.920 284.240 ; - RECT 143.600 4.080 144.800 284.240 ; - RECT 154.480 4.080 155.680 284.240 ; - RECT 165.360 4.080 166.560 284.240 ; - RECT 176.240 4.080 177.440 284.240 ; - RECT 187.120 4.080 188.320 284.240 ; - RECT 198.000 4.080 199.200 284.240 ; - RECT 208.880 4.080 210.080 284.240 ; - RECT 219.760 4.080 220.960 284.240 ; - RECT 230.640 4.080 231.840 284.240 ; - RECT 241.520 4.080 242.720 284.240 ; - RECT 252.400 4.080 253.600 284.240 ; - RECT 263.280 4.080 264.480 284.240 ; - RECT 274.160 4.080 275.360 284.240 ; - RECT 285.040 4.080 286.240 284.240 ; - RECT 295.920 4.080 297.120 284.240 ; - RECT 306.800 4.080 308.000 284.240 ; - RECT 317.680 4.080 318.880 284.240 ; - RECT 328.560 4.080 329.760 284.240 ; - RECT 339.440 4.080 340.640 284.240 ; - RECT 350.320 4.080 351.520 284.240 ; - RECT 361.200 4.080 362.400 284.240 ; - RECT 372.080 4.080 373.280 284.240 ; + RECT 2.160 4.080 3.360 213.520 ; + RECT 13.040 4.080 14.240 213.520 ; + RECT 23.920 4.080 25.120 213.520 ; + RECT 34.800 4.080 36.000 213.520 ; + RECT 45.680 4.080 46.880 213.520 ; + RECT 56.560 4.080 57.760 213.520 ; + RECT 67.440 4.080 68.640 213.520 ; + RECT 78.320 4.080 79.520 213.520 ; + RECT 89.200 4.080 90.400 213.520 ; + RECT 100.080 4.080 101.280 213.520 ; + RECT 110.960 4.080 112.160 213.520 ; + RECT 121.840 4.080 123.040 213.520 ; + RECT 132.720 4.080 133.920 213.520 ; + RECT 143.600 4.080 144.800 213.520 ; + RECT 154.480 4.080 155.680 213.520 ; + RECT 165.360 4.080 166.560 213.520 ; + RECT 176.240 4.080 177.440 213.520 ; + RECT 187.120 4.080 188.320 213.520 ; + RECT 198.000 4.080 199.200 213.520 ; + RECT 208.880 4.080 210.080 213.520 ; + RECT 219.760 4.080 220.960 213.520 ; + RECT 230.640 4.080 231.840 213.520 ; + RECT 241.520 4.080 242.720 213.520 ; + RECT 252.400 4.080 253.600 213.520 ; + RECT 263.280 4.080 264.480 213.520 ; + RECT 274.160 4.080 275.360 213.520 ; + RECT 285.040 4.080 286.240 213.520 ; + RECT 295.920 4.080 297.120 213.520 ; + RECT 306.800 4.080 308.000 213.520 ; + RECT 317.680 4.080 318.880 213.520 ; + RECT 328.560 4.080 329.760 213.520 ; + RECT 339.440 4.080 340.640 213.520 ; + RECT 350.320 4.080 351.520 213.520 ; + RECT 361.200 4.080 362.400 213.520 ; + RECT 372.080 4.080 373.280 213.520 ; + RECT 382.960 4.080 384.160 213.520 ; + RECT 393.840 4.080 395.040 213.520 ; END END VDD OBS LAYER met1 ; - RECT 0 0 382.260 288.320 ; + RECT 0 0 398.360 217.600 ; LAYER met2 ; - RECT 0 0 382.260 288.320 ; + RECT 0 0 398.360 217.600 ; LAYER met3 ; - RECT 0 0 382.260 288.320 ; + RECT 0 0 398.360 217.600 ; LAYER met4 ; - RECT 0 0 382.260 288.320 ; + RECT 0 0 398.360 217.600 ; END END fakeram_12x2048_1r1w diff --git a/designs/sky130hd/eyeriss/sram/lef/fakeram_13x256_1rw.lef b/designs/sky130hd/eyeriss/sram/lef/fakeram_13x256_1rw.lef index 9256f7e4..d985548d 100644 --- a/designs/sky130hd/eyeriss/sram/lef/fakeram_13x256_1rw.lef +++ b/designs/sky130hd/eyeriss/sram/lef/fakeram_13x256_1rw.lef @@ -3,7 +3,7 @@ BUSBITCHARS "[]" ; MACRO fakeram_13x256_1rw FOREIGN fakeram_13x256_1rw 0 0 ; SYMMETRY X Y R90 ; - SIZE 285.660 BY 187.680 ; + SIZE 278.300 BY 141.440 ; CLASS BLOCK ; PIN rw0_wd_in[0] DIRECTION INPUT ; @@ -20,7 +20,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 25.690 0.900 25.990 ; + RECT 0.000 20.250 0.900 20.550 ; END END rw0_wd_in[1] PIN rw0_wd_in[2] @@ -29,7 +29,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 47.450 0.900 47.750 ; + RECT 0.000 36.570 0.900 36.870 ; END END rw0_wd_in[2] PIN rw0_wd_in[3] @@ -38,7 +38,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 69.210 0.900 69.510 ; + RECT 0.000 52.890 0.900 53.190 ; END END rw0_wd_in[3] PIN rw0_wd_in[4] @@ -47,7 +47,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 284.760 3.930 285.660 4.230 ; + RECT 277.400 3.930 278.300 4.230 ; END END rw0_wd_in[4] PIN rw0_wd_in[5] @@ -56,7 +56,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 284.760 25.690 285.660 25.990 ; + RECT 277.400 20.250 278.300 20.550 ; END END rw0_wd_in[5] PIN rw0_wd_in[6] @@ -65,11 +65,11 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 284.760 47.450 285.660 47.750 ; + RECT 277.400 36.570 278.300 36.870 ; END END rw0_wd_in[6] PIN rw0_wd_in[7] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -78,48 +78,48 @@ MACRO fakeram_13x256_1rw END END rw0_wd_in[7] PIN rw0_wd_in[8] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 22.470 0.000 22.610 0.420 ; + RECT 22.010 0.000 22.150 0.420 ; END END rw0_wd_in[8] PIN rw0_wd_in[9] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 42.250 0.000 42.390 0.420 ; + RECT 41.330 0.000 41.470 0.420 ; END END rw0_wd_in[9] PIN rw0_wd_in[10] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 62.030 0.000 62.170 0.420 ; + RECT 60.650 0.000 60.790 0.420 ; END END rw0_wd_in[10] PIN rw0_wd_in[11] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 81.810 0.000 81.950 0.420 ; + RECT 79.970 0.000 80.110 0.420 ; END END rw0_wd_in[11] PIN rw0_wd_in[12] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 101.590 0.000 101.730 0.420 ; + RECT 99.290 0.000 99.430 0.420 ; END END rw0_wd_in[12] PIN rw0_rd_out[0] @@ -128,7 +128,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 121.370 0.000 121.510 0.420 ; + RECT 118.610 0.000 118.750 0.420 ; END END rw0_rd_out[0] PIN rw0_rd_out[1] @@ -137,7 +137,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 141.150 0.000 141.290 0.420 ; + RECT 137.930 0.000 138.070 0.420 ; END END rw0_rd_out[1] PIN rw0_rd_out[2] @@ -146,7 +146,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 160.930 0.000 161.070 0.420 ; + RECT 157.250 0.000 157.390 0.420 ; END END rw0_rd_out[2] PIN rw0_rd_out[3] @@ -155,7 +155,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 180.710 0.000 180.850 0.420 ; + RECT 176.570 0.000 176.710 0.420 ; END END rw0_rd_out[3] PIN rw0_rd_out[4] @@ -164,7 +164,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 200.490 0.000 200.630 0.420 ; + RECT 195.890 0.000 196.030 0.420 ; END END rw0_rd_out[4] PIN rw0_rd_out[5] @@ -173,7 +173,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 220.270 0.000 220.410 0.420 ; + RECT 215.210 0.000 215.350 0.420 ; END END rw0_rd_out[5] PIN rw0_rd_out[6] @@ -182,7 +182,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 240.050 0.000 240.190 0.420 ; + RECT 234.530 0.000 234.670 0.420 ; END END rw0_rd_out[6] PIN rw0_rd_out[7] @@ -191,7 +191,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 2.690 187.260 2.830 187.680 ; + RECT 2.690 141.020 2.830 141.440 ; END END rw0_rd_out[7] PIN rw0_rd_out[8] @@ -200,7 +200,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 30.290 187.260 30.430 187.680 ; + RECT 29.830 141.020 29.970 141.440 ; END END rw0_rd_out[8] PIN rw0_rd_out[9] @@ -209,7 +209,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 57.890 187.260 58.030 187.680 ; + RECT 56.970 141.020 57.110 141.440 ; END END rw0_rd_out[9] PIN rw0_rd_out[10] @@ -218,7 +218,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 85.490 187.260 85.630 187.680 ; + RECT 84.110 141.020 84.250 141.440 ; END END rw0_rd_out[10] PIN rw0_rd_out[11] @@ -227,7 +227,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 113.090 187.260 113.230 187.680 ; + RECT 111.250 141.020 111.390 141.440 ; END END rw0_rd_out[11] PIN rw0_rd_out[12] @@ -236,7 +236,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 140.690 187.260 140.830 187.680 ; + RECT 138.390 141.020 138.530 141.440 ; END END rw0_rd_out[12] PIN rw0_addr_in[0] @@ -245,7 +245,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 90.970 0.900 91.270 ; + RECT 0.000 69.210 0.900 69.510 ; END END rw0_addr_in[0] PIN rw0_addr_in[1] @@ -254,7 +254,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 112.730 0.900 113.030 ; + RECT 0.000 85.530 0.900 85.830 ; END END rw0_addr_in[1] PIN rw0_addr_in[2] @@ -263,7 +263,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 134.490 0.900 134.790 ; + RECT 0.000 101.850 0.900 102.150 ; END END rw0_addr_in[2] PIN rw0_addr_in[3] @@ -272,7 +272,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 156.250 0.900 156.550 ; + RECT 0.000 118.170 0.900 118.470 ; END END rw0_addr_in[3] PIN rw0_addr_in[4] @@ -281,7 +281,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 284.760 69.210 285.660 69.510 ; + RECT 277.400 52.890 278.300 53.190 ; END END rw0_addr_in[4] PIN rw0_addr_in[5] @@ -290,7 +290,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 284.760 90.970 285.660 91.270 ; + RECT 277.400 69.210 278.300 69.510 ; END END rw0_addr_in[5] PIN rw0_addr_in[6] @@ -299,7 +299,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 284.760 112.730 285.660 113.030 ; + RECT 277.400 85.530 278.300 85.830 ; END END rw0_addr_in[6] PIN rw0_addr_in[7] @@ -308,7 +308,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 284.760 134.490 285.660 134.790 ; + RECT 277.400 101.850 278.300 102.150 ; END END rw0_addr_in[7] PIN rw0_we_in @@ -317,7 +317,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 168.290 187.260 168.430 187.680 ; + RECT 165.530 141.020 165.670 141.440 ; END END rw0_we_in PIN rw0_ce_in @@ -326,7 +326,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 195.890 187.260 196.030 187.680 ; + RECT 192.670 141.020 192.810 141.440 ; END END rw0_ce_in PIN rw0_clk @@ -335,7 +335,7 @@ MACRO fakeram_13x256_1rw SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 223.490 187.260 223.630 187.680 ; + RECT 219.810 141.020 219.950 141.440 ; END END rw0_clk PIN VSS @@ -343,32 +343,32 @@ MACRO fakeram_13x256_1rw USE GROUND ; PORT LAYER met4 ; - RECT 2.160 4.080 3.360 183.600 ; - RECT 13.040 4.080 14.240 183.600 ; - RECT 23.920 4.080 25.120 183.600 ; - RECT 34.800 4.080 36.000 183.600 ; - RECT 45.680 4.080 46.880 183.600 ; - RECT 56.560 4.080 57.760 183.600 ; - RECT 67.440 4.080 68.640 183.600 ; - RECT 78.320 4.080 79.520 183.600 ; - RECT 89.200 4.080 90.400 183.600 ; - RECT 100.080 4.080 101.280 183.600 ; - RECT 110.960 4.080 112.160 183.600 ; - RECT 121.840 4.080 123.040 183.600 ; - RECT 132.720 4.080 133.920 183.600 ; - RECT 143.600 4.080 144.800 183.600 ; - RECT 154.480 4.080 155.680 183.600 ; - RECT 165.360 4.080 166.560 183.600 ; - RECT 176.240 4.080 177.440 183.600 ; - RECT 187.120 4.080 188.320 183.600 ; - RECT 198.000 4.080 199.200 183.600 ; - RECT 208.880 4.080 210.080 183.600 ; - RECT 219.760 4.080 220.960 183.600 ; - RECT 230.640 4.080 231.840 183.600 ; - RECT 241.520 4.080 242.720 183.600 ; - RECT 252.400 4.080 253.600 183.600 ; - RECT 263.280 4.080 264.480 183.600 ; - RECT 274.160 4.080 275.360 183.600 ; + RECT 2.160 4.080 3.360 137.360 ; + RECT 13.040 4.080 14.240 137.360 ; + RECT 23.920 4.080 25.120 137.360 ; + RECT 34.800 4.080 36.000 137.360 ; + RECT 45.680 4.080 46.880 137.360 ; + RECT 56.560 4.080 57.760 137.360 ; + RECT 67.440 4.080 68.640 137.360 ; + RECT 78.320 4.080 79.520 137.360 ; + RECT 89.200 4.080 90.400 137.360 ; + RECT 100.080 4.080 101.280 137.360 ; + RECT 110.960 4.080 112.160 137.360 ; + RECT 121.840 4.080 123.040 137.360 ; + RECT 132.720 4.080 133.920 137.360 ; + RECT 143.600 4.080 144.800 137.360 ; + RECT 154.480 4.080 155.680 137.360 ; + RECT 165.360 4.080 166.560 137.360 ; + RECT 176.240 4.080 177.440 137.360 ; + RECT 187.120 4.080 188.320 137.360 ; + RECT 198.000 4.080 199.200 137.360 ; + RECT 208.880 4.080 210.080 137.360 ; + RECT 219.760 4.080 220.960 137.360 ; + RECT 230.640 4.080 231.840 137.360 ; + RECT 241.520 4.080 242.720 137.360 ; + RECT 252.400 4.080 253.600 137.360 ; + RECT 263.280 4.080 264.480 137.360 ; + RECT 274.160 4.080 275.360 137.360 ; END END VSS PIN VDD @@ -376,43 +376,43 @@ MACRO fakeram_13x256_1rw USE POWER ; PORT LAYER met4 ; - RECT 2.160 4.080 3.360 183.600 ; - RECT 13.040 4.080 14.240 183.600 ; - RECT 23.920 4.080 25.120 183.600 ; - RECT 34.800 4.080 36.000 183.600 ; - RECT 45.680 4.080 46.880 183.600 ; - RECT 56.560 4.080 57.760 183.600 ; - RECT 67.440 4.080 68.640 183.600 ; - RECT 78.320 4.080 79.520 183.600 ; - RECT 89.200 4.080 90.400 183.600 ; - RECT 100.080 4.080 101.280 183.600 ; - RECT 110.960 4.080 112.160 183.600 ; - RECT 121.840 4.080 123.040 183.600 ; - RECT 132.720 4.080 133.920 183.600 ; - RECT 143.600 4.080 144.800 183.600 ; - RECT 154.480 4.080 155.680 183.600 ; - RECT 165.360 4.080 166.560 183.600 ; - RECT 176.240 4.080 177.440 183.600 ; - RECT 187.120 4.080 188.320 183.600 ; - RECT 198.000 4.080 199.200 183.600 ; - RECT 208.880 4.080 210.080 183.600 ; - RECT 219.760 4.080 220.960 183.600 ; - RECT 230.640 4.080 231.840 183.600 ; - RECT 241.520 4.080 242.720 183.600 ; - RECT 252.400 4.080 253.600 183.600 ; - RECT 263.280 4.080 264.480 183.600 ; - RECT 274.160 4.080 275.360 183.600 ; + RECT 2.160 4.080 3.360 137.360 ; + RECT 13.040 4.080 14.240 137.360 ; + RECT 23.920 4.080 25.120 137.360 ; + RECT 34.800 4.080 36.000 137.360 ; + RECT 45.680 4.080 46.880 137.360 ; + RECT 56.560 4.080 57.760 137.360 ; + RECT 67.440 4.080 68.640 137.360 ; + RECT 78.320 4.080 79.520 137.360 ; + RECT 89.200 4.080 90.400 137.360 ; + RECT 100.080 4.080 101.280 137.360 ; + RECT 110.960 4.080 112.160 137.360 ; + RECT 121.840 4.080 123.040 137.360 ; + RECT 132.720 4.080 133.920 137.360 ; + RECT 143.600 4.080 144.800 137.360 ; + RECT 154.480 4.080 155.680 137.360 ; + RECT 165.360 4.080 166.560 137.360 ; + RECT 176.240 4.080 177.440 137.360 ; + RECT 187.120 4.080 188.320 137.360 ; + RECT 198.000 4.080 199.200 137.360 ; + RECT 208.880 4.080 210.080 137.360 ; + RECT 219.760 4.080 220.960 137.360 ; + RECT 230.640 4.080 231.840 137.360 ; + RECT 241.520 4.080 242.720 137.360 ; + RECT 252.400 4.080 253.600 137.360 ; + RECT 263.280 4.080 264.480 137.360 ; + RECT 274.160 4.080 275.360 137.360 ; END END VDD OBS LAYER met1 ; - RECT 0 0 285.660 187.680 ; + RECT 0 0 278.300 141.440 ; LAYER met2 ; - RECT 0 0 285.660 187.680 ; + RECT 0 0 278.300 141.440 ; LAYER met3 ; - RECT 0 0 285.660 187.680 ; + RECT 0 0 278.300 141.440 ; LAYER met4 ; - RECT 0 0 285.660 187.680 ; + RECT 0 0 278.300 141.440 ; END END fakeram_13x256_1rw diff --git a/designs/sky130hd/eyeriss/sram/lef/fakeram_21x32_1r1w.lef b/designs/sky130hd/eyeriss/sram/lef/fakeram_21x32_1r1w.lef index f8f117d4..42c87292 100644 --- a/designs/sky130hd/eyeriss/sram/lef/fakeram_21x32_1r1w.lef +++ b/designs/sky130hd/eyeriss/sram/lef/fakeram_21x32_1r1w.lef @@ -3,7 +3,7 @@ BUSBITCHARS "[]" ; MACRO fakeram_21x32_1r1w FOREIGN fakeram_21x32_1r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 153.640 BY 146.880 ; + SIZE 174.340 BY 108.800 ; CLASS BLOCK ; PIN w0_wd_in[0] DIRECTION INPUT ; @@ -20,7 +20,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 16.170 0.900 16.470 ; + RECT 0.000 12.770 0.900 13.070 ; END END w0_wd_in[1] PIN w0_wd_in[2] @@ -29,7 +29,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 28.410 0.900 28.710 ; + RECT 0.000 21.610 0.900 21.910 ; END END w0_wd_in[2] PIN w0_wd_in[3] @@ -38,7 +38,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 40.650 0.900 40.950 ; + RECT 0.000 30.450 0.900 30.750 ; END END w0_wd_in[3] PIN w0_wd_in[4] @@ -47,7 +47,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 52.890 0.900 53.190 ; + RECT 0.000 39.290 0.900 39.590 ; END END w0_wd_in[4] PIN w0_wd_in[5] @@ -56,7 +56,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 65.130 0.900 65.430 ; + RECT 0.000 48.130 0.900 48.430 ; END END w0_wd_in[5] PIN w0_wd_in[6] @@ -65,7 +65,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 152.740 3.930 153.640 4.230 ; + RECT 173.440 3.930 174.340 4.230 ; END END w0_wd_in[6] PIN w0_wd_in[7] @@ -74,7 +74,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 152.740 16.170 153.640 16.470 ; + RECT 173.440 12.770 174.340 13.070 ; END END w0_wd_in[7] PIN w0_wd_in[8] @@ -83,7 +83,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 152.740 28.410 153.640 28.710 ; + RECT 173.440 21.610 174.340 21.910 ; END END w0_wd_in[8] PIN w0_wd_in[9] @@ -92,7 +92,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 152.740 40.650 153.640 40.950 ; + RECT 173.440 30.450 174.340 30.750 ; END END w0_wd_in[9] PIN w0_wd_in[10] @@ -101,11 +101,11 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 152.740 52.890 153.640 53.190 ; + RECT 173.440 39.290 174.340 39.590 ; END END w0_wd_in[10] PIN w0_wd_in[11] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -114,84 +114,84 @@ MACRO fakeram_21x32_1r1w END END w0_wd_in[11] PIN w0_wd_in[12] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 9.130 0.000 9.270 0.420 ; + RECT 10.050 0.000 10.190 0.420 ; END END w0_wd_in[12] PIN w0_wd_in[13] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 15.570 0.000 15.710 0.420 ; + RECT 17.410 0.000 17.550 0.420 ; END END w0_wd_in[13] PIN w0_wd_in[14] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 22.010 0.000 22.150 0.420 ; + RECT 24.770 0.000 24.910 0.420 ; END END w0_wd_in[14] PIN w0_wd_in[15] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 28.450 0.000 28.590 0.420 ; + RECT 32.130 0.000 32.270 0.420 ; END END w0_wd_in[15] PIN w0_wd_in[16] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 34.890 0.000 35.030 0.420 ; + RECT 39.490 0.000 39.630 0.420 ; END END w0_wd_in[16] PIN w0_wd_in[17] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 41.330 0.000 41.470 0.420 ; + RECT 46.850 0.000 46.990 0.420 ; END END w0_wd_in[17] PIN w0_wd_in[18] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 47.770 0.000 47.910 0.420 ; + RECT 54.210 0.000 54.350 0.420 ; END END w0_wd_in[18] PIN w0_wd_in[19] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 54.210 0.000 54.350 0.420 ; + RECT 61.570 0.000 61.710 0.420 ; END END w0_wd_in[19] PIN w0_wd_in[20] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 60.650 0.000 60.790 0.420 ; + RECT 68.930 0.000 69.070 0.420 ; END END w0_wd_in[20] PIN r0_rd_out[0] @@ -200,7 +200,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 67.090 0.000 67.230 0.420 ; + RECT 76.290 0.000 76.430 0.420 ; END END r0_rd_out[0] PIN r0_rd_out[1] @@ -209,7 +209,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 73.530 0.000 73.670 0.420 ; + RECT 83.650 0.000 83.790 0.420 ; END END r0_rd_out[1] PIN r0_rd_out[2] @@ -218,7 +218,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 79.970 0.000 80.110 0.420 ; + RECT 91.010 0.000 91.150 0.420 ; END END r0_rd_out[2] PIN r0_rd_out[3] @@ -227,7 +227,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 86.410 0.000 86.550 0.420 ; + RECT 98.370 0.000 98.510 0.420 ; END END r0_rd_out[3] PIN r0_rd_out[4] @@ -236,7 +236,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 92.850 0.000 92.990 0.420 ; + RECT 105.730 0.000 105.870 0.420 ; END END r0_rd_out[4] PIN r0_rd_out[5] @@ -245,7 +245,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 99.290 0.000 99.430 0.420 ; + RECT 113.090 0.000 113.230 0.420 ; END END r0_rd_out[5] PIN r0_rd_out[6] @@ -254,7 +254,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 105.730 0.000 105.870 0.420 ; + RECT 120.450 0.000 120.590 0.420 ; END END r0_rd_out[6] PIN r0_rd_out[7] @@ -263,7 +263,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 112.170 0.000 112.310 0.420 ; + RECT 127.810 0.000 127.950 0.420 ; END END r0_rd_out[7] PIN r0_rd_out[8] @@ -272,7 +272,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 118.610 0.000 118.750 0.420 ; + RECT 135.170 0.000 135.310 0.420 ; END END r0_rd_out[8] PIN r0_rd_out[9] @@ -281,7 +281,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 125.050 0.000 125.190 0.420 ; + RECT 142.530 0.000 142.670 0.420 ; END END r0_rd_out[9] PIN r0_rd_out[10] @@ -290,7 +290,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 131.490 0.000 131.630 0.420 ; + RECT 149.890 0.000 150.030 0.420 ; END END r0_rd_out[10] PIN r0_rd_out[11] @@ -299,7 +299,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 2.690 146.460 2.830 146.880 ; + RECT 2.690 108.380 2.830 108.800 ; END END r0_rd_out[11] PIN r0_rd_out[12] @@ -308,7 +308,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 11.890 146.460 12.030 146.880 ; + RECT 12.810 108.380 12.950 108.800 ; END END r0_rd_out[12] PIN r0_rd_out[13] @@ -317,7 +317,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 21.090 146.460 21.230 146.880 ; + RECT 22.930 108.380 23.070 108.800 ; END END r0_rd_out[13] PIN r0_rd_out[14] @@ -326,7 +326,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 30.290 146.460 30.430 146.880 ; + RECT 33.050 108.380 33.190 108.800 ; END END r0_rd_out[14] PIN r0_rd_out[15] @@ -335,7 +335,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 39.490 146.460 39.630 146.880 ; + RECT 43.170 108.380 43.310 108.800 ; END END r0_rd_out[15] PIN r0_rd_out[16] @@ -344,7 +344,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 48.690 146.460 48.830 146.880 ; + RECT 53.290 108.380 53.430 108.800 ; END END r0_rd_out[16] PIN r0_rd_out[17] @@ -353,7 +353,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 57.890 146.460 58.030 146.880 ; + RECT 63.410 108.380 63.550 108.800 ; END END r0_rd_out[17] PIN r0_rd_out[18] @@ -362,7 +362,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 67.090 146.460 67.230 146.880 ; + RECT 73.530 108.380 73.670 108.800 ; END END r0_rd_out[18] PIN r0_rd_out[19] @@ -371,7 +371,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 76.290 146.460 76.430 146.880 ; + RECT 83.650 108.380 83.790 108.800 ; END END r0_rd_out[19] PIN r0_rd_out[20] @@ -380,7 +380,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 85.490 146.460 85.630 146.880 ; + RECT 93.770 108.380 93.910 108.800 ; END END r0_rd_out[20] PIN w0_addr_in[0] @@ -389,7 +389,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 77.370 0.900 77.670 ; + RECT 0.000 56.970 0.900 57.270 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -398,7 +398,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 89.610 0.900 89.910 ; + RECT 0.000 65.810 0.900 66.110 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -407,7 +407,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 101.850 0.900 102.150 ; + RECT 0.000 74.650 0.900 74.950 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -416,7 +416,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 152.740 65.130 153.640 65.430 ; + RECT 173.440 48.130 174.340 48.430 ; END END w0_addr_in[3] PIN w0_addr_in[4] @@ -425,7 +425,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 152.740 77.370 153.640 77.670 ; + RECT 173.440 56.970 174.340 57.270 ; END END w0_addr_in[4] PIN r0_addr_in[0] @@ -434,7 +434,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 114.090 0.900 114.390 ; + RECT 0.000 83.490 0.900 83.790 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -443,7 +443,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 126.330 0.900 126.630 ; + RECT 0.000 92.330 0.900 92.630 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -452,7 +452,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 138.570 0.900 138.870 ; + RECT 0.000 101.170 0.900 101.470 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -461,7 +461,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 152.740 89.610 153.640 89.910 ; + RECT 173.440 65.810 174.340 66.110 ; END END r0_addr_in[3] PIN r0_addr_in[4] @@ -470,7 +470,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 152.740 101.850 153.640 102.150 ; + RECT 173.440 74.650 174.340 74.950 ; END END r0_addr_in[4] PIN w0_we_in @@ -479,7 +479,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 94.690 146.460 94.830 146.880 ; + RECT 103.890 108.380 104.030 108.800 ; END END w0_we_in PIN w0_ce_in @@ -488,7 +488,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 103.890 146.460 104.030 146.880 ; + RECT 114.010 108.380 114.150 108.800 ; END END w0_ce_in PIN w0_clk @@ -497,7 +497,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 113.090 146.460 113.230 146.880 ; + RECT 124.130 108.380 124.270 108.800 ; END END w0_clk PIN r0_ce_in @@ -506,7 +506,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 122.290 146.460 122.430 146.880 ; + RECT 134.250 108.380 134.390 108.800 ; END END r0_ce_in PIN r0_clk @@ -515,7 +515,7 @@ MACRO fakeram_21x32_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 131.490 146.460 131.630 146.880 ; + RECT 144.370 108.380 144.510 108.800 ; END END r0_clk PIN VSS @@ -523,20 +523,22 @@ MACRO fakeram_21x32_1r1w USE GROUND ; PORT LAYER met4 ; - RECT 2.160 4.080 3.360 142.800 ; - RECT 13.040 4.080 14.240 142.800 ; - RECT 23.920 4.080 25.120 142.800 ; - RECT 34.800 4.080 36.000 142.800 ; - RECT 45.680 4.080 46.880 142.800 ; - RECT 56.560 4.080 57.760 142.800 ; - RECT 67.440 4.080 68.640 142.800 ; - RECT 78.320 4.080 79.520 142.800 ; - RECT 89.200 4.080 90.400 142.800 ; - RECT 100.080 4.080 101.280 142.800 ; - RECT 110.960 4.080 112.160 142.800 ; - RECT 121.840 4.080 123.040 142.800 ; - RECT 132.720 4.080 133.920 142.800 ; - RECT 143.600 4.080 144.800 142.800 ; + RECT 2.160 4.080 3.360 104.720 ; + RECT 13.040 4.080 14.240 104.720 ; + RECT 23.920 4.080 25.120 104.720 ; + RECT 34.800 4.080 36.000 104.720 ; + RECT 45.680 4.080 46.880 104.720 ; + RECT 56.560 4.080 57.760 104.720 ; + RECT 67.440 4.080 68.640 104.720 ; + RECT 78.320 4.080 79.520 104.720 ; + RECT 89.200 4.080 90.400 104.720 ; + RECT 100.080 4.080 101.280 104.720 ; + RECT 110.960 4.080 112.160 104.720 ; + RECT 121.840 4.080 123.040 104.720 ; + RECT 132.720 4.080 133.920 104.720 ; + RECT 143.600 4.080 144.800 104.720 ; + RECT 154.480 4.080 155.680 104.720 ; + RECT 165.360 4.080 166.560 104.720 ; END END VSS PIN VDD @@ -544,31 +546,33 @@ MACRO fakeram_21x32_1r1w USE POWER ; PORT LAYER met4 ; - RECT 2.160 4.080 3.360 142.800 ; - RECT 13.040 4.080 14.240 142.800 ; - RECT 23.920 4.080 25.120 142.800 ; - RECT 34.800 4.080 36.000 142.800 ; - RECT 45.680 4.080 46.880 142.800 ; - RECT 56.560 4.080 57.760 142.800 ; - RECT 67.440 4.080 68.640 142.800 ; - RECT 78.320 4.080 79.520 142.800 ; - RECT 89.200 4.080 90.400 142.800 ; - RECT 100.080 4.080 101.280 142.800 ; - RECT 110.960 4.080 112.160 142.800 ; - RECT 121.840 4.080 123.040 142.800 ; - RECT 132.720 4.080 133.920 142.800 ; - RECT 143.600 4.080 144.800 142.800 ; + RECT 2.160 4.080 3.360 104.720 ; + RECT 13.040 4.080 14.240 104.720 ; + RECT 23.920 4.080 25.120 104.720 ; + RECT 34.800 4.080 36.000 104.720 ; + RECT 45.680 4.080 46.880 104.720 ; + RECT 56.560 4.080 57.760 104.720 ; + RECT 67.440 4.080 68.640 104.720 ; + RECT 78.320 4.080 79.520 104.720 ; + RECT 89.200 4.080 90.400 104.720 ; + RECT 100.080 4.080 101.280 104.720 ; + RECT 110.960 4.080 112.160 104.720 ; + RECT 121.840 4.080 123.040 104.720 ; + RECT 132.720 4.080 133.920 104.720 ; + RECT 143.600 4.080 144.800 104.720 ; + RECT 154.480 4.080 155.680 104.720 ; + RECT 165.360 4.080 166.560 104.720 ; END END VDD OBS LAYER met1 ; - RECT 0 0 153.640 146.880 ; + RECT 0 0 174.340 108.800 ; LAYER met2 ; - RECT 0 0 153.640 146.880 ; + RECT 0 0 174.340 108.800 ; LAYER met3 ; - RECT 0 0 153.640 146.880 ; + RECT 0 0 174.340 108.800 ; LAYER met4 ; - RECT 0 0 153.640 146.880 ; + RECT 0 0 174.340 108.800 ; END END fakeram_21x32_1r1w diff --git a/designs/sky130hd/eyeriss/sram/lef/fakeram_21x512_1r1w.lef b/designs/sky130hd/eyeriss/sram/lef/fakeram_21x512_1r1w.lef index dae002dd..e73bb32c 100644 --- a/designs/sky130hd/eyeriss/sram/lef/fakeram_21x512_1r1w.lef +++ b/designs/sky130hd/eyeriss/sram/lef/fakeram_21x512_1r1w.lef @@ -3,7 +3,7 @@ BUSBITCHARS "[]" ; MACRO fakeram_21x512_1r1w FOREIGN fakeram_21x512_1r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 224.020 BY 519.520 ; + SIZE 348.680 BY 217.600 ; CLASS BLOCK ; PIN w0_wd_in[0] DIRECTION INPUT ; @@ -20,7 +20,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 42.690 0.900 42.990 ; + RECT 0.000 19.570 0.900 19.870 ; END END w0_wd_in[1] PIN w0_wd_in[2] @@ -29,7 +29,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 81.450 0.900 81.750 ; + RECT 0.000 35.210 0.900 35.510 ; END END w0_wd_in[2] PIN w0_wd_in[3] @@ -38,7 +38,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 120.210 0.900 120.510 ; + RECT 0.000 50.850 0.900 51.150 ; END END w0_wd_in[3] PIN w0_wd_in[4] @@ -47,7 +47,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 158.970 0.900 159.270 ; + RECT 0.000 66.490 0.900 66.790 ; END END w0_wd_in[4] PIN w0_wd_in[5] @@ -56,7 +56,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 197.730 0.900 198.030 ; + RECT 0.000 82.130 0.900 82.430 ; END END w0_wd_in[5] PIN w0_wd_in[6] @@ -65,7 +65,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 223.120 3.930 224.020 4.230 ; + RECT 347.780 3.930 348.680 4.230 ; END END w0_wd_in[6] PIN w0_wd_in[7] @@ -74,7 +74,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 223.120 42.690 224.020 42.990 ; + RECT 347.780 19.570 348.680 19.870 ; END END w0_wd_in[7] PIN w0_wd_in[8] @@ -83,7 +83,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 223.120 81.450 224.020 81.750 ; + RECT 347.780 35.210 348.680 35.510 ; END END w0_wd_in[8] PIN w0_wd_in[9] @@ -92,7 +92,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 223.120 120.210 224.020 120.510 ; + RECT 347.780 50.850 348.680 51.150 ; END END w0_wd_in[9] PIN w0_wd_in[10] @@ -101,11 +101,11 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 223.120 158.970 224.020 159.270 ; + RECT 347.780 66.490 348.680 66.790 ; END END w0_wd_in[10] PIN w0_wd_in[11] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -114,84 +114,84 @@ MACRO fakeram_21x512_1r1w END END w0_wd_in[11] PIN w0_wd_in[12] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 12.350 0.000 12.490 0.420 ; + RECT 17.870 0.000 18.010 0.420 ; END END w0_wd_in[12] PIN w0_wd_in[13] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 22.010 0.000 22.150 0.420 ; + RECT 33.050 0.000 33.190 0.420 ; END END w0_wd_in[13] PIN w0_wd_in[14] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 31.670 0.000 31.810 0.420 ; + RECT 48.230 0.000 48.370 0.420 ; END END w0_wd_in[14] PIN w0_wd_in[15] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 41.330 0.000 41.470 0.420 ; + RECT 63.410 0.000 63.550 0.420 ; END END w0_wd_in[15] PIN w0_wd_in[16] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 50.990 0.000 51.130 0.420 ; + RECT 78.590 0.000 78.730 0.420 ; END END w0_wd_in[16] PIN w0_wd_in[17] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 60.650 0.000 60.790 0.420 ; + RECT 93.770 0.000 93.910 0.420 ; END END w0_wd_in[17] PIN w0_wd_in[18] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 70.310 0.000 70.450 0.420 ; + RECT 108.950 0.000 109.090 0.420 ; END END w0_wd_in[18] PIN w0_wd_in[19] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 79.970 0.000 80.110 0.420 ; + RECT 124.130 0.000 124.270 0.420 ; END END w0_wd_in[19] PIN w0_wd_in[20] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 89.630 0.000 89.770 0.420 ; + RECT 139.310 0.000 139.450 0.420 ; END END w0_wd_in[20] PIN r0_rd_out[0] @@ -200,7 +200,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 99.290 0.000 99.430 0.420 ; + RECT 154.490 0.000 154.630 0.420 ; END END r0_rd_out[0] PIN r0_rd_out[1] @@ -209,7 +209,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 108.950 0.000 109.090 0.420 ; + RECT 169.670 0.000 169.810 0.420 ; END END r0_rd_out[1] PIN r0_rd_out[2] @@ -218,7 +218,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 118.610 0.000 118.750 0.420 ; + RECT 184.850 0.000 184.990 0.420 ; END END r0_rd_out[2] PIN r0_rd_out[3] @@ -227,7 +227,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 128.270 0.000 128.410 0.420 ; + RECT 200.030 0.000 200.170 0.420 ; END END r0_rd_out[3] PIN r0_rd_out[4] @@ -236,7 +236,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 137.930 0.000 138.070 0.420 ; + RECT 215.210 0.000 215.350 0.420 ; END END r0_rd_out[4] PIN r0_rd_out[5] @@ -245,7 +245,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 147.590 0.000 147.730 0.420 ; + RECT 230.390 0.000 230.530 0.420 ; END END r0_rd_out[5] PIN r0_rd_out[6] @@ -254,7 +254,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 157.250 0.000 157.390 0.420 ; + RECT 245.570 0.000 245.710 0.420 ; END END r0_rd_out[6] PIN r0_rd_out[7] @@ -263,7 +263,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 166.910 0.000 167.050 0.420 ; + RECT 260.750 0.000 260.890 0.420 ; END END r0_rd_out[7] PIN r0_rd_out[8] @@ -272,7 +272,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 176.570 0.000 176.710 0.420 ; + RECT 275.930 0.000 276.070 0.420 ; END END r0_rd_out[8] PIN r0_rd_out[9] @@ -281,7 +281,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 186.230 0.000 186.370 0.420 ; + RECT 291.110 0.000 291.250 0.420 ; END END r0_rd_out[9] PIN r0_rd_out[10] @@ -290,7 +290,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 195.890 0.000 196.030 0.420 ; + RECT 306.290 0.000 306.430 0.420 ; END END r0_rd_out[10] PIN r0_rd_out[11] @@ -299,7 +299,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 2.690 519.100 2.830 519.520 ; + RECT 2.690 217.180 2.830 217.600 ; END END r0_rd_out[11] PIN r0_rd_out[12] @@ -308,7 +308,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 16.030 519.100 16.170 519.520 ; + RECT 23.850 217.180 23.990 217.600 ; END END r0_rd_out[12] PIN r0_rd_out[13] @@ -317,7 +317,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 29.370 519.100 29.510 519.520 ; + RECT 45.010 217.180 45.150 217.600 ; END END r0_rd_out[13] PIN r0_rd_out[14] @@ -326,7 +326,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 42.710 519.100 42.850 519.520 ; + RECT 66.170 217.180 66.310 217.600 ; END END r0_rd_out[14] PIN r0_rd_out[15] @@ -335,7 +335,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 56.050 519.100 56.190 519.520 ; + RECT 87.330 217.180 87.470 217.600 ; END END r0_rd_out[15] PIN r0_rd_out[16] @@ -344,7 +344,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 69.390 519.100 69.530 519.520 ; + RECT 108.490 217.180 108.630 217.600 ; END END r0_rd_out[16] PIN r0_rd_out[17] @@ -353,7 +353,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 82.730 519.100 82.870 519.520 ; + RECT 129.650 217.180 129.790 217.600 ; END END r0_rd_out[17] PIN r0_rd_out[18] @@ -362,7 +362,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 96.070 519.100 96.210 519.520 ; + RECT 150.810 217.180 150.950 217.600 ; END END r0_rd_out[18] PIN r0_rd_out[19] @@ -371,7 +371,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 109.410 519.100 109.550 519.520 ; + RECT 171.970 217.180 172.110 217.600 ; END END r0_rd_out[19] PIN r0_rd_out[20] @@ -380,7 +380,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 122.750 519.100 122.890 519.520 ; + RECT 193.130 217.180 193.270 217.600 ; END END r0_rd_out[20] PIN w0_addr_in[0] @@ -389,7 +389,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 236.490 0.900 236.790 ; + RECT 0.000 97.770 0.900 98.070 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -398,7 +398,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 275.250 0.900 275.550 ; + RECT 0.000 113.410 0.900 113.710 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -407,7 +407,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 314.010 0.900 314.310 ; + RECT 0.000 129.050 0.900 129.350 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -416,7 +416,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 352.770 0.900 353.070 ; + RECT 0.000 144.690 0.900 144.990 ; END END w0_addr_in[3] PIN w0_addr_in[4] @@ -425,7 +425,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 223.120 197.730 224.020 198.030 ; + RECT 347.780 82.130 348.680 82.430 ; END END w0_addr_in[4] PIN w0_addr_in[5] @@ -434,7 +434,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 223.120 236.490 224.020 236.790 ; + RECT 347.780 97.770 348.680 98.070 ; END END w0_addr_in[5] PIN w0_addr_in[6] @@ -443,7 +443,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 223.120 275.250 224.020 275.550 ; + RECT 347.780 113.410 348.680 113.710 ; END END w0_addr_in[6] PIN r0_addr_in[0] @@ -452,7 +452,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 391.530 0.900 391.830 ; + RECT 0.000 160.330 0.900 160.630 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -461,7 +461,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 430.290 0.900 430.590 ; + RECT 0.000 175.970 0.900 176.270 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -470,7 +470,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 469.050 0.900 469.350 ; + RECT 0.000 191.610 0.900 191.910 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -479,7 +479,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 507.810 0.900 508.110 ; + RECT 0.000 207.250 0.900 207.550 ; END END r0_addr_in[3] PIN r0_addr_in[4] @@ -488,7 +488,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 223.120 314.010 224.020 314.310 ; + RECT 347.780 129.050 348.680 129.350 ; END END r0_addr_in[4] PIN r0_addr_in[5] @@ -497,7 +497,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 223.120 352.770 224.020 353.070 ; + RECT 347.780 144.690 348.680 144.990 ; END END r0_addr_in[5] PIN r0_addr_in[6] @@ -506,7 +506,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 223.120 391.530 224.020 391.830 ; + RECT 347.780 160.330 348.680 160.630 ; END END r0_addr_in[6] PIN w0_we_in @@ -515,7 +515,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 136.090 519.100 136.230 519.520 ; + RECT 214.290 217.180 214.430 217.600 ; END END w0_we_in PIN w0_ce_in @@ -524,7 +524,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 149.430 519.100 149.570 519.520 ; + RECT 235.450 217.180 235.590 217.600 ; END END w0_ce_in PIN w0_clk @@ -533,7 +533,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 162.770 519.100 162.910 519.520 ; + RECT 256.610 217.180 256.750 217.600 ; END END w0_clk PIN r0_ce_in @@ -542,7 +542,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 176.110 519.100 176.250 519.520 ; + RECT 277.770 217.180 277.910 217.600 ; END END r0_ce_in PIN r0_clk @@ -551,7 +551,7 @@ MACRO fakeram_21x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 189.450 519.100 189.590 519.520 ; + RECT 298.930 217.180 299.070 217.600 ; END END r0_clk PIN VSS @@ -559,27 +559,38 @@ MACRO fakeram_21x512_1r1w USE GROUND ; PORT LAYER met4 ; - RECT 2.160 4.080 3.360 515.440 ; - RECT 13.040 4.080 14.240 515.440 ; - RECT 23.920 4.080 25.120 515.440 ; - RECT 34.800 4.080 36.000 515.440 ; - RECT 45.680 4.080 46.880 515.440 ; - RECT 56.560 4.080 57.760 515.440 ; - RECT 67.440 4.080 68.640 515.440 ; - RECT 78.320 4.080 79.520 515.440 ; - RECT 89.200 4.080 90.400 515.440 ; - RECT 100.080 4.080 101.280 515.440 ; - RECT 110.960 4.080 112.160 515.440 ; - RECT 121.840 4.080 123.040 515.440 ; - RECT 132.720 4.080 133.920 515.440 ; - RECT 143.600 4.080 144.800 515.440 ; - RECT 154.480 4.080 155.680 515.440 ; - RECT 165.360 4.080 166.560 515.440 ; - RECT 176.240 4.080 177.440 515.440 ; - RECT 187.120 4.080 188.320 515.440 ; - RECT 198.000 4.080 199.200 515.440 ; - RECT 208.880 4.080 210.080 515.440 ; - RECT 219.760 4.080 220.960 515.440 ; + RECT 2.160 4.080 3.360 213.520 ; + RECT 13.040 4.080 14.240 213.520 ; + RECT 23.920 4.080 25.120 213.520 ; + RECT 34.800 4.080 36.000 213.520 ; + RECT 45.680 4.080 46.880 213.520 ; + RECT 56.560 4.080 57.760 213.520 ; + RECT 67.440 4.080 68.640 213.520 ; + RECT 78.320 4.080 79.520 213.520 ; + RECT 89.200 4.080 90.400 213.520 ; + RECT 100.080 4.080 101.280 213.520 ; + RECT 110.960 4.080 112.160 213.520 ; + RECT 121.840 4.080 123.040 213.520 ; + RECT 132.720 4.080 133.920 213.520 ; + RECT 143.600 4.080 144.800 213.520 ; + RECT 154.480 4.080 155.680 213.520 ; + RECT 165.360 4.080 166.560 213.520 ; + RECT 176.240 4.080 177.440 213.520 ; + RECT 187.120 4.080 188.320 213.520 ; + RECT 198.000 4.080 199.200 213.520 ; + RECT 208.880 4.080 210.080 213.520 ; + RECT 219.760 4.080 220.960 213.520 ; + RECT 230.640 4.080 231.840 213.520 ; + RECT 241.520 4.080 242.720 213.520 ; + RECT 252.400 4.080 253.600 213.520 ; + RECT 263.280 4.080 264.480 213.520 ; + RECT 274.160 4.080 275.360 213.520 ; + RECT 285.040 4.080 286.240 213.520 ; + RECT 295.920 4.080 297.120 213.520 ; + RECT 306.800 4.080 308.000 213.520 ; + RECT 317.680 4.080 318.880 213.520 ; + RECT 328.560 4.080 329.760 213.520 ; + RECT 339.440 4.080 340.640 213.520 ; END END VSS PIN VDD @@ -587,38 +598,49 @@ MACRO fakeram_21x512_1r1w USE POWER ; PORT LAYER met4 ; - RECT 2.160 4.080 3.360 515.440 ; - RECT 13.040 4.080 14.240 515.440 ; - RECT 23.920 4.080 25.120 515.440 ; - RECT 34.800 4.080 36.000 515.440 ; - RECT 45.680 4.080 46.880 515.440 ; - RECT 56.560 4.080 57.760 515.440 ; - RECT 67.440 4.080 68.640 515.440 ; - RECT 78.320 4.080 79.520 515.440 ; - RECT 89.200 4.080 90.400 515.440 ; - RECT 100.080 4.080 101.280 515.440 ; - RECT 110.960 4.080 112.160 515.440 ; - RECT 121.840 4.080 123.040 515.440 ; - RECT 132.720 4.080 133.920 515.440 ; - RECT 143.600 4.080 144.800 515.440 ; - RECT 154.480 4.080 155.680 515.440 ; - RECT 165.360 4.080 166.560 515.440 ; - RECT 176.240 4.080 177.440 515.440 ; - RECT 187.120 4.080 188.320 515.440 ; - RECT 198.000 4.080 199.200 515.440 ; - RECT 208.880 4.080 210.080 515.440 ; - RECT 219.760 4.080 220.960 515.440 ; + RECT 2.160 4.080 3.360 213.520 ; + RECT 13.040 4.080 14.240 213.520 ; + RECT 23.920 4.080 25.120 213.520 ; + RECT 34.800 4.080 36.000 213.520 ; + RECT 45.680 4.080 46.880 213.520 ; + RECT 56.560 4.080 57.760 213.520 ; + RECT 67.440 4.080 68.640 213.520 ; + RECT 78.320 4.080 79.520 213.520 ; + RECT 89.200 4.080 90.400 213.520 ; + RECT 100.080 4.080 101.280 213.520 ; + RECT 110.960 4.080 112.160 213.520 ; + RECT 121.840 4.080 123.040 213.520 ; + RECT 132.720 4.080 133.920 213.520 ; + RECT 143.600 4.080 144.800 213.520 ; + RECT 154.480 4.080 155.680 213.520 ; + RECT 165.360 4.080 166.560 213.520 ; + RECT 176.240 4.080 177.440 213.520 ; + RECT 187.120 4.080 188.320 213.520 ; + RECT 198.000 4.080 199.200 213.520 ; + RECT 208.880 4.080 210.080 213.520 ; + RECT 219.760 4.080 220.960 213.520 ; + RECT 230.640 4.080 231.840 213.520 ; + RECT 241.520 4.080 242.720 213.520 ; + RECT 252.400 4.080 253.600 213.520 ; + RECT 263.280 4.080 264.480 213.520 ; + RECT 274.160 4.080 275.360 213.520 ; + RECT 285.040 4.080 286.240 213.520 ; + RECT 295.920 4.080 297.120 213.520 ; + RECT 306.800 4.080 308.000 213.520 ; + RECT 317.680 4.080 318.880 213.520 ; + RECT 328.560 4.080 329.760 213.520 ; + RECT 339.440 4.080 340.640 213.520 ; END END VDD OBS LAYER met1 ; - RECT 0 0 224.020 519.520 ; + RECT 0 0 348.680 217.600 ; LAYER met2 ; - RECT 0 0 224.020 519.520 ; + RECT 0 0 348.680 217.600 ; LAYER met3 ; - RECT 0 0 224.020 519.520 ; + RECT 0 0 348.680 217.600 ; LAYER met4 ; - RECT 0 0 224.020 519.520 ; + RECT 0 0 348.680 217.600 ; END END fakeram_21x512_1r1w diff --git a/designs/sky130hd/eyeriss/sram/lef/fakeram_7x512_1r1w.lef b/designs/sky130hd/eyeriss/sram/lef/fakeram_7x512_1r1w.lef index fa10c11d..9b465fac 100644 --- a/designs/sky130hd/eyeriss/sram/lef/fakeram_7x512_1r1w.lef +++ b/designs/sky130hd/eyeriss/sram/lef/fakeram_7x512_1r1w.lef @@ -3,7 +3,7 @@ BUSBITCHARS "[]" ; MACRO fakeram_7x512_1r1w FOREIGN fakeram_7x512_1r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 229.540 BY 484.160 ; + SIZE 232.300 BY 217.600 ; CLASS BLOCK ; PIN w0_wd_in[0] DIRECTION INPUT ; @@ -20,7 +20,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 50.850 0.900 51.150 ; + RECT 0.000 24.330 0.900 24.630 ; END END w0_wd_in[1] PIN w0_wd_in[2] @@ -29,7 +29,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 228.640 3.930 229.540 4.230 ; + RECT 231.400 3.930 232.300 4.230 ; END END w0_wd_in[2] PIN w0_wd_in[3] @@ -38,11 +38,11 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 228.640 50.850 229.540 51.150 ; + RECT 231.400 24.330 232.300 24.630 ; END END w0_wd_in[3] PIN w0_wd_in[4] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -51,21 +51,21 @@ MACRO fakeram_7x512_1r1w END END w0_wd_in[4] PIN w0_wd_in[5] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 30.290 0.000 30.430 0.420 ; + RECT 30.750 0.000 30.890 0.420 ; END END w0_wd_in[5] PIN w0_wd_in[6] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 57.890 0.000 58.030 0.420 ; + RECT 58.810 0.000 58.950 0.420 ; END END w0_wd_in[6] PIN r0_rd_out[0] @@ -74,7 +74,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 85.490 0.000 85.630 0.420 ; + RECT 86.870 0.000 87.010 0.420 ; END END r0_rd_out[0] PIN r0_rd_out[1] @@ -83,7 +83,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 113.090 0.000 113.230 0.420 ; + RECT 114.930 0.000 115.070 0.420 ; END END r0_rd_out[1] PIN r0_rd_out[2] @@ -92,7 +92,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 140.690 0.000 140.830 0.420 ; + RECT 142.990 0.000 143.130 0.420 ; END END r0_rd_out[2] PIN r0_rd_out[3] @@ -101,7 +101,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 168.290 0.000 168.430 0.420 ; + RECT 171.050 0.000 171.190 0.420 ; END END r0_rd_out[3] PIN r0_rd_out[4] @@ -110,7 +110,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 2.690 483.740 2.830 484.160 ; + RECT 2.690 217.180 2.830 217.600 ; END END r0_rd_out[4] PIN r0_rd_out[5] @@ -119,7 +119,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 27.070 483.740 27.210 484.160 ; + RECT 27.530 217.180 27.670 217.600 ; END END r0_rd_out[5] PIN r0_rd_out[6] @@ -128,7 +128,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 51.450 483.740 51.590 484.160 ; + RECT 52.370 217.180 52.510 217.600 ; END END r0_rd_out[6] PIN w0_addr_in[0] @@ -137,7 +137,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 97.770 0.900 98.070 ; + RECT 0.000 44.730 0.900 45.030 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -146,7 +146,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 144.690 0.900 144.990 ; + RECT 0.000 65.130 0.900 65.430 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -155,7 +155,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 191.610 0.900 191.910 ; + RECT 0.000 85.530 0.900 85.830 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -164,7 +164,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 238.530 0.900 238.830 ; + RECT 0.000 105.930 0.900 106.230 ; END END w0_addr_in[3] PIN w0_addr_in[4] @@ -173,7 +173,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 228.640 97.770 229.540 98.070 ; + RECT 231.400 44.730 232.300 45.030 ; END END w0_addr_in[4] PIN w0_addr_in[5] @@ -182,7 +182,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 228.640 144.690 229.540 144.990 ; + RECT 231.400 65.130 232.300 65.430 ; END END w0_addr_in[5] PIN w0_addr_in[6] @@ -191,7 +191,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 228.640 191.610 229.540 191.910 ; + RECT 231.400 85.530 232.300 85.830 ; END END w0_addr_in[6] PIN w0_addr_in[7] @@ -200,7 +200,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 228.640 238.530 229.540 238.830 ; + RECT 231.400 105.930 232.300 106.230 ; END END w0_addr_in[7] PIN r0_addr_in[0] @@ -209,7 +209,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 285.450 0.900 285.750 ; + RECT 0.000 126.330 0.900 126.630 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -218,7 +218,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 332.370 0.900 332.670 ; + RECT 0.000 146.730 0.900 147.030 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -227,7 +227,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 379.290 0.900 379.590 ; + RECT 0.000 167.130 0.900 167.430 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -236,7 +236,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 426.210 0.900 426.510 ; + RECT 0.000 187.530 0.900 187.830 ; END END r0_addr_in[3] PIN r0_addr_in[4] @@ -245,7 +245,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 228.640 285.450 229.540 285.750 ; + RECT 231.400 126.330 232.300 126.630 ; END END r0_addr_in[4] PIN r0_addr_in[5] @@ -254,7 +254,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 228.640 332.370 229.540 332.670 ; + RECT 231.400 146.730 232.300 147.030 ; END END r0_addr_in[5] PIN r0_addr_in[6] @@ -263,7 +263,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 228.640 379.290 229.540 379.590 ; + RECT 231.400 167.130 232.300 167.430 ; END END r0_addr_in[6] PIN r0_addr_in[7] @@ -272,7 +272,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 228.640 426.210 229.540 426.510 ; + RECT 231.400 187.530 232.300 187.830 ; END END r0_addr_in[7] PIN w0_we_in @@ -281,7 +281,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 75.830 483.740 75.970 484.160 ; + RECT 77.210 217.180 77.350 217.600 ; END END w0_we_in PIN w0_ce_in @@ -290,7 +290,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 100.210 483.740 100.350 484.160 ; + RECT 102.050 217.180 102.190 217.600 ; END END w0_ce_in PIN w0_clk @@ -299,7 +299,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 124.590 483.740 124.730 484.160 ; + RECT 126.890 217.180 127.030 217.600 ; END END w0_clk PIN r0_ce_in @@ -308,7 +308,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 148.970 483.740 149.110 484.160 ; + RECT 151.730 217.180 151.870 217.600 ; END END r0_ce_in PIN r0_clk @@ -317,7 +317,7 @@ MACRO fakeram_7x512_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 173.350 483.740 173.490 484.160 ; + RECT 176.570 217.180 176.710 217.600 ; END END r0_clk PIN VSS @@ -325,27 +325,28 @@ MACRO fakeram_7x512_1r1w USE GROUND ; PORT LAYER met4 ; - RECT 2.160 4.080 3.360 480.080 ; - RECT 13.040 4.080 14.240 480.080 ; - RECT 23.920 4.080 25.120 480.080 ; - RECT 34.800 4.080 36.000 480.080 ; - RECT 45.680 4.080 46.880 480.080 ; - RECT 56.560 4.080 57.760 480.080 ; - RECT 67.440 4.080 68.640 480.080 ; - RECT 78.320 4.080 79.520 480.080 ; - RECT 89.200 4.080 90.400 480.080 ; - RECT 100.080 4.080 101.280 480.080 ; - RECT 110.960 4.080 112.160 480.080 ; - RECT 121.840 4.080 123.040 480.080 ; - RECT 132.720 4.080 133.920 480.080 ; - RECT 143.600 4.080 144.800 480.080 ; - RECT 154.480 4.080 155.680 480.080 ; - RECT 165.360 4.080 166.560 480.080 ; - RECT 176.240 4.080 177.440 480.080 ; - RECT 187.120 4.080 188.320 480.080 ; - RECT 198.000 4.080 199.200 480.080 ; - RECT 208.880 4.080 210.080 480.080 ; - RECT 219.760 4.080 220.960 480.080 ; + RECT 2.160 4.080 3.360 213.520 ; + RECT 13.040 4.080 14.240 213.520 ; + RECT 23.920 4.080 25.120 213.520 ; + RECT 34.800 4.080 36.000 213.520 ; + RECT 45.680 4.080 46.880 213.520 ; + RECT 56.560 4.080 57.760 213.520 ; + RECT 67.440 4.080 68.640 213.520 ; + RECT 78.320 4.080 79.520 213.520 ; + RECT 89.200 4.080 90.400 213.520 ; + RECT 100.080 4.080 101.280 213.520 ; + RECT 110.960 4.080 112.160 213.520 ; + RECT 121.840 4.080 123.040 213.520 ; + RECT 132.720 4.080 133.920 213.520 ; + RECT 143.600 4.080 144.800 213.520 ; + RECT 154.480 4.080 155.680 213.520 ; + RECT 165.360 4.080 166.560 213.520 ; + RECT 176.240 4.080 177.440 213.520 ; + RECT 187.120 4.080 188.320 213.520 ; + RECT 198.000 4.080 199.200 213.520 ; + RECT 208.880 4.080 210.080 213.520 ; + RECT 219.760 4.080 220.960 213.520 ; + RECT 230.640 4.080 231.840 213.520 ; END END VSS PIN VDD @@ -353,38 +354,39 @@ MACRO fakeram_7x512_1r1w USE POWER ; PORT LAYER met4 ; - RECT 2.160 4.080 3.360 480.080 ; - RECT 13.040 4.080 14.240 480.080 ; - RECT 23.920 4.080 25.120 480.080 ; - RECT 34.800 4.080 36.000 480.080 ; - RECT 45.680 4.080 46.880 480.080 ; - RECT 56.560 4.080 57.760 480.080 ; - RECT 67.440 4.080 68.640 480.080 ; - RECT 78.320 4.080 79.520 480.080 ; - RECT 89.200 4.080 90.400 480.080 ; - RECT 100.080 4.080 101.280 480.080 ; - RECT 110.960 4.080 112.160 480.080 ; - RECT 121.840 4.080 123.040 480.080 ; - RECT 132.720 4.080 133.920 480.080 ; - RECT 143.600 4.080 144.800 480.080 ; - RECT 154.480 4.080 155.680 480.080 ; - RECT 165.360 4.080 166.560 480.080 ; - RECT 176.240 4.080 177.440 480.080 ; - RECT 187.120 4.080 188.320 480.080 ; - RECT 198.000 4.080 199.200 480.080 ; - RECT 208.880 4.080 210.080 480.080 ; - RECT 219.760 4.080 220.960 480.080 ; + RECT 2.160 4.080 3.360 213.520 ; + RECT 13.040 4.080 14.240 213.520 ; + RECT 23.920 4.080 25.120 213.520 ; + RECT 34.800 4.080 36.000 213.520 ; + RECT 45.680 4.080 46.880 213.520 ; + RECT 56.560 4.080 57.760 213.520 ; + RECT 67.440 4.080 68.640 213.520 ; + RECT 78.320 4.080 79.520 213.520 ; + RECT 89.200 4.080 90.400 213.520 ; + RECT 100.080 4.080 101.280 213.520 ; + RECT 110.960 4.080 112.160 213.520 ; + RECT 121.840 4.080 123.040 213.520 ; + RECT 132.720 4.080 133.920 213.520 ; + RECT 143.600 4.080 144.800 213.520 ; + RECT 154.480 4.080 155.680 213.520 ; + RECT 165.360 4.080 166.560 213.520 ; + RECT 176.240 4.080 177.440 213.520 ; + RECT 187.120 4.080 188.320 213.520 ; + RECT 198.000 4.080 199.200 213.520 ; + RECT 208.880 4.080 210.080 213.520 ; + RECT 219.760 4.080 220.960 213.520 ; + RECT 230.640 4.080 231.840 213.520 ; END END VDD OBS LAYER met1 ; - RECT 0 0 229.540 484.160 ; + RECT 0 0 232.300 217.600 ; LAYER met2 ; - RECT 0 0 229.540 484.160 ; + RECT 0 0 232.300 217.600 ; LAYER met3 ; - RECT 0 0 229.540 484.160 ; + RECT 0 0 232.300 217.600 ; LAYER met4 ; - RECT 0 0 229.540 484.160 ; + RECT 0 0 232.300 217.600 ; END END fakeram_7x512_1r1w diff --git a/designs/sky130hd/eyeriss/sram/lef/fakeram_8x4096_1r1w.lef b/designs/sky130hd/eyeriss/sram/lef/fakeram_8x4096_1r1w.lef index 4d0810ff..841b4c36 100644 --- a/designs/sky130hd/eyeriss/sram/lef/fakeram_8x4096_1r1w.lef +++ b/designs/sky130hd/eyeriss/sram/lef/fakeram_8x4096_1r1w.lef @@ -3,7 +3,7 @@ BUSBITCHARS "[]" ; MACRO fakeram_8x4096_1r1w FOREIGN fakeram_8x4096_1r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 229.540 BY 484.160 ; + SIZE 265.420 BY 217.600 ; CLASS BLOCK ; PIN w0_wd_in[0] DIRECTION INPUT ; @@ -20,7 +20,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 50.850 0.900 51.150 ; + RECT 0.000 24.330 0.900 24.630 ; END END w0_wd_in[1] PIN w0_wd_in[2] @@ -29,7 +29,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 228.640 3.930 229.540 4.230 ; + RECT 264.520 3.930 265.420 4.230 ; END END w0_wd_in[2] PIN w0_wd_in[3] @@ -38,11 +38,11 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 228.640 50.850 229.540 51.150 ; + RECT 264.520 24.330 265.420 24.630 ; END END w0_wd_in[3] PIN w0_wd_in[4] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT @@ -51,30 +51,30 @@ MACRO fakeram_8x4096_1r1w END END w0_wd_in[4] PIN w0_wd_in[5] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 30.290 0.000 30.430 0.420 ; + RECT 34.890 0.000 35.030 0.420 ; END END w0_wd_in[5] PIN w0_wd_in[6] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 57.890 0.000 58.030 0.420 ; + RECT 67.090 0.000 67.230 0.420 ; END END w0_wd_in[6] PIN w0_wd_in[7] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 85.490 0.000 85.630 0.420 ; + RECT 99.290 0.000 99.430 0.420 ; END END w0_wd_in[7] PIN r0_rd_out[0] @@ -83,7 +83,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 113.090 0.000 113.230 0.420 ; + RECT 131.490 0.000 131.630 0.420 ; END END r0_rd_out[0] PIN r0_rd_out[1] @@ -92,7 +92,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 140.690 0.000 140.830 0.420 ; + RECT 163.690 0.000 163.830 0.420 ; END END r0_rd_out[1] PIN r0_rd_out[2] @@ -101,7 +101,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 168.290 0.000 168.430 0.420 ; + RECT 195.890 0.000 196.030 0.420 ; END END r0_rd_out[2] PIN r0_rd_out[3] @@ -110,7 +110,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 195.890 0.000 196.030 0.420 ; + RECT 228.090 0.000 228.230 0.420 ; END END r0_rd_out[3] PIN r0_rd_out[4] @@ -119,7 +119,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 2.690 483.740 2.830 484.160 ; + RECT 2.690 217.180 2.830 217.600 ; END END r0_rd_out[4] PIN r0_rd_out[5] @@ -128,7 +128,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 27.070 483.740 27.210 484.160 ; + RECT 31.210 217.180 31.350 217.600 ; END END r0_rd_out[5] PIN r0_rd_out[6] @@ -137,7 +137,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 51.450 483.740 51.590 484.160 ; + RECT 59.730 217.180 59.870 217.600 ; END END r0_rd_out[6] PIN r0_rd_out[7] @@ -146,7 +146,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 75.830 483.740 75.970 484.160 ; + RECT 88.250 217.180 88.390 217.600 ; END END r0_rd_out[7] PIN w0_addr_in[0] @@ -155,7 +155,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 97.770 0.900 98.070 ; + RECT 0.000 44.730 0.900 45.030 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -164,7 +164,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 144.690 0.900 144.990 ; + RECT 0.000 65.130 0.900 65.430 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -173,7 +173,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 191.610 0.900 191.910 ; + RECT 0.000 85.530 0.900 85.830 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -182,7 +182,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 238.530 0.900 238.830 ; + RECT 0.000 105.930 0.900 106.230 ; END END w0_addr_in[3] PIN w0_addr_in[4] @@ -191,7 +191,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 228.640 97.770 229.540 98.070 ; + RECT 264.520 44.730 265.420 45.030 ; END END w0_addr_in[4] PIN w0_addr_in[5] @@ -200,7 +200,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 228.640 144.690 229.540 144.990 ; + RECT 264.520 65.130 265.420 65.430 ; END END w0_addr_in[5] PIN w0_addr_in[6] @@ -209,7 +209,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 228.640 191.610 229.540 191.910 ; + RECT 264.520 85.530 265.420 85.830 ; END END w0_addr_in[6] PIN w0_addr_in[7] @@ -218,7 +218,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 228.640 238.530 229.540 238.830 ; + RECT 264.520 105.930 265.420 106.230 ; END END w0_addr_in[7] PIN r0_addr_in[0] @@ -227,7 +227,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 285.450 0.900 285.750 ; + RECT 0.000 126.330 0.900 126.630 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -236,7 +236,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 332.370 0.900 332.670 ; + RECT 0.000 146.730 0.900 147.030 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -245,7 +245,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 379.290 0.900 379.590 ; + RECT 0.000 167.130 0.900 167.430 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -254,7 +254,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 0.000 426.210 0.900 426.510 ; + RECT 0.000 187.530 0.900 187.830 ; END END r0_addr_in[3] PIN r0_addr_in[4] @@ -263,7 +263,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 228.640 285.450 229.540 285.750 ; + RECT 264.520 126.330 265.420 126.630 ; END END r0_addr_in[4] PIN r0_addr_in[5] @@ -272,7 +272,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 228.640 332.370 229.540 332.670 ; + RECT 264.520 146.730 265.420 147.030 ; END END r0_addr_in[5] PIN r0_addr_in[6] @@ -281,7 +281,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 228.640 379.290 229.540 379.590 ; + RECT 264.520 167.130 265.420 167.430 ; END END r0_addr_in[6] PIN r0_addr_in[7] @@ -290,7 +290,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met3 ; - RECT 228.640 426.210 229.540 426.510 ; + RECT 264.520 187.530 265.420 187.830 ; END END r0_addr_in[7] PIN w0_we_in @@ -299,7 +299,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 100.210 483.740 100.350 484.160 ; + RECT 116.770 217.180 116.910 217.600 ; END END w0_we_in PIN w0_ce_in @@ -308,7 +308,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 124.590 483.740 124.730 484.160 ; + RECT 145.290 217.180 145.430 217.600 ; END END w0_ce_in PIN w0_clk @@ -317,7 +317,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 148.970 483.740 149.110 484.160 ; + RECT 173.810 217.180 173.950 217.600 ; END END w0_clk PIN r0_ce_in @@ -326,7 +326,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 173.350 483.740 173.490 484.160 ; + RECT 202.330 217.180 202.470 217.600 ; END END r0_ce_in PIN r0_clk @@ -335,7 +335,7 @@ MACRO fakeram_8x4096_1r1w SHAPE ABUTMENT ; PORT LAYER met2 ; - RECT 197.730 483.740 197.870 484.160 ; + RECT 230.850 217.180 230.990 217.600 ; END END r0_clk PIN VSS @@ -343,27 +343,31 @@ MACRO fakeram_8x4096_1r1w USE GROUND ; PORT LAYER met4 ; - RECT 2.160 4.080 3.360 480.080 ; - RECT 13.040 4.080 14.240 480.080 ; - RECT 23.920 4.080 25.120 480.080 ; - RECT 34.800 4.080 36.000 480.080 ; - RECT 45.680 4.080 46.880 480.080 ; - RECT 56.560 4.080 57.760 480.080 ; - RECT 67.440 4.080 68.640 480.080 ; - RECT 78.320 4.080 79.520 480.080 ; - RECT 89.200 4.080 90.400 480.080 ; - RECT 100.080 4.080 101.280 480.080 ; - RECT 110.960 4.080 112.160 480.080 ; - RECT 121.840 4.080 123.040 480.080 ; - RECT 132.720 4.080 133.920 480.080 ; - RECT 143.600 4.080 144.800 480.080 ; - RECT 154.480 4.080 155.680 480.080 ; - RECT 165.360 4.080 166.560 480.080 ; - RECT 176.240 4.080 177.440 480.080 ; - RECT 187.120 4.080 188.320 480.080 ; - RECT 198.000 4.080 199.200 480.080 ; - RECT 208.880 4.080 210.080 480.080 ; - RECT 219.760 4.080 220.960 480.080 ; + RECT 2.160 4.080 3.360 213.520 ; + RECT 13.040 4.080 14.240 213.520 ; + RECT 23.920 4.080 25.120 213.520 ; + RECT 34.800 4.080 36.000 213.520 ; + RECT 45.680 4.080 46.880 213.520 ; + RECT 56.560 4.080 57.760 213.520 ; + RECT 67.440 4.080 68.640 213.520 ; + RECT 78.320 4.080 79.520 213.520 ; + RECT 89.200 4.080 90.400 213.520 ; + RECT 100.080 4.080 101.280 213.520 ; + RECT 110.960 4.080 112.160 213.520 ; + RECT 121.840 4.080 123.040 213.520 ; + RECT 132.720 4.080 133.920 213.520 ; + RECT 143.600 4.080 144.800 213.520 ; + RECT 154.480 4.080 155.680 213.520 ; + RECT 165.360 4.080 166.560 213.520 ; + RECT 176.240 4.080 177.440 213.520 ; + RECT 187.120 4.080 188.320 213.520 ; + RECT 198.000 4.080 199.200 213.520 ; + RECT 208.880 4.080 210.080 213.520 ; + RECT 219.760 4.080 220.960 213.520 ; + RECT 230.640 4.080 231.840 213.520 ; + RECT 241.520 4.080 242.720 213.520 ; + RECT 252.400 4.080 253.600 213.520 ; + RECT 263.280 4.080 264.480 213.520 ; END END VSS PIN VDD @@ -371,38 +375,42 @@ MACRO fakeram_8x4096_1r1w USE POWER ; PORT LAYER met4 ; - RECT 2.160 4.080 3.360 480.080 ; - RECT 13.040 4.080 14.240 480.080 ; - RECT 23.920 4.080 25.120 480.080 ; - RECT 34.800 4.080 36.000 480.080 ; - RECT 45.680 4.080 46.880 480.080 ; - RECT 56.560 4.080 57.760 480.080 ; - RECT 67.440 4.080 68.640 480.080 ; - RECT 78.320 4.080 79.520 480.080 ; - RECT 89.200 4.080 90.400 480.080 ; - RECT 100.080 4.080 101.280 480.080 ; - RECT 110.960 4.080 112.160 480.080 ; - RECT 121.840 4.080 123.040 480.080 ; - RECT 132.720 4.080 133.920 480.080 ; - RECT 143.600 4.080 144.800 480.080 ; - RECT 154.480 4.080 155.680 480.080 ; - RECT 165.360 4.080 166.560 480.080 ; - RECT 176.240 4.080 177.440 480.080 ; - RECT 187.120 4.080 188.320 480.080 ; - RECT 198.000 4.080 199.200 480.080 ; - RECT 208.880 4.080 210.080 480.080 ; - RECT 219.760 4.080 220.960 480.080 ; + RECT 2.160 4.080 3.360 213.520 ; + RECT 13.040 4.080 14.240 213.520 ; + RECT 23.920 4.080 25.120 213.520 ; + RECT 34.800 4.080 36.000 213.520 ; + RECT 45.680 4.080 46.880 213.520 ; + RECT 56.560 4.080 57.760 213.520 ; + RECT 67.440 4.080 68.640 213.520 ; + RECT 78.320 4.080 79.520 213.520 ; + RECT 89.200 4.080 90.400 213.520 ; + RECT 100.080 4.080 101.280 213.520 ; + RECT 110.960 4.080 112.160 213.520 ; + RECT 121.840 4.080 123.040 213.520 ; + RECT 132.720 4.080 133.920 213.520 ; + RECT 143.600 4.080 144.800 213.520 ; + RECT 154.480 4.080 155.680 213.520 ; + RECT 165.360 4.080 166.560 213.520 ; + RECT 176.240 4.080 177.440 213.520 ; + RECT 187.120 4.080 188.320 213.520 ; + RECT 198.000 4.080 199.200 213.520 ; + RECT 208.880 4.080 210.080 213.520 ; + RECT 219.760 4.080 220.960 213.520 ; + RECT 230.640 4.080 231.840 213.520 ; + RECT 241.520 4.080 242.720 213.520 ; + RECT 252.400 4.080 253.600 213.520 ; + RECT 263.280 4.080 264.480 213.520 ; END END VDD OBS LAYER met1 ; - RECT 0 0 229.540 484.160 ; + RECT 0 0 265.420 217.600 ; LAYER met2 ; - RECT 0 0 229.540 484.160 ; + RECT 0 0 265.420 217.600 ; LAYER met3 ; - RECT 0 0 229.540 484.160 ; + RECT 0 0 265.420 217.600 ; LAYER met4 ; - RECT 0 0 229.540 484.160 ; + RECT 0 0 265.420 217.600 ; END END fakeram_8x4096_1r1w diff --git a/designs/sky130hd/eyeriss/sram/lib/fakeram_12x128_1rw.lib b/designs/sky130hd/eyeriss/sram/lib/fakeram_12x128_1rw.lib index 2c519be4..b6e73f70 100644 --- a/designs/sky130hd/eyeriss/sram/lib/fakeram_12x128_1rw.lib +++ b/designs/sky130hd/eyeriss/sram/lib/fakeram_12x128_1rw.lib @@ -2,7 +2,7 @@ library(fakeram_12x128_1rw) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-05-13 14:52:37Z"; + date : "2026-08-13 14:43:19Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -29,7 +29,7 @@ library(fakeram_12x128_1rw) { default_input_pin_cap : 0.0; default_output_pin_cap : 0.0; default_input_pin_cap : 0.0; - default_max_transition : 1.110; + default_max_transition : 5.000; default_operating_conditions : tt_1.0_25.0; default_leakage_power_density : 0.0; @@ -88,7 +88,7 @@ library(fakeram_12x128_1rw) { downto : true ; } cell(fakeram_12x128_1rw) { - area : 30820.810; + area : 18217.472; interface_timing : true; memory() { type : ram; @@ -99,15 +99,15 @@ cell(fakeram_12x128_1rw) { direction : input; capacitance : 0.025; clock : true; - min_period : 0.394 ; + min_period : 1.000 ; internal_power(){ rise_power(fakeram_12x128_1rw_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("9.994, 9.994") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } fall_power(fakeram_12x128_1rw_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("9.994, 9.994") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } } } @@ -124,28 +124,28 @@ cell(fakeram_12x128_1rw) { timing_type : rising_edge; timing_sense : non_unate; cell_rise(fakeram_12x128_1rw_mem_out_delay_template) { - index_1 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); index_2 ("0.005, 0.500"); values ( \ - "0.585, 0.585", \ - "0.585, 0.585" \ + "1.400, 1.400", \ + "1.400, 1.400" \ ) } cell_fall(fakeram_12x128_1rw_mem_out_delay_template) { - index_1 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); index_2 ("0.005, 0.500"); values ( \ - "0.585, 0.585", \ - "0.585, 0.585" \ + "1.400, 1.400", \ + "1.400, 1.400" \ ) } rise_transition(fakeram_12x128_1rw_mem_out_slew_template) { index_1 ("0.005, 0.500"); - values ("0.044, 1.110") + values ("0.200, 5.000") } fall_transition(fakeram_12x128_1rw_mem_out_slew_template) { index_1 ("0.005, 0.500"); - values ("0.044, 1.110") + values ("0.200, 5.000") } } } @@ -156,16 +156,16 @@ cell(fakeram_12x128_1rw) { related_pin : rw0_clk; timing_type : setup_rising ; rise_constraint(fakeram_12x128_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_12x128_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -176,16 +176,16 @@ cell(fakeram_12x128_1rw) { related_pin : rw0_clk; timing_type : hold_rising ; rise_constraint(fakeram_12x128_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_12x128_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -194,12 +194,12 @@ cell(fakeram_12x128_1rw) { } internal_power(){ rise_power(fakeram_12x128_1rw_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.100, 0.100") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_12x128_1rw_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.100, 0.100") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -210,16 +210,16 @@ cell(fakeram_12x128_1rw) { related_pin : rw0_clk; timing_type : setup_rising ; rise_constraint(fakeram_12x128_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_12x128_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -230,16 +230,16 @@ cell(fakeram_12x128_1rw) { related_pin : rw0_clk; timing_type : hold_rising ; rise_constraint(fakeram_12x128_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_12x128_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -248,12 +248,12 @@ cell(fakeram_12x128_1rw) { } internal_power(){ rise_power(fakeram_12x128_1rw_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.100, 0.100") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_12x128_1rw_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.100, 0.100") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -265,16 +265,16 @@ cell(fakeram_12x128_1rw) { related_pin : rw0_clk; timing_type : setup_rising ; rise_constraint(fakeram_12x128_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_12x128_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -285,16 +285,16 @@ cell(fakeram_12x128_1rw) { related_pin : rw0_clk; timing_type : hold_rising ; rise_constraint(fakeram_12x128_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_12x128_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -303,12 +303,12 @@ cell(fakeram_12x128_1rw) { } internal_power(){ rise_power(fakeram_12x128_1rw_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.100, 0.100") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_12x128_1rw_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.100, 0.100") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -324,16 +324,16 @@ cell(fakeram_12x128_1rw) { related_pin : rw0_clk; timing_type : setup_rising ; rise_constraint(fakeram_12x128_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_12x128_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -344,16 +344,16 @@ cell(fakeram_12x128_1rw) { related_pin : rw0_clk; timing_type : hold_rising ; rise_constraint(fakeram_12x128_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_12x128_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -363,27 +363,27 @@ cell(fakeram_12x128_1rw) { internal_power(){ when : "(! (rw0_we_in) )"; rise_power(fakeram_12x128_1rw_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.100, 0.100") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_12x128_1rw_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.100, 0.100") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } internal_power(){ when : "(rw0_we_in)"; rise_power(fakeram_12x128_1rw_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.100, 0.100") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_12x128_1rw_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.100, 0.100") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } - cell_leakage_power : 79.580; + cell_leakage_power : 50.000; } } diff --git a/designs/sky130hd/eyeriss/sram/lib/fakeram_12x2048_1r1w.lib b/designs/sky130hd/eyeriss/sram/lib/fakeram_12x2048_1r1w.lib index d0aa40c4..f0fb3a94 100644 --- a/designs/sky130hd/eyeriss/sram/lib/fakeram_12x2048_1r1w.lib +++ b/designs/sky130hd/eyeriss/sram/lib/fakeram_12x2048_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_12x2048_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-05-13 14:52:35Z"; + date : "2026-08-13 14:43:19Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -29,7 +29,7 @@ library(fakeram_12x2048_1r1w) { default_input_pin_cap : 0.0; default_output_pin_cap : 0.0; default_input_pin_cap : 0.0; - default_max_transition : 1.110; + default_max_transition : 5.000; default_operating_conditions : tt_1.0_25.0; default_leakage_power_density : 0.0; @@ -88,7 +88,7 @@ library(fakeram_12x2048_1r1w) { downto : true ; } cell(fakeram_12x2048_1r1w) { - area : 110213.203; + area : 86683.136; interface_timing : true; memory() { type : ram; @@ -99,15 +99,15 @@ cell(fakeram_12x2048_1r1w) { direction : input; capacitance : 0.025; clock : true; - min_period : 0.450 ; + min_period : 1.000 ; internal_power(){ rise_power(fakeram_12x2048_1r1w_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("13.052, 13.052") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } fall_power(fakeram_12x2048_1r1w_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("13.052, 13.052") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } } } @@ -116,15 +116,15 @@ cell(fakeram_12x2048_1r1w) { direction : input; capacitance : 0.025; clock : true; - min_period : 0.450 ; + min_period : 1.000 ; internal_power(){ rise_power(fakeram_12x2048_1r1w_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("13.052, 13.052") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } fall_power(fakeram_12x2048_1r1w_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("13.052, 13.052") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } } } @@ -141,28 +141,28 @@ cell(fakeram_12x2048_1r1w) { timing_type : rising_edge; timing_sense : non_unate; cell_rise(fakeram_12x2048_1r1w_mem_out_delay_template) { - index_1 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); index_2 ("0.005, 0.500"); values ( \ - "0.598, 0.598", \ - "0.598, 0.598" \ + "1.400, 1.400", \ + "1.400, 1.400" \ ) } cell_fall(fakeram_12x2048_1r1w_mem_out_delay_template) { - index_1 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); index_2 ("0.005, 0.500"); values ( \ - "0.598, 0.598", \ - "0.598, 0.598" \ + "1.400, 1.400", \ + "1.400, 1.400" \ ) } rise_transition(fakeram_12x2048_1r1w_mem_out_slew_template) { index_1 ("0.005, 0.500"); - values ("0.044, 1.110") + values ("0.200, 5.000") } fall_transition(fakeram_12x2048_1r1w_mem_out_slew_template) { index_1 ("0.005, 0.500"); - values ("0.044, 1.110") + values ("0.200, 5.000") } } } @@ -173,16 +173,16 @@ cell(fakeram_12x2048_1r1w) { related_pin : w0_clk; timing_type : setup_rising ; rise_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -193,16 +193,16 @@ cell(fakeram_12x2048_1r1w) { related_pin : w0_clk; timing_type : hold_rising ; rise_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -211,12 +211,12 @@ cell(fakeram_12x2048_1r1w) { } internal_power(){ rise_power(fakeram_12x2048_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.131, 0.131") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_12x2048_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.131, 0.131") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -227,16 +227,16 @@ cell(fakeram_12x2048_1r1w) { related_pin : r0_clk; timing_type : setup_rising ; rise_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -247,16 +247,16 @@ cell(fakeram_12x2048_1r1w) { related_pin : r0_clk; timing_type : hold_rising ; rise_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -265,12 +265,12 @@ cell(fakeram_12x2048_1r1w) { } internal_power(){ rise_power(fakeram_12x2048_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.131, 0.131") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_12x2048_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.131, 0.131") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -281,16 +281,16 @@ cell(fakeram_12x2048_1r1w) { related_pin : w0_clk; timing_type : setup_rising ; rise_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -301,16 +301,16 @@ cell(fakeram_12x2048_1r1w) { related_pin : w0_clk; timing_type : hold_rising ; rise_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -319,12 +319,12 @@ cell(fakeram_12x2048_1r1w) { } internal_power(){ rise_power(fakeram_12x2048_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.131, 0.131") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_12x2048_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.131, 0.131") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -340,16 +340,16 @@ cell(fakeram_12x2048_1r1w) { related_pin : w0_clk; timing_type : setup_rising ; rise_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -360,16 +360,16 @@ cell(fakeram_12x2048_1r1w) { related_pin : w0_clk; timing_type : hold_rising ; rise_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -379,23 +379,23 @@ cell(fakeram_12x2048_1r1w) { internal_power(){ when : "(! (w0_we_in) )"; rise_power(fakeram_12x2048_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.131, 0.131") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_12x2048_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.131, 0.131") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } internal_power(){ when : "(w0_we_in)"; rise_power(fakeram_12x2048_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.131, 0.131") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_12x2048_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.131, 0.131") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -407,16 +407,16 @@ cell(fakeram_12x2048_1r1w) { related_pin : r0_clk; timing_type : setup_rising ; rise_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -427,16 +427,16 @@ cell(fakeram_12x2048_1r1w) { related_pin : r0_clk; timing_type : hold_rising ; rise_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -445,12 +445,12 @@ cell(fakeram_12x2048_1r1w) { } internal_power(){ rise_power(fakeram_12x2048_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.131, 0.131") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_12x2048_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.131, 0.131") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -462,16 +462,16 @@ cell(fakeram_12x2048_1r1w) { related_pin : w0_clk; timing_type : setup_rising ; rise_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -482,16 +482,16 @@ cell(fakeram_12x2048_1r1w) { related_pin : w0_clk; timing_type : hold_rising ; rise_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_12x2048_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -500,16 +500,16 @@ cell(fakeram_12x2048_1r1w) { } internal_power(){ rise_power(fakeram_12x2048_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.131, 0.131") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_12x2048_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.131, 0.131") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } - cell_leakage_power : 175.802; + cell_leakage_power : 50.000; } } diff --git a/designs/sky130hd/eyeriss/sram/lib/fakeram_13x256_1rw.lib b/designs/sky130hd/eyeriss/sram/lib/fakeram_13x256_1rw.lib index 3b8d9be8..f88cf4fc 100644 --- a/designs/sky130hd/eyeriss/sram/lib/fakeram_13x256_1rw.lib +++ b/designs/sky130hd/eyeriss/sram/lib/fakeram_13x256_1rw.lib @@ -2,7 +2,7 @@ library(fakeram_13x256_1rw) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-05-13 14:52:36Z"; + date : "2026-08-13 14:43:19Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -29,7 +29,7 @@ library(fakeram_13x256_1rw) { default_input_pin_cap : 0.0; default_output_pin_cap : 0.0; default_input_pin_cap : 0.0; - default_max_transition : 1.110; + default_max_transition : 5.000; default_operating_conditions : tt_1.0_25.0; default_leakage_power_density : 0.0; @@ -88,7 +88,7 @@ library(fakeram_13x256_1rw) { downto : true ; } cell(fakeram_13x256_1rw) { - area : 53612.669; + area : 39362.752; interface_timing : true; memory() { type : ram; @@ -99,15 +99,15 @@ cell(fakeram_13x256_1rw) { direction : input; capacitance : 0.025; clock : true; - min_period : 0.440 ; + min_period : 1.000 ; internal_power(){ rise_power(fakeram_13x256_1rw_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("11.919, 11.919") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } fall_power(fakeram_13x256_1rw_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("11.919, 11.919") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } } } @@ -124,28 +124,28 @@ cell(fakeram_13x256_1rw) { timing_type : rising_edge; timing_sense : non_unate; cell_rise(fakeram_13x256_1rw_mem_out_delay_template) { - index_1 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); index_2 ("0.005, 0.500"); values ( \ - "0.584, 0.584", \ - "0.584, 0.584" \ + "1.400, 1.400", \ + "1.400, 1.400" \ ) } cell_fall(fakeram_13x256_1rw_mem_out_delay_template) { - index_1 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); index_2 ("0.005, 0.500"); values ( \ - "0.584, 0.584", \ - "0.584, 0.584" \ + "1.400, 1.400", \ + "1.400, 1.400" \ ) } rise_transition(fakeram_13x256_1rw_mem_out_slew_template) { index_1 ("0.005, 0.500"); - values ("0.044, 1.110") + values ("0.200, 5.000") } fall_transition(fakeram_13x256_1rw_mem_out_slew_template) { index_1 ("0.005, 0.500"); - values ("0.044, 1.110") + values ("0.200, 5.000") } } } @@ -156,16 +156,16 @@ cell(fakeram_13x256_1rw) { related_pin : rw0_clk; timing_type : setup_rising ; rise_constraint(fakeram_13x256_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_13x256_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -176,16 +176,16 @@ cell(fakeram_13x256_1rw) { related_pin : rw0_clk; timing_type : hold_rising ; rise_constraint(fakeram_13x256_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_13x256_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -194,12 +194,12 @@ cell(fakeram_13x256_1rw) { } internal_power(){ rise_power(fakeram_13x256_1rw_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_13x256_1rw_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -210,16 +210,16 @@ cell(fakeram_13x256_1rw) { related_pin : rw0_clk; timing_type : setup_rising ; rise_constraint(fakeram_13x256_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_13x256_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -230,16 +230,16 @@ cell(fakeram_13x256_1rw) { related_pin : rw0_clk; timing_type : hold_rising ; rise_constraint(fakeram_13x256_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_13x256_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -248,12 +248,12 @@ cell(fakeram_13x256_1rw) { } internal_power(){ rise_power(fakeram_13x256_1rw_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_13x256_1rw_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -265,16 +265,16 @@ cell(fakeram_13x256_1rw) { related_pin : rw0_clk; timing_type : setup_rising ; rise_constraint(fakeram_13x256_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_13x256_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -285,16 +285,16 @@ cell(fakeram_13x256_1rw) { related_pin : rw0_clk; timing_type : hold_rising ; rise_constraint(fakeram_13x256_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_13x256_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -303,12 +303,12 @@ cell(fakeram_13x256_1rw) { } internal_power(){ rise_power(fakeram_13x256_1rw_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_13x256_1rw_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -324,16 +324,16 @@ cell(fakeram_13x256_1rw) { related_pin : rw0_clk; timing_type : setup_rising ; rise_constraint(fakeram_13x256_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_13x256_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -344,16 +344,16 @@ cell(fakeram_13x256_1rw) { related_pin : rw0_clk; timing_type : hold_rising ; rise_constraint(fakeram_13x256_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_13x256_1rw_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -363,27 +363,27 @@ cell(fakeram_13x256_1rw) { internal_power(){ when : "(! (rw0_we_in) )"; rise_power(fakeram_13x256_1rw_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_13x256_1rw_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } internal_power(){ when : "(rw0_we_in)"; rise_power(fakeram_13x256_1rw_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_13x256_1rw_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.119, 0.119") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } - cell_leakage_power : 148.019; + cell_leakage_power : 50.000; } } diff --git a/designs/sky130hd/eyeriss/sram/lib/fakeram_21x32_1r1w.lib b/designs/sky130hd/eyeriss/sram/lib/fakeram_21x32_1r1w.lib index 576b8599..08fc0a59 100644 --- a/designs/sky130hd/eyeriss/sram/lib/fakeram_21x32_1r1w.lib +++ b/designs/sky130hd/eyeriss/sram/lib/fakeram_21x32_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_21x32_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-05-13 14:52:38Z"; + date : "2026-08-13 14:43:19Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -29,7 +29,7 @@ library(fakeram_21x32_1r1w) { default_input_pin_cap : 0.0; default_output_pin_cap : 0.0; default_input_pin_cap : 0.0; - default_max_transition : 1.110; + default_max_transition : 5.000; default_operating_conditions : tt_1.0_25.0; default_leakage_power_density : 0.0; @@ -88,7 +88,7 @@ library(fakeram_21x32_1r1w) { downto : true ; } cell(fakeram_21x32_1r1w) { - area : 22566.643; + area : 18968.192; interface_timing : true; memory() { type : ram; @@ -99,15 +99,15 @@ cell(fakeram_21x32_1r1w) { direction : input; capacitance : 0.025; clock : true; - min_period : 0.421 ; + min_period : 1.000 ; internal_power(){ rise_power(fakeram_21x32_1r1w_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("8.153, 8.153") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } fall_power(fakeram_21x32_1r1w_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("8.153, 8.153") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } } } @@ -116,15 +116,15 @@ cell(fakeram_21x32_1r1w) { direction : input; capacitance : 0.025; clock : true; - min_period : 0.421 ; + min_period : 1.000 ; internal_power(){ rise_power(fakeram_21x32_1r1w_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("8.153, 8.153") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } fall_power(fakeram_21x32_1r1w_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("8.153, 8.153") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } } } @@ -141,28 +141,28 @@ cell(fakeram_21x32_1r1w) { timing_type : rising_edge; timing_sense : non_unate; cell_rise(fakeram_21x32_1r1w_mem_out_delay_template) { - index_1 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); index_2 ("0.005, 0.500"); values ( \ - "0.534, 0.534", \ - "0.534, 0.534" \ + "1.400, 1.400", \ + "1.400, 1.400" \ ) } cell_fall(fakeram_21x32_1r1w_mem_out_delay_template) { - index_1 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); index_2 ("0.005, 0.500"); values ( \ - "0.534, 0.534", \ - "0.534, 0.534" \ + "1.400, 1.400", \ + "1.400, 1.400" \ ) } rise_transition(fakeram_21x32_1r1w_mem_out_slew_template) { index_1 ("0.005, 0.500"); - values ("0.044, 1.110") + values ("0.200, 5.000") } fall_transition(fakeram_21x32_1r1w_mem_out_slew_template) { index_1 ("0.005, 0.500"); - values ("0.044, 1.110") + values ("0.200, 5.000") } } } @@ -173,16 +173,16 @@ cell(fakeram_21x32_1r1w) { related_pin : w0_clk; timing_type : setup_rising ; rise_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -193,16 +193,16 @@ cell(fakeram_21x32_1r1w) { related_pin : w0_clk; timing_type : hold_rising ; rise_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -211,12 +211,12 @@ cell(fakeram_21x32_1r1w) { } internal_power(){ rise_power(fakeram_21x32_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.082, 0.082") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_21x32_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.082, 0.082") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -227,16 +227,16 @@ cell(fakeram_21x32_1r1w) { related_pin : r0_clk; timing_type : setup_rising ; rise_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -247,16 +247,16 @@ cell(fakeram_21x32_1r1w) { related_pin : r0_clk; timing_type : hold_rising ; rise_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -265,12 +265,12 @@ cell(fakeram_21x32_1r1w) { } internal_power(){ rise_power(fakeram_21x32_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.082, 0.082") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_21x32_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.082, 0.082") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -281,16 +281,16 @@ cell(fakeram_21x32_1r1w) { related_pin : w0_clk; timing_type : setup_rising ; rise_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -301,16 +301,16 @@ cell(fakeram_21x32_1r1w) { related_pin : w0_clk; timing_type : hold_rising ; rise_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -319,12 +319,12 @@ cell(fakeram_21x32_1r1w) { } internal_power(){ rise_power(fakeram_21x32_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.082, 0.082") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_21x32_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.082, 0.082") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -340,16 +340,16 @@ cell(fakeram_21x32_1r1w) { related_pin : w0_clk; timing_type : setup_rising ; rise_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -360,16 +360,16 @@ cell(fakeram_21x32_1r1w) { related_pin : w0_clk; timing_type : hold_rising ; rise_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -379,23 +379,23 @@ cell(fakeram_21x32_1r1w) { internal_power(){ when : "(! (w0_we_in) )"; rise_power(fakeram_21x32_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.082, 0.082") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_21x32_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.082, 0.082") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } internal_power(){ when : "(w0_we_in)"; rise_power(fakeram_21x32_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.082, 0.082") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_21x32_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.082, 0.082") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -407,16 +407,16 @@ cell(fakeram_21x32_1r1w) { related_pin : r0_clk; timing_type : setup_rising ; rise_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -427,16 +427,16 @@ cell(fakeram_21x32_1r1w) { related_pin : r0_clk; timing_type : hold_rising ; rise_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -445,12 +445,12 @@ cell(fakeram_21x32_1r1w) { } internal_power(){ rise_power(fakeram_21x32_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.082, 0.082") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_21x32_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.082, 0.082") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -462,16 +462,16 @@ cell(fakeram_21x32_1r1w) { related_pin : w0_clk; timing_type : setup_rising ; rise_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -482,16 +482,16 @@ cell(fakeram_21x32_1r1w) { related_pin : w0_clk; timing_type : hold_rising ; rise_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x32_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -500,16 +500,16 @@ cell(fakeram_21x32_1r1w) { } internal_power(){ rise_power(fakeram_21x32_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.082, 0.082") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_21x32_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.082, 0.082") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } - cell_leakage_power : 55.389; + cell_leakage_power : 50.000; } } diff --git a/designs/sky130hd/eyeriss/sram/lib/fakeram_21x512_1r1w.lib b/designs/sky130hd/eyeriss/sram/lib/fakeram_21x512_1r1w.lib index f5ddbb3c..23ccfbef 100644 --- a/designs/sky130hd/eyeriss/sram/lib/fakeram_21x512_1r1w.lib +++ b/designs/sky130hd/eyeriss/sram/lib/fakeram_21x512_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_21x512_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-05-13 14:52:35Z"; + date : "2026-08-13 14:43:19Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -29,7 +29,7 @@ library(fakeram_21x512_1r1w) { default_input_pin_cap : 0.0; default_output_pin_cap : 0.0; default_input_pin_cap : 0.0; - default_max_transition : 1.110; + default_max_transition : 5.000; default_operating_conditions : tt_1.0_25.0; default_leakage_power_density : 0.0; @@ -88,7 +88,7 @@ library(fakeram_21x512_1r1w) { downto : true ; } cell(fakeram_21x512_1r1w) { - area : 116382.870; + area : 75872.768; interface_timing : true; memory() { type : ram; @@ -99,15 +99,15 @@ cell(fakeram_21x512_1r1w) { direction : input; capacitance : 0.025; clock : true; - min_period : 0.421 ; + min_period : 1.000 ; internal_power(){ rise_power(fakeram_21x512_1r1w_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("16.873, 16.873") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } fall_power(fakeram_21x512_1r1w_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("16.873, 16.873") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } } } @@ -116,15 +116,15 @@ cell(fakeram_21x512_1r1w) { direction : input; capacitance : 0.025; clock : true; - min_period : 0.421 ; + min_period : 1.000 ; internal_power(){ rise_power(fakeram_21x512_1r1w_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("16.873, 16.873") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } fall_power(fakeram_21x512_1r1w_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("16.873, 16.873") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } } } @@ -141,28 +141,28 @@ cell(fakeram_21x512_1r1w) { timing_type : rising_edge; timing_sense : non_unate; cell_rise(fakeram_21x512_1r1w_mem_out_delay_template) { - index_1 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); index_2 ("0.005, 0.500"); values ( \ - "0.643, 0.643", \ - "0.643, 0.643" \ + "1.400, 1.400", \ + "1.400, 1.400" \ ) } cell_fall(fakeram_21x512_1r1w_mem_out_delay_template) { - index_1 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); index_2 ("0.005, 0.500"); values ( \ - "0.643, 0.643", \ - "0.643, 0.643" \ + "1.400, 1.400", \ + "1.400, 1.400" \ ) } rise_transition(fakeram_21x512_1r1w_mem_out_slew_template) { index_1 ("0.005, 0.500"); - values ("0.044, 1.110") + values ("0.200, 5.000") } fall_transition(fakeram_21x512_1r1w_mem_out_slew_template) { index_1 ("0.005, 0.500"); - values ("0.044, 1.110") + values ("0.200, 5.000") } } } @@ -173,16 +173,16 @@ cell(fakeram_21x512_1r1w) { related_pin : w0_clk; timing_type : setup_rising ; rise_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -193,16 +193,16 @@ cell(fakeram_21x512_1r1w) { related_pin : w0_clk; timing_type : hold_rising ; rise_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -211,12 +211,12 @@ cell(fakeram_21x512_1r1w) { } internal_power(){ rise_power(fakeram_21x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.169, 0.169") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_21x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.169, 0.169") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -227,16 +227,16 @@ cell(fakeram_21x512_1r1w) { related_pin : r0_clk; timing_type : setup_rising ; rise_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -247,16 +247,16 @@ cell(fakeram_21x512_1r1w) { related_pin : r0_clk; timing_type : hold_rising ; rise_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -265,12 +265,12 @@ cell(fakeram_21x512_1r1w) { } internal_power(){ rise_power(fakeram_21x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.169, 0.169") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_21x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.169, 0.169") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -281,16 +281,16 @@ cell(fakeram_21x512_1r1w) { related_pin : w0_clk; timing_type : setup_rising ; rise_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -301,16 +301,16 @@ cell(fakeram_21x512_1r1w) { related_pin : w0_clk; timing_type : hold_rising ; rise_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -319,12 +319,12 @@ cell(fakeram_21x512_1r1w) { } internal_power(){ rise_power(fakeram_21x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.169, 0.169") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_21x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.169, 0.169") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -340,16 +340,16 @@ cell(fakeram_21x512_1r1w) { related_pin : w0_clk; timing_type : setup_rising ; rise_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -360,16 +360,16 @@ cell(fakeram_21x512_1r1w) { related_pin : w0_clk; timing_type : hold_rising ; rise_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -379,23 +379,23 @@ cell(fakeram_21x512_1r1w) { internal_power(){ when : "(! (w0_we_in) )"; rise_power(fakeram_21x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.169, 0.169") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_21x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.169, 0.169") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } internal_power(){ when : "(w0_we_in)"; rise_power(fakeram_21x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.169, 0.169") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_21x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.169, 0.169") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -407,16 +407,16 @@ cell(fakeram_21x512_1r1w) { related_pin : r0_clk; timing_type : setup_rising ; rise_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -427,16 +427,16 @@ cell(fakeram_21x512_1r1w) { related_pin : r0_clk; timing_type : hold_rising ; rise_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -445,12 +445,12 @@ cell(fakeram_21x512_1r1w) { } internal_power(){ rise_power(fakeram_21x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.169, 0.169") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_21x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.169, 0.169") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -462,16 +462,16 @@ cell(fakeram_21x512_1r1w) { related_pin : w0_clk; timing_type : setup_rising ; rise_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -482,16 +482,16 @@ cell(fakeram_21x512_1r1w) { related_pin : w0_clk; timing_type : hold_rising ; rise_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_21x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -500,16 +500,16 @@ cell(fakeram_21x512_1r1w) { } internal_power(){ rise_power(fakeram_21x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.169, 0.169") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_21x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.169, 0.169") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } - cell_leakage_power : 127.804; + cell_leakage_power : 50.000; } } diff --git a/designs/sky130hd/eyeriss/sram/lib/fakeram_7x512_1r1w.lib b/designs/sky130hd/eyeriss/sram/lib/fakeram_7x512_1r1w.lib index 8b7d1705..e09dbe28 100644 --- a/designs/sky130hd/eyeriss/sram/lib/fakeram_7x512_1r1w.lib +++ b/designs/sky130hd/eyeriss/sram/lib/fakeram_7x512_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_7x512_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-05-13 14:52:34Z"; + date : "2026-08-13 14:43:19Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -29,7 +29,7 @@ library(fakeram_7x512_1r1w) { default_input_pin_cap : 0.0; default_output_pin_cap : 0.0; default_input_pin_cap : 0.0; - default_max_transition : 1.110; + default_max_transition : 5.000; default_operating_conditions : tt_1.0_25.0; default_leakage_power_density : 0.0; @@ -88,7 +88,7 @@ library(fakeram_7x512_1r1w) { downto : true ; } cell(fakeram_7x512_1r1w) { - area : 111134.086; + area : 50548.480; interface_timing : true; memory() { type : ram; @@ -99,15 +99,15 @@ cell(fakeram_7x512_1r1w) { direction : input; capacitance : 0.025; clock : true; - min_period : 0.421 ; + min_period : 1.000 ; internal_power(){ rise_power(fakeram_7x512_1r1w_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("14.322, 14.322") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } fall_power(fakeram_7x512_1r1w_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("14.322, 14.322") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } } } @@ -116,15 +116,15 @@ cell(fakeram_7x512_1r1w) { direction : input; capacitance : 0.025; clock : true; - min_period : 0.421 ; + min_period : 1.000 ; internal_power(){ rise_power(fakeram_7x512_1r1w_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("14.322, 14.322") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } fall_power(fakeram_7x512_1r1w_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("14.322, 14.322") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } } } @@ -141,28 +141,28 @@ cell(fakeram_7x512_1r1w) { timing_type : rising_edge; timing_sense : non_unate; cell_rise(fakeram_7x512_1r1w_mem_out_delay_template) { - index_1 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); index_2 ("0.005, 0.500"); values ( \ - "0.633, 0.633", \ - "0.633, 0.633" \ + "1.400, 1.400", \ + "1.400, 1.400" \ ) } cell_fall(fakeram_7x512_1r1w_mem_out_delay_template) { - index_1 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); index_2 ("0.005, 0.500"); values ( \ - "0.633, 0.633", \ - "0.633, 0.633" \ + "1.400, 1.400", \ + "1.400, 1.400" \ ) } rise_transition(fakeram_7x512_1r1w_mem_out_slew_template) { index_1 ("0.005, 0.500"); - values ("0.044, 1.110") + values ("0.200, 5.000") } fall_transition(fakeram_7x512_1r1w_mem_out_slew_template) { index_1 ("0.005, 0.500"); - values ("0.044, 1.110") + values ("0.200, 5.000") } } } @@ -173,16 +173,16 @@ cell(fakeram_7x512_1r1w) { related_pin : w0_clk; timing_type : setup_rising ; rise_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -193,16 +193,16 @@ cell(fakeram_7x512_1r1w) { related_pin : w0_clk; timing_type : hold_rising ; rise_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -211,12 +211,12 @@ cell(fakeram_7x512_1r1w) { } internal_power(){ rise_power(fakeram_7x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_7x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -227,16 +227,16 @@ cell(fakeram_7x512_1r1w) { related_pin : r0_clk; timing_type : setup_rising ; rise_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -247,16 +247,16 @@ cell(fakeram_7x512_1r1w) { related_pin : r0_clk; timing_type : hold_rising ; rise_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -265,12 +265,12 @@ cell(fakeram_7x512_1r1w) { } internal_power(){ rise_power(fakeram_7x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_7x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -281,16 +281,16 @@ cell(fakeram_7x512_1r1w) { related_pin : w0_clk; timing_type : setup_rising ; rise_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -301,16 +301,16 @@ cell(fakeram_7x512_1r1w) { related_pin : w0_clk; timing_type : hold_rising ; rise_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -319,12 +319,12 @@ cell(fakeram_7x512_1r1w) { } internal_power(){ rise_power(fakeram_7x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_7x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -340,16 +340,16 @@ cell(fakeram_7x512_1r1w) { related_pin : w0_clk; timing_type : setup_rising ; rise_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -360,16 +360,16 @@ cell(fakeram_7x512_1r1w) { related_pin : w0_clk; timing_type : hold_rising ; rise_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -379,23 +379,23 @@ cell(fakeram_7x512_1r1w) { internal_power(){ when : "(! (w0_we_in) )"; rise_power(fakeram_7x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_7x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } internal_power(){ when : "(w0_we_in)"; rise_power(fakeram_7x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_7x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -407,16 +407,16 @@ cell(fakeram_7x512_1r1w) { related_pin : r0_clk; timing_type : setup_rising ; rise_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -427,16 +427,16 @@ cell(fakeram_7x512_1r1w) { related_pin : r0_clk; timing_type : hold_rising ; rise_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -445,12 +445,12 @@ cell(fakeram_7x512_1r1w) { } internal_power(){ rise_power(fakeram_7x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_7x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -462,16 +462,16 @@ cell(fakeram_7x512_1r1w) { related_pin : w0_clk; timing_type : setup_rising ; rise_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -482,16 +482,16 @@ cell(fakeram_7x512_1r1w) { related_pin : w0_clk; timing_type : hold_rising ; rise_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_7x512_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -500,16 +500,16 @@ cell(fakeram_7x512_1r1w) { } internal_power(){ rise_power(fakeram_7x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_7x512_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } - cell_leakage_power : 174.164; + cell_leakage_power : 50.000; } } diff --git a/designs/sky130hd/eyeriss/sram/lib/fakeram_8x4096_1r1w.lib b/designs/sky130hd/eyeriss/sram/lib/fakeram_8x4096_1r1w.lib index 9078adfc..caa8e14d 100644 --- a/designs/sky130hd/eyeriss/sram/lib/fakeram_8x4096_1r1w.lib +++ b/designs/sky130hd/eyeriss/sram/lib/fakeram_8x4096_1r1w.lib @@ -2,7 +2,7 @@ library(fakeram_8x4096_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2026-05-13 14:52:38Z"; + date : "2026-08-13 14:43:19Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -29,7 +29,7 @@ library(fakeram_8x4096_1r1w) { default_input_pin_cap : 0.0; default_output_pin_cap : 0.0; default_input_pin_cap : 0.0; - default_max_transition : 1.110; + default_max_transition : 5.000; default_operating_conditions : tt_1.0_25.0; default_leakage_power_density : 0.0; @@ -88,7 +88,7 @@ library(fakeram_8x4096_1r1w) { downto : true ; } cell(fakeram_8x4096_1r1w) { - area : 111134.086; + area : 57755.392; interface_timing : true; memory() { type : ram; @@ -99,15 +99,15 @@ cell(fakeram_8x4096_1r1w) { direction : input; capacitance : 0.025; clock : true; - min_period : 0.421 ; + min_period : 1.000 ; internal_power(){ rise_power(fakeram_8x4096_1r1w_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("14.322, 14.322") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } fall_power(fakeram_8x4096_1r1w_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("14.322, 14.322") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } } } @@ -116,15 +116,15 @@ cell(fakeram_8x4096_1r1w) { direction : input; capacitance : 0.025; clock : true; - min_period : 0.421 ; + min_period : 1.000 ; internal_power(){ rise_power(fakeram_8x4096_1r1w_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("14.322, 14.322") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } fall_power(fakeram_8x4096_1r1w_energy_template_clkslew) { - index_1 ("0.044, 1.110"); - values ("14.322, 14.322") + index_1 ("0.200, 5.000"); + values ("15.000, 15.000") } } } @@ -141,28 +141,28 @@ cell(fakeram_8x4096_1r1w) { timing_type : rising_edge; timing_sense : non_unate; cell_rise(fakeram_8x4096_1r1w_mem_out_delay_template) { - index_1 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); index_2 ("0.005, 0.500"); values ( \ - "0.633, 0.633", \ - "0.633, 0.633" \ + "1.400, 1.400", \ + "1.400, 1.400" \ ) } cell_fall(fakeram_8x4096_1r1w_mem_out_delay_template) { - index_1 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); index_2 ("0.005, 0.500"); values ( \ - "0.633, 0.633", \ - "0.633, 0.633" \ + "1.400, 1.400", \ + "1.400, 1.400" \ ) } rise_transition(fakeram_8x4096_1r1w_mem_out_slew_template) { index_1 ("0.005, 0.500"); - values ("0.044, 1.110") + values ("0.200, 5.000") } fall_transition(fakeram_8x4096_1r1w_mem_out_slew_template) { index_1 ("0.005, 0.500"); - values ("0.044, 1.110") + values ("0.200, 5.000") } } } @@ -173,16 +173,16 @@ cell(fakeram_8x4096_1r1w) { related_pin : w0_clk; timing_type : setup_rising ; rise_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -193,16 +193,16 @@ cell(fakeram_8x4096_1r1w) { related_pin : w0_clk; timing_type : hold_rising ; rise_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -211,12 +211,12 @@ cell(fakeram_8x4096_1r1w) { } internal_power(){ rise_power(fakeram_8x4096_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_8x4096_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -227,16 +227,16 @@ cell(fakeram_8x4096_1r1w) { related_pin : r0_clk; timing_type : setup_rising ; rise_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -247,16 +247,16 @@ cell(fakeram_8x4096_1r1w) { related_pin : r0_clk; timing_type : hold_rising ; rise_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -265,12 +265,12 @@ cell(fakeram_8x4096_1r1w) { } internal_power(){ rise_power(fakeram_8x4096_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_8x4096_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -281,16 +281,16 @@ cell(fakeram_8x4096_1r1w) { related_pin : w0_clk; timing_type : setup_rising ; rise_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -301,16 +301,16 @@ cell(fakeram_8x4096_1r1w) { related_pin : w0_clk; timing_type : hold_rising ; rise_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -319,12 +319,12 @@ cell(fakeram_8x4096_1r1w) { } internal_power(){ rise_power(fakeram_8x4096_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_8x4096_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -340,16 +340,16 @@ cell(fakeram_8x4096_1r1w) { related_pin : w0_clk; timing_type : setup_rising ; rise_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -360,16 +360,16 @@ cell(fakeram_8x4096_1r1w) { related_pin : w0_clk; timing_type : hold_rising ; rise_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -379,23 +379,23 @@ cell(fakeram_8x4096_1r1w) { internal_power(){ when : "(! (w0_we_in) )"; rise_power(fakeram_8x4096_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_8x4096_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } internal_power(){ when : "(w0_we_in)"; rise_power(fakeram_8x4096_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_8x4096_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -407,16 +407,16 @@ cell(fakeram_8x4096_1r1w) { related_pin : r0_clk; timing_type : setup_rising ; rise_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -427,16 +427,16 @@ cell(fakeram_8x4096_1r1w) { related_pin : r0_clk; timing_type : hold_rising ; rise_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -445,12 +445,12 @@ cell(fakeram_8x4096_1r1w) { } internal_power(){ rise_power(fakeram_8x4096_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_8x4096_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } @@ -462,16 +462,16 @@ cell(fakeram_8x4096_1r1w) { related_pin : w0_clk; timing_type : setup_rising ; rise_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -482,16 +482,16 @@ cell(fakeram_8x4096_1r1w) { related_pin : w0_clk; timing_type : hold_rising ; rise_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ ) } fall_constraint(fakeram_8x4096_1r1w_constraint_template) { - index_1 ("0.044, 1.110"); - index_2 ("0.044, 1.110"); + index_1 ("0.200, 5.000"); + index_2 ("0.200, 5.000"); values ( \ "0.050, 0.050", \ "0.050, 0.050" \ @@ -500,16 +500,16 @@ cell(fakeram_8x4096_1r1w) { } internal_power(){ rise_power(fakeram_8x4096_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } fall_power(fakeram_8x4096_1r1w_energy_template_sigslew) { - index_1 ("0.044, 1.110"); - values ("0.143, 0.143") + index_1 ("0.200, 5.000"); + values ("0.150, 0.150") } } } - cell_leakage_power : 174.164; + cell_leakage_power : 50.000; } } diff --git a/designs/asap7/eyeriss/sram/fakeram_asap7.cfg b/designs/src/eyeriss/dev/generated/fakeram_asap7.cfg similarity index 100% rename from designs/asap7/eyeriss/sram/fakeram_asap7.cfg rename to designs/src/eyeriss/dev/generated/fakeram_asap7.cfg diff --git a/designs/nangate45/eyeriss/sram/fakeram_nangate45.cfg b/designs/src/eyeriss/dev/generated/fakeram_nangate45.cfg similarity index 100% rename from designs/nangate45/eyeriss/sram/fakeram_nangate45.cfg rename to designs/src/eyeriss/dev/generated/fakeram_nangate45.cfg diff --git a/designs/sky130hd/eyeriss/sram/fakeram_sky130hd.cfg b/designs/src/eyeriss/dev/generated/fakeram_sky130hd.cfg similarity index 100% rename from designs/sky130hd/eyeriss/sram/fakeram_sky130hd.cfg rename to designs/src/eyeriss/dev/generated/fakeram_sky130hd.cfg From c6b406ce2be06c7e198c863209ad99899af31b3c Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 13 Aug 2026 07:52:15 -0700 Subject: [PATCH 2/3] ci: lint committed FakeRAM LEFs for the wd_in direction bug The bug in #234 escaped because nothing checks the invariant: a *_wd_in pin is an input by definition, so a DIRECTION OUTPUT on one is always the pre-c83ecb4 side-vs-function bug and always electrically invalid. tools/check_sram_lef.sh scans every designs/*/*/sram/lef/*.lef and fails with the offending pin names; a grep-only PR workflow runs it on any LEF change. --- .github/workflows/lint-sram-lef.yml | 21 ++++++++++++++++ .gitignore | 1 + tools/check_sram_lef.sh | 38 +++++++++++++++++++++++++++++ 3 files changed, 60 insertions(+) create mode 100644 .github/workflows/lint-sram-lef.yml create mode 100755 tools/check_sram_lef.sh diff --git a/.github/workflows/lint-sram-lef.yml b/.github/workflows/lint-sram-lef.yml new file mode 100644 index 00000000..67a3350a --- /dev/null +++ b/.github/workflows/lint-sram-lef.yml @@ -0,0 +1,21 @@ +name: Lint FakeRAM LEFs + +# Guards the wd_in pin-direction invariant on every committed FakeRAM LEF. +# Cheap grep-only check — no toolchain, no LLM, no bazel cache. +on: + pull_request: + paths: + - "designs/**/sram/lef/*.lef" + - "tools/check_sram_lef.sh" + - ".github/workflows/lint-sram-lef.yml" + push: + branches: [main] + workflow_dispatch: + +jobs: + check-sram-lef: + runs-on: ubuntu-latest + timeout-minutes: 5 + steps: + - uses: actions/checkout@v4 + - run: ./tools/check_sram_lef.sh diff --git a/.gitignore b/.gitignore index 95d81666..d8d56bb0 100644 --- a/.gitignore +++ b/.gitignore @@ -24,3 +24,4 @@ tmp/ # tools/regenerate_sram.sh; the .lef/.lib that matter are copied into # designs///sram/{lef,lib}/ and tracked there. designs/src/*/dev/generated/sram/ +scratch/ diff --git a/tools/check_sram_lef.sh b/tools/check_sram_lef.sh new file mode 100755 index 00000000..f367dba9 --- /dev/null +++ b/tools/check_sram_lef.sh @@ -0,0 +1,38 @@ +#!/usr/bin/env bash +# tools/check_sram_lef.sh +# +# Lint every committed FakeRAM LEF for the wd_in pin-direction bug: bsg_fakeram +# before c83ecb4 set pin DIRECTION by which die side the pin landed on rather +# than by pin function, so the upper half of every write-data bus came out +# DIRECTION OUTPUT while Liberty correctly said input. Gate-level sim then +# floats those bits and OpenROAD PnR shorts them into one net (unroutable +# GRT-0116). See CLAUDE.md and HighTide#234. +# +# Any LEF that trips this is electrically invalid and must be regenerated with +# tools/regenerate_sram.sh. Exits non-zero if anything is wrong. + +set -euo pipefail + +ROOT=$(git rev-parse --show-toplevel) +cd "$ROOT" + +bad=0 +while IFS= read -r lef; do + # A wd_in pin is an input by definition; anything else is the side-vs-function bug. + offenders=$(grep -B1 'DIRECTION[[:space:]]\+OUTPUT' "$lef" | grep -o '[A-Za-z0-9_]*wd_in\[[0-9]*\]' || true) + if [[ -n "$offenders" ]]; then + n=$(wc -l <<<"$offenders") + echo "FAIL $lef: $n wd_in pin(s) declared DIRECTION OUTPUT" + sed 's/^/ /' <<<"$offenders" + bad=$((bad + 1)) + fi +done < <(find designs -path '*/sram/lef/*.lef' | sort) + +if (( bad )); then + echo + echo "$bad LEF file(s) carry the wd_in direction bug — regenerate with:" + echo " tools/regenerate_sram.sh " + exit 1 +fi + +echo "OK: no wd_in pin is declared DIRECTION OUTPUT" From c2e4a6cb3fb77052c231f4a94ae2d05444f41ee9 Mon Sep 17 00:00:00 2001 From: mrg Date: Thu, 13 Aug 2026 12:23:19 -0700 Subject: [PATCH 3/3] docs(eyeriss): record FakeRAM regeneration re-validation on all 3 platforms All three platforms still reach 6_final with 0 DRC and 0 setup violations on bazel-orfs 6c1bbca after the #234 macro regeneration. nangate45 reproduces its baseline to within 0.05% on every area/cell figure (its geometry was byte-identical), which makes it the control for separating toolchain drift from the macro change: its +145 ps setup gain is drift. asap7 trades die area for correctness as expected -- calibrated macros are 2-4x larger, so the die nearly doubles at unchanged util; timing flat. sky130hd shrinks 29% but setup margin falls +1348 -> +147 ps against an unchanged 25 ns clock (period_min 24.85 ns, set/period_min ~1.006 vs the 1.10 guardband). Attributable to the new macro aspect ratios changing the RTLMP floorplan, since the control shows drift went the other way. Closes cleanly; whether to relax the clock is a PPA call, left at 25 ns. Hold violations on n45 (3) and sky130hd (52) are recorded but not attributed -- the baseline never captured hold. --- designs/src/eyeriss/DECISIONS.md | 71 ++++++++++++++++++++++++++++++-- 1 file changed, 68 insertions(+), 3 deletions(-) diff --git a/designs/src/eyeriss/DECISIONS.md b/designs/src/eyeriss/DECISIONS.md index f312c622..403d41e8 100644 --- a/designs/src/eyeriss/DECISIONS.md +++ b/designs/src/eyeriss/DECISIONS.md @@ -25,14 +25,79 @@ Macro-heavy (GLB iact/Psum SRAM spads). Uses RTLMP for macro placement. each cluster's macro sub-region so annealing converges (flow knob; costs die area). See the asap7 section for the result. +## 2026-08 FakeRAM regeneration (HighTide#234) + +eyeriss was the **only** design whose FakeRAM cfgs lived at +`designs//eyeriss/sram/fakeram_.cfg` instead of the standard +`designs/src//dev/generated/` path that `tools/regenerate_sram.sh` reads. The mass +regeneration in `94296798` — the bump to bsg_fakeram `c83ecb4` that fixed the **`wd_in` LEF +pin-direction bug** — therefore skipped eyeriss silently, and its committed LEFs kept +declaring the upper half of every `rw*/w*_wd_in` bus as `DIRECTION OUTPUT` while Liberty said +`input`. Reported from a downstream gate-level sim where those bits read as floating. + +Cfgs moved to the standard path and LEF/LIB regenerated on all three platforms. Beyond the +direction fix the macros were stale on a second axis — they predate the asap7 area calibration +and the sky130hd analytical path: + +| platform | Δ macro area | cause | +|---|---|---| +| nangate45 | **0.0 %, byte-identical** | CACTI path unchanged; direction fix only | +| asap7 | **+80 % … +389 %** | 2.5× periphery overhead + dynamic column mux calibration | +| sky130hd | **−16 % … −55 %** | analytical bitcell (1.07×1.74 µm, OpenRAM) replaces scaled CACTI | + +Re-validated on bazel-orfs `6c1bbca` / OpenROAD `b65c274c`. **All three still reach `6_final` +with 0 DRC and 0 setup violations.** Baseline column is `fde02b5d` (results.html, toolchain +`553c1c3`), so it carries toolchain drift as well as the macro change — nangate45 is the clean +control for separating the two, since its geometry did not move. + +| | asap7 base → new | nangate45 base → new | sky130hd base → new | +|---|---|---|---| +| die area µm² | 226 900 → **421 713** (+86 %) | 8 406 380 → 8 407 450 (+0.0 %) | 53 040 900 → **37 526 200** (−29 %) | +| util % | 30.8 → 30.7 | 38.5 → 38.5 | 31.9 → 32.3 | +| logic cells | 301 728 → 307 541 (+1.9 %) | 307 758 → 307 635 (−0.0 %) | 222 577 → 224 313 (+0.8 %) | +| setup WNS | +138.4 → **+141.3 ps** | +102.8 → **+247.5 ps** | +1348.4 → **+147.2 ps** | +| Fmax GHz | 0.42 → 0.42 | 0.23 → 0.24 | 0.04 → 0.04 | + +- **nangate45** reproduces the baseline to within 0.05 % on every area/cell figure, confirming + the CACTI geometry is untouched. Its +145 ps setup gain is therefore **pure toolchain drift** + (`553c1c3` → `6c1bbca`), not a consequence of this change — useful as the scale of drift to + discount elsewhere. +- **asap7** trades die area for correctness exactly as expected: the calibrated macros are + ~2–4× larger, so at an unchanged util target the die nearly doubles. Timing, util and cell + count are all flat. The `CORE_UTILIZATION` 40→30 MPL-0040 workaround is still in place and + still needed. +- **sky130hd** shrinks 29 % (smaller macros), but setup margin falls from +1348 ps to +147 ps + against an unchanged 25 ns clock. `report_clock_min_period` now gives `period_min` 24.85 ns, + i.e. **set/period_min ≈ 1.006** versus the 1.10 guardband the repo's freq-push method targets. + The nangate45 control (+145 ps of *favourable* drift) does not explain a −1201 ps swing, so + this is attributable to the new macro geometry — the aspect ratios moved enough (e.g. + `fakeram_7x512_1r1w` 2.11 → 1.07) that RTLMP produces a materially different floorplan. + It closes cleanly, but with almost no headroom: relaxing the sky130hd clock toward + `period_min × 1.10` ≈ 27.5 ns would restore the guardband at the cost of reported Fmax. + **Left at 25 ns for now** — that is a PPA call, not a correctness one. +- **Hold**: asap7 clean (+23.1 ps). nangate45 −16.3 ps / 3 violations and sky130hd −374.2 ps / + 52 violations. These run with `SKIP_INCREMENTAL_REPAIR` + `SKIP_LAST_GASP`, which suppress the + post-GRT repair passes, and the `fde02b5d` baseline did not record hold, so they are **not + attributed** — an A/B against a pre-change build on this same toolchain pin would be needed + to say whether the macro change caused them. + +A grep-only guard (`tools/check_sram_lef.sh`, wired to a PR workflow) now fails any commit that +reintroduces a `wd_in` pin declared `DIRECTION OUTPUT`. + ## asap7 -**Status**: finishing — util 40→30 clears the new-RTLMP MPL-0040; WNS +122.5 ps, util 30.8 %, 301 586 logic cells, Fmax 0.42 GHz. Die area grew (the util drop) but the design now floorplans and routes to `6_final`. +**Status**: finishing — util 40→30 clears the new-RTLMP MPL-0040. On regenerated FakeRAMs +(`6c1bbca`): WNS +141.3 ps, hold +23.1 ps, util 30.7 %, 307 541 logic cells, Fmax 0.42 GHz, +die 421 713 µm², 0 DRC. Die area is ~1.9× the pre-regeneration figure because the calibrated +asap7 macros are 2–4× larger. ## nangate45 -**Status**: finishing — WNS +133.4 ps, util 38.5 %, 307 701 cells. +**Status**: finishing — WNS +247.5 ps, hold −16.3 ps (3 violations), util 38.5 %, +307 635 logic cells, Fmax 0.24 GHz, 0 DRC. Geometry byte-identical across the regeneration. ## sky130hd -**Status**: finishing — WNS ≈ +1.9 ns, 221 703 cells. +**Status**: finishing — WNS +147.2 ps, hold −374.2 ps (52 violations), util 32.3 %, +224 313 logic cells, Fmax 0.04 GHz, die 37 526 200 µm², 0 DRC. Setup headroom is now thin +(`period_min` 24.85 ns against a 25 ns clock); see the 2026-08 section above.