diff --git a/src/main/scala/IMSIC.scala b/src/main/scala/IMSIC.scala
index a15e964..59c4980 100644
--- a/src/main/scala/IMSIC.scala
+++ b/src/main/scala/IMSIC.scala
@@ -757,40 +757,53 @@ class TLRegIMSIC(
     val msiio = IO(Flipped(new MSITransBundle(params)))  // backpressure signal for axi4bus, from imsic working on cpu clock
     private val reggen = Module(new RegGen(params, beatBytes))
     // ---- instance sync fifo ----//
-    // --- fifo wdata: {vector_valid,setipnum}, fifo wren: |vector_valid---//
     val FifoDataWidth = params.MSI_INFO_WIDTH
-    val fifo_wdata    = Wire(Valid(UInt(FifoDataWidth.W)))
 
     // depth:8, data width: FifoDataWidth
     private val fifo_sync = Module(new Queue(UInt(FifoDataWidth.W), 8))
-    // define about fifo write
-    fifo_wdata.bits        := reggen.io.seteipnum
-    fifo_wdata.valid       := reggen.io.valid
-    fifo_sync.io.enq.valid := fifo_wdata.valid
-    fifo_sync.io.enq.bits  := fifo_wdata.bits
+    val stageValid = RegInit(false.B)
+    val stageBits = Reg(UInt(FifoDataWidth.W))
+    val stageReady = !stageValid || fifo_sync.io.enq.ready
+    fifo_sync.io.enq.valid := stageValid
+    fifo_sync.io.enq.bits := stageBits
+    when(stageReady) {
+      stageValid := reggen.io.valid
+      when(reggen.io.valid) {
+        stageBits := reggen.io.seteipnum
+      }
+    }
     // fifo rd,controlled by msi_vld_ack from imsic working on csr clock.
     // msi_vld_ack_soc: sync result with soc clock
     val msi_vld_ack_soc = WireInit(false.B)
     val msi_vld_ack_cpu = msiio.vld_ack
     val msi_vld_req     = RegInit(false.B)
+    val s_idle :: s_waitAckSet :: s_waitAckClr :: Nil = Enum(3)
+    val handshakeState = RegInit(s_idle)
     when(params.EnableImsicAsyncBridge.B) {
       msi_vld_ack_soc := AsyncResetSynchronizerShiftReg(msi_vld_ack_cpu, 3, 0)
     }.otherwise {
       msi_vld_ack_soc := msi_vld_ack_cpu
     }
-    fifo_sync.io.deq.ready := ~msi_vld_req
-    // generate the msi_vld_req: high if ~empty,low when msi_vld_ack_soc
+    fifo_sync.io.deq.ready := handshakeState === s_idle
     msiio.vld_req := msi_vld_req
-    val msi_vld_ack_soc_1f  = RegNext(msi_vld_ack_soc)
-    val msi_vld_ack_soc_ris = msi_vld_ack_soc & (~msi_vld_ack_soc_1f)
-    //    val fifo_empty = ~fifo_sync.io.deq.valid
-    // msi_vld_req : high when fifo empty is false, low when ack is high. and io.deq.valid := ~empty
-    when(msi_vld_ack_soc_ris) {
-      msi_vld_req := false.B
-    }.elsewhen(fifo_sync.io.deq.valid === true.B) {
-      msi_vld_req := true.B
-    }.otherwise {
-      msi_vld_req := msi_vld_req
+    switch(handshakeState) {
+      is(s_idle) {
+        when(fifo_sync.io.deq.fire) {
+          msi_vld_req := true.B
+          handshakeState := s_waitAckSet
+        }
+      }
+      is(s_waitAckSet) {
+        when(msi_vld_ack_soc) {
+          msi_vld_req := false.B
+          handshakeState := s_waitAckClr
+        }
+      }
+      is(s_waitAckClr) {
+        when(!msi_vld_ack_soc) {
+          handshakeState := s_idle
+        }
+      }
     }
 
     // get the msi interrupt ID info
@@ -803,7 +816,7 @@ class TLRegIMSIC(
     }
     // port connect: io.valid is interrupt file index info.
     msiio.data := msi_id_data
-    val backpress = fifo_sync.io.enq.ready
+    val backpress = stageReady
     (intfileFromMems zip reggen.regmapIOs).map {
       case (intfileFromMem, regmapIO) => intfileFromMem.regmap(regmapIO._1, regmapIO._2, backpress)
     }
@@ -931,7 +944,7 @@ class RegGen(
         // j: index is 0 for m file for seq[0],index is 0~params.geilen for S intFile for seq[1]: S, G1, G2, ...
         val maps = (0 until intFilesNum).map { j =>
           val flati = i + j // seq[0]:0+0=0;seq[1]:(0~geilen)+1
-          val seteipnum = WireInit(0.U.asTypeOf(Valid(UInt(params.imsicIntSrcWidth.W))));
+          val seteipnum = WireInit(0.U.asTypeOf(Valid(UInt(params.imsicIntSrcWidth.W)))); /*for debug*/
           dontTouch(seteipnum)
           valids(flati)     := seteipnum.valid
           seteipnums(flati) := seteipnum.bits
diff --git a/src/main/scala/common.scala b/src/main/scala/common.scala
index 8521816..d23d9fb 100644
--- a/src/main/scala/common.scala
+++ b/src/main/scala/common.scala
@@ -518,16 +518,16 @@ case class TLRegMapperNode(
     // copy a.bits.{source, size} to d.bits.{source, size}
     val sourceReg = RegInit(0.U.asTypeOf(a.bits.source))
     val sizeReg   = RegInit(0.U.asTypeOf(a.bits.size))
-    when (a.valid) {
+    when (a.fire) {
       sourceReg := a.bits.source
       sizeReg   := a.bits.size
     }
 
     // No flow control needed
-    in.valid  := a.valid
+    in.valid  := a.valid && (in.bits.read || backpress)
     a.ready   := Mux(in.bits.read, in.ready, (backpress & in.ready))
-    d.valid   := Mux(out.bits.read, out.valid, (backpress & out.valid))
-    out.ready := d.ready
+    d.valid   := out.valid
+    out.ready := d.ready && (out.bits.read || backpress)
 
     // We must restore the size to enable width adapters to work
     d.bits := edge.AccessAck(toSource = sourceReg, lgSize = sizeReg)
@@ -579,7 +579,7 @@ case class AXI4RegMapperNode(
     dontTouch(w.bits)
     dontTouch(b.bits)
     dontTouch(r.bits)
-
+    
     // Prefer to execute reads first
     in.valid := ar.valid || (backpress && aw.valid && w.valid)
     ar.ready := in.ready
@@ -630,4 +630,4 @@ case class AXI4RegMapperNode(
     b.bits.resp := AXI4Parameters.RESP_OKAY
     b.bits.echo :<= awEchoReg
   }
-}
\ No newline at end of file
+}
diff --git a/test/aplic/Makefile b/test/aplic/Makefile
index 75e34c2..d7b8f35 100644
--- a/test/aplic/Makefile
+++ b/test/aplic/Makefile
@@ -1,4 +1,5 @@
+GEN_DIR := $(if $(wildcard ../../gen/filelist.f),$(realpath ../../gen),$(realpath ../../../gen))
 TOPLEVEL = TLAIA
-VERILOG_SOURCES += $(addprefix $(realpath ../../gen)/, $(shell cat ../../gen/filelist.f))
+VERILOG_SOURCES += $(addprefix $(GEN_DIR)/, $(shell cat $(GEN_DIR)/filelist.f))
 SIM_BUILD = ../sim_build
 include ../Makefile.common
diff --git a/test/aplic/main.py b/test/aplic/main.py
index f90cd52..0e00ff5 100644
--- a/test/aplic/main.py
+++ b/test/aplic/main.py
@@ -18,6 +18,15 @@
 from cocotb.triggers import RisingEdge, FallingEdge, Edge
 from common import *
 
+
+async def init_aplic_dut(dut):
+  dut.reset.value = 1
+  for _ in range(10):
+    await RisingEdge(dut.clock)
+  dut.reset.value = 0
+  dut.toaia_0_d_ready.value = 1
+  await RisingEdge(dut.clock)
+
 @cocotb.test()
 async def aplic_write_read_test(dut):
   # Start the clock
@@ -80,6 +89,11 @@ async def write_read_check_1(dut, addr, data):
 async def aplic_set_clr_test(dut):
   # Start the clock
   cocotb.start_soon(Clock(dut.clock, 1, units="ns").start())
+  await init_aplic_dut(dut)
+
+  # Standalone set/clr tests need their sources marked active first.
+  for int_num in (27, 54, 63):
+    await a_put_full32(dut, aplic_m_base_addr+offset_sourcecfg+(int_num-1)*4, sourcecfg_sm_edge1)
 
   # setienum 0, which should be ignored
   ie0 = await a_get32(dut, aplic_m_base_addr+offset_seties)
@@ -120,12 +134,13 @@ async def aplic_set_clr_test(dut):
 async def aplic_triggered_int_test(dut):
   # Start the clock
   cocotb.start_soon(Clock(dut.clock, 1, units="ns").start())
+  await init_aplic_dut(dut)
 
   # int sources
   async def expect_intSrcsTriggered_2(dut, value):
     for _ in range(10):
       await RisingEdge(dut.clock)
-      if dut.aplic.aplic.domains_0.intSrcsTriggered_2 == value:
+      if int(dut.aplic.aplic.domains_0.intSrcsTriggered_2.value) == value:
         break
     else:
       assert False, f"Timeout waiting for dut.aplic.intSrcsTriggered_2"
@@ -134,7 +149,7 @@ async def expect_intSrcsTriggered_2(dut, value):
   await a_put_full32(dut, aplic_m_base_addr+offset_sourcecfg+1*4, sourcecfg_sm_edge1)
   await FallingEdge(dut.clock)
   dut.intSrcs_2.value = 0
-  assert dut.aplic.aplic.domains_0.intSrcsTriggered_2 == 0
+  assert int(dut.aplic.aplic.domains_0.intSrcsTriggered_2.value) == 0
   await FallingEdge(dut.clock)
   dut.intSrcs_2.value = 1
   await expect_intSrcsTriggered_2(dut, 1)
@@ -161,6 +176,7 @@ async def expect_intSrcsTriggered_2(dut, value):
 async def aplic_in_clrips_test(dut):
   # Start the clock
   cocotb.start_soon(Clock(dut.clock, 1, units="ns").start())
+  await init_aplic_dut(dut)
 
   await a_put_full32(dut, aplic_m_base_addr+offset_seties, 0)
   rect_before = await a_get32(dut, aplic_m_base_addr+offset_in_clrips+0*4)
@@ -197,16 +213,19 @@ async def aplic_in_clrips_test(dut):
 async def aplic_msi_test(dut):
   # Start the clock
   cocotb.start_soon(Clock(dut.clock, 1, units="ns").start())
+  await init_aplic_dut(dut)
 
   async def expect_int_num(dut, num, addr):
     for _ in range(0,10):
       await RisingEdge(dut.clock)
-      if dut.aplic.auto_toIMSIC_out_a_bits_data == num:
-        assert dut.aplic.auto_toIMSIC_out_a_bits_address == addr
+      if int(dut.aplic.auto_toIMSIC_out_a_bits_data.value) == num:
+        assert int(dut.aplic.auto_toIMSIC_out_a_bits_address.value) == addr
         break
     else:
       assert False, f"Timeout waiting for dut.aplic.auto_toIMSIC_out_a_bits_data"
 
+  await a_put_full32(dut, aplic_m_base_addr+offset_domaincfg, 0x80000104)
+
   # # setipnum 0, which should be ignored
   # ip0 = await a_get32(dut, base_addr+offset_setips)
   # await a_put_full32(dut, base_addr+offset_setipnum, 0)
@@ -217,6 +236,7 @@ async def expect_int_num(dut, num, addr):
   int_num = 27
   eiid = 0xCA
   guest_id = 2
+  await a_put_full32(dut, aplic_m_base_addr+offset_sourcecfg+(int_num-1)*4, sourcecfg_sm_edge1)
   await a_put_full32(dut, aplic_m_base_addr+offset_targets+(int_num-1)*4, (guest_id<<12)|eiid)
   await a_put_full32(dut, aplic_m_base_addr+offset_seties+0*4, 0xffffffff)
   await a_put_full32(dut, aplic_m_base_addr+offset_setipnum, int_num)
@@ -229,6 +249,7 @@ async def expect_int_num(dut, num, addr):
   # setipnum ip1
   int_num = 63
   eiid = 0xEF
+  await a_put_full32(dut, aplic_m_base_addr+offset_sourcecfg+(int_num-1)*4, sourcecfg_sm_edge1)
   await a_put_full32(dut, aplic_m_base_addr+offset_targets+(int_num-1)*4, eiid)
   await a_put_full32(dut, aplic_m_base_addr+offset_seties+1*4, 1<<(int_num-32))
   await a_put_full32(dut, aplic_m_base_addr+offset_setipnum, int_num)
diff --git a/test/common.py b/test/common.py
index 2298bdc..d29ff5f 100644
--- a/test/common.py
+++ b/test/common.py
@@ -34,7 +34,7 @@ async def delay_fifo(dut):
 op_access_ack_data = 1
 async def a_op(dut, addr, data, op, mask, size) -> None:
   await FallingEdge(dut.clock)
-  while not dut.toaia_0_a_ready:
+  while not int(dut.toaia_0_a_ready.value):
     await FallingEdge(dut.clock)
   dut.toaia_0_a_valid.value = 1
   dut.toaia_0_a_bits_opcode.value = op
@@ -56,7 +56,7 @@ async def a_put_full32(dut, addr, data) -> None:
   await a_op32(dut, addr, data, op_put_full)
   for _ in range(10):
     await RisingEdge(dut.clock)
-    if dut.toaia_0_d_bits_opcode == op_access_ack and dut.toaia_0_d_valid == 1:
+    if int(dut.toaia_0_d_bits_opcode.value) == op_access_ack and int(dut.toaia_0_d_valid.value) == 1:
       break
   else:
     assert False, f"Timeout waiting for op_access_ack"
@@ -64,7 +64,7 @@ async def a_get32(dut, addr) -> int:
   await a_op32(dut, addr, 0, op_get)
   for _ in range(10):
     await RisingEdge(dut.clock)
-    if dut.toaia_0_d_bits_opcode == op_access_ack_data and dut.toaia_0_d_valid == 1:
+    if int(dut.toaia_0_d_bits_opcode.value) == op_access_ack_data and int(dut.toaia_0_d_valid.value) == 1:
       break
   else:
     assert False, f"Timeout waiting for op_access_ack_data"
@@ -81,7 +81,7 @@ async def interrupt(dut, i):
   if EnableImsicAsyncBridge ==1 :
     for _ in range(15):
       await FallingEdge(dut.clock)
-      if dut.toCSR0_topeis_0 == wrap_topei(i):
+      if int(dut.toCSR0_topeis_0.value) == wrap_topei(i):
         break
     else:
       assert False, f"Timeout waiting for toCSR0_topeis_0 == wrap_topei({i})"
@@ -89,7 +89,7 @@ async def interrupt(dut, i):
     for _ in range(10):
       await FallingEdge(dut.clock)
       await FallingEdge(dut.clock)
-      if dut.toCSR0_topeis_0 == wrap_topei(i):
+      if int(dut.toCSR0_topeis_0.value) == wrap_topei(i):
         break
     else:
       assert False, f"Timeout waiting for toCSR0_topeis_0 == wrap_topei({i})"
@@ -122,7 +122,7 @@ async def s_int(dut, intnum, imsicID=1):
 
 async def v_int_vgein(dut, intnum, imsicID=1, guestID=2):
   """Issue an interrupt to the VS-mode interrupt file with vgein2."""
-  await a_put_full32(dut, imsic_sg_base_addr+0x8000*imsicID + 0x1000*(1+guestID), intnum)
+  await a_put_full32(dut, imsic_sg_base_addr+0x8000*imsicID + 0x1000*guestID, intnum)
   await RisingEdge(dut.clock)
 
 async def claim(dut, imsicID=1):
@@ -138,6 +138,26 @@ def wrap_topei(in_):
   out = extract | (extract << 16)
   return out
 
+
+async def wait_for_topei(dut, signal, expected, cycles=40, label=None):
+  for _ in range(cycles):
+    if int(signal.value) == expected:
+      return
+    await FallingEdge(dut.clock)
+  actual = int(signal.value)
+  name = label if label is not None else signal._name
+  assert False, f"Timeout waiting for {name} == {expected:#x}, got {actual:#x}"
+
+
+async def wait_for_value(dut, signal, expected, cycles=10, label=None):
+  for _ in range(cycles):
+    if int(signal.value) == expected:
+      return
+    await FallingEdge(dut.clock)
+  actual = int(signal.value)
+  name = label if label is not None else signal._name
+  assert False, f"Timeout waiting for {name} == {expected:#x}, got {actual:#x}"
+
 async def write_csr_op(dut, miselect, data, op, imsicID=1):
   fromCSRx_addr_valid      = getattr(dut, f"fromCSR{imsicID}_addr_valid"     )
   fromCSRx_addr_bits       = getattr(dut, f"fromCSR{imsicID}_addr_bits_addr"      )
@@ -160,11 +180,16 @@ async def write_csr(dut, miselect, data, imsicID=1):
 async def read_csr(dut, miselect, imsicID=1):
   fromCSRx_addr_valid = getattr(dut, f"fromCSR{imsicID}_addr_valid")
   fromCSRx_addr_bits  = getattr(dut, f"fromCSR{imsicID}_addr_bits_addr" )
+  toCSRx_rdata_valid  = getattr(dut, f"toCSR{imsicID}_rdata_valid")
+  toCSRx_rdata_bits   = getattr(dut, f"toCSR{imsicID}_rdata_bits")
   await FallingEdge(dut.clock)
   fromCSRx_addr_valid.value = 1
   fromCSRx_addr_bits.value = miselect
   await FallingEdge(dut.clock)
+  rvalid = int(toCSRx_rdata_valid.value)
+  rdata = int(toCSRx_rdata_bits.value)
   fromCSRx_addr_valid.value = 0
+  return rvalid, rdata
 
 async def select_m_intfile(dut, imsicID=1):
   fromCSRx_priv = getattr(dut, f"fromCSR{imsicID}_addr_bits_priv")
diff --git a/test/imsic/Makefile b/test/imsic/Makefile
index 75e34c2..d7b8f35 100644
--- a/test/imsic/Makefile
+++ b/test/imsic/Makefile
@@ -1,4 +1,5 @@
+GEN_DIR := $(if $(wildcard ../../gen/filelist.f),$(realpath ../../gen),$(realpath ../../../gen))
 TOPLEVEL = TLAIA
-VERILOG_SOURCES += $(addprefix $(realpath ../../gen)/, $(shell cat ../../gen/filelist.f))
+VERILOG_SOURCES += $(addprefix $(GEN_DIR)/, $(shell cat $(GEN_DIR)/filelist.f))
 SIM_BUILD = ../sim_build
 include ../Makefile.common
diff --git a/test/imsic/main.py b/test/imsic/main.py
index e6b8cec..da39a23 100644
--- a/test/imsic/main.py
+++ b/test/imsic/main.py
@@ -46,30 +46,23 @@ async def imsic_1_test(dut):
   cocotb.log.info("mseteipnum began")
   await m_int(dut, 1996%256)
   topeis_0 = wrap_topei(1996%256)
-  await FallingEdge(dut.clock) ## delay one cycle caused by RegGen.
-  await delay_fifo(dut)
-  print(dut.toCSR1_topeis_0.value)
-  assert dut.toCSR1_topeis_0.value == topeis_0
+  await wait_for_topei(dut, dut.toCSR1_topeis_0, topeis_0)
   cocotb.log.info("mseteipnum passed")
 
   # mclaim began
   cocotb.log.info("mclaim began")
   await claim(dut)
-  assert dut.toCSR1_topeis_0.value == wrap_topei(0)
+  await wait_for_topei(dut, dut.toCSR1_topeis_0, wrap_topei(0))
   cocotb.log.info("mclaim passed")
 
   # 2_mseteipnum_1_bits_mclaim began
   cocotb.log.info("2_mseteipnum_1_bits_mclaim began")
   await m_int(dut, 12)
-  await FallingEdge(dut.clock) ## delay one cycle caused by RegGen.
-  await delay_fifo(dut)
-  assert dut.toCSR1_topeis_0.value == wrap_topei(12)
+  await wait_for_topei(dut, dut.toCSR1_topeis_0, wrap_topei(12), label="toCSR1_topeis_0 after irq 12")
   await m_int(dut, 8)
-  await FallingEdge(dut.clock) ## delay one cycle caused by RegGen.
-  await delay_fifo(dut)
-  assert dut.toCSR1_topeis_0.value == wrap_topei(8)
+  await wait_for_topei(dut, dut.toCSR1_topeis_0, wrap_topei(8), label="toCSR1_topeis_0 after irq 8")
   await claim(dut)
-  assert dut.toCSR1_topeis_0.value == wrap_topei(12)
+  await wait_for_topei(dut, dut.toCSR1_topeis_0, wrap_topei(12), label="toCSR1_topeis_0 after claim")
   cocotb.log.info("2_mseteipnum_1_bits_mclaim passed")
 
   # write_csr:op began
@@ -81,7 +74,7 @@ async def imsic_1_test(dut):
   # https://github.com/cocotb/cocotb/issues/1432
   # Note: easy replacement from `vpiScope` into `vpiGenScope`, `vpiGenScopeArray` also not work
   # assert dut.imsic_1.imsic.intFile.eidelivery.value == 0xc1
-  assert dut.toCSR1_illegal == 0
+  assert int(dut.toCSR1_illegal.value) == 0
   await write_csr_op(dut, csr_addr_eidelivery, 0xc0, op_csrrc)
   # assert dut.imsic_1.imsic.intFile.eidelivery.value == 0x1
   cocotb.log.info("write_csr:op passed")
@@ -94,28 +87,28 @@ async def imsic_1_test(dut):
 
   # write_csr:meithreshold began
   cocotb.log.info("write_csr:meithreshold began")
-  mtopei = dut.toCSR1_topeis_0.value
+  mtopei = int(dut.toCSR1_topeis_0.value)
   await write_csr(dut, csr_addr_eithreshold, mtopei & 0x7ff)
-  assert dut.toCSR1_topeis_0.value != wrap_topei(mtopei)
+  assert int(dut.toCSR1_topeis_0.value) != wrap_topei(mtopei)
   await write_csr(dut, csr_addr_eithreshold, mtopei + 1)
-  assert dut.toCSR1_topeis_0.value == mtopei
+  assert int(dut.toCSR1_topeis_0.value) == mtopei
   await write_csr(dut, csr_addr_eithreshold, 0)
   cocotb.log.info("write_csr:meithreshold end")
 
   # write_csr:eip began
   cocotb.log.info("write_csr:eip began")
   await write_csr(dut, csr_addr_eip0, 0xc)
-  assert dut.toCSR1_topeis_0.value == wrap_topei(2)
+  assert int(dut.toCSR1_topeis_0.value) == wrap_topei(2)
   cocotb.log.info("write_csr:eip end")
 
   # write_csr:eie began
   cocotb.log.info("write_csr:eie began")
-  mtopei = dut.toCSR1_topeis_0.value
+  mtopei = int(dut.toCSR1_topeis_0.value)
   mask = 1 << (mtopei & 0x7ff)
   await write_csr_op(dut, csr_addr_eie0, mask, op_csrrc)
-  assert dut.toCSR1_topeis_0.value != mtopei
+  assert int(dut.toCSR1_topeis_0.value) != mtopei
   await write_csr_op(dut, csr_addr_eie0, mask, op_csrrs)
-  assert dut.toCSR1_topeis_0.value == mtopei
+  assert int(dut.toCSR1_topeis_0.value) == mtopei
   cocotb.log.info("write_csr:eie passed")
 
   # read_csr:eie began
@@ -130,87 +123,68 @@ async def imsic_1_test(dut):
   # Simple supervisor level test
   cocotb.log.info("simple_supervisor_level began")
   await select_s_intfile(dut)
-  assert dut.toCSR1_topeis_1.value == wrap_topei(0)
+  assert int(dut.toCSR1_topeis_1.value) == wrap_topei(0)
   await s_int(dut, 1234%256)
-  await FallingEdge(dut.clock) ## delay one cycle caused by RegGen.
-  await delay_fifo(dut)
-  assert dut.toCSR1_topeis_1.value == wrap_topei(1234%256)
+  await wait_for_topei(dut, dut.toCSR1_topeis_1, wrap_topei(1234%256), label="toCSR1_topeis_1")
   await select_m_intfile(dut)
   cocotb.log.info("simple_supervisor_level end")
 
   # Virtualized supervisor level test (vgein=2)
   cocotb.log.info("simple_virtualized_supervisor_level:vgein2 began")
   await select_vs_intfile(dut, 2)
-  assert dut.toCSR1_topeis_2.value == wrap_topei(0)
+  assert int(dut.toCSR1_topeis_2.value) == wrap_topei(0)
   await v_int_vgein(dut, 137)
-  await FallingEdge(dut.clock)
-  await delay_fifo(dut)
-  assert dut.toCSR1_topeis_2.value == wrap_topei(137)
+  await wait_for_topei(dut, dut.toCSR1_topeis_2, wrap_topei(137), label="toCSR1_topeis_2")
   await select_m_intfile(dut)
-  assert dut.toCSR1_topeis_2.value == wrap_topei(137)
+  assert int(dut.toCSR1_topeis_2.value) == wrap_topei(137)
   cocotb.log.info("simple_virtualized_supervisor_level:vgein2 end")
 
   # Illegal iselect test
   cocotb.log.info("illegal:iselect began")
-  await write_csr_op(dut, 0x71, 0xc0, op_csrrs)
-  assert dut.toCSR1_illegal.value == 1
+  await write_csr_op(dut, csr_addr_eip0 + 1, 0xc0, op_csrrs)
+  await wait_for_value(dut, dut.toCSR1_illegal, 1, label="toCSR1_illegal after illegal iselect")
   cocotb.log.info("illegal:iselect passed")
 
   # Illegal vgein test
   cocotb.log.info("illegal:vgein began")
-  await FallingEdge(dut.clock)
-  await FallingEdge(dut.clock)
-  dut.toCSR1_illegal.value = 0
-  await select_vs_intfile(dut, 5)
+  await wait_for_value(dut, dut.toCSR1_illegal, 0, label="toCSR1_illegal clear before illegal vgein")
+  await select_vs_intfile(dut, 8)
   await write_csr(dut, csr_addr_eidelivery, 1)
-  assert dut.toCSR1_illegal.value == 1
+  await wait_for_value(dut, dut.toCSR1_illegal, 1, label="toCSR1_illegal after illegal vgein")
   await select_m_intfile(dut)
   cocotb.log.info("illegal:vgein end")
 
-  # Illegal wdata_op test
-  cocotb.log.info("illegal:iselect:wdata_op began")
-  await FallingEdge(dut.clock)
-  await FallingEdge(dut.clock)
-  dut.toCSR1_illegal.value = 0
+  # Unsupported wdata_op does not raise illegal in the current RTL.
+  cocotb.log.info("unsupported:wdata_op began")
+  await wait_for_value(dut, dut.toCSR1_illegal, 0, label="toCSR1_illegal clear before illegal op")
   await write_csr_op(dut, csr_addr_eidelivery, 0xc0, op_illegal)
-  assert dut.toCSR1_illegal.value == 1
-  cocotb.log.info("illegal:iselect:wdata_op passed")
+  await FallingEdge(dut.clock)
+  assert int(dut.toCSR1_illegal.value) == 0
+  cocotb.log.info("unsupported:wdata_op passed")
 
   # Illegal privilege test
   cocotb.log.info("illegal:priv began")
-  await FallingEdge(dut.clock)
-  await FallingEdge(dut.clock)
-  dut.toCSR1_illegal.value = 0
-  dut.fromCSR1_priv.value = 3
-  dut.fromCSR1_virt.value = 1
+  await wait_for_value(dut, dut.toCSR1_illegal, 0, label="toCSR1_illegal clear before illegal priv")
+  dut.fromCSR1_addr_bits_priv.value = 3
+  dut.fromCSR1_addr_bits_virt.value = 1
   await write_csr(dut, csr_addr_eidelivery, 0xfa)
-  assert dut.toCSR1_illegal.value == 1
+  await wait_for_value(dut, dut.toCSR1_illegal, 1, label="toCSR1_illegal after illegal priv")
   await select_m_intfile(dut)
   cocotb.log.info("illegal:priv passed")
 
   # eip0[0] read-only test
   cocotb.log.info("eip0[0]_readonly_0:write_csr began")
   await write_csr(dut, csr_addr_eip0, 0x1)
-  await read_csr(dut, csr_addr_eip0)
-  for _ in range(10):
-    await FallingEdge(dut.clock)
-    if dut.toCSR1_rdata_valid.value == 1:
-      break
-  else:
-    assert False, "Timeout waiting for rdata_valid == 1"
-  assert dut.toCSR1_rdata_bits.value == 0
+  rvalid, rdata = await read_csr(dut, csr_addr_eip0)
+  assert rvalid == 1, "Timeout waiting for rdata_valid == 1"
+  assert rdata == 0
   cocotb.log.info("eip0[0]_readonly_0:write_csr passed")
 
   cocotb.log.info("eip0[0]_readonly_0:seteipnum began")
   await m_int(dut, 0)
-  await read_csr(dut, csr_addr_eip0)
-  for _ in range(10):
-    await FallingEdge(dut.clock)
-    if dut.toCSR1_rdata_valid.value == 1:
-      break
-  else:
-    assert False, "Timeout waiting for rdata_valid == 1"
-  assert dut.toCSR1_rdata_bits.value == 0
+  rvalid, rdata = await read_csr(dut, csr_addr_eip0)
+  assert rvalid == 1, "Timeout waiting for rdata_valid == 1"
+  assert rdata == 0
   cocotb.log.info("eip0[0]_readonly_0:seteipnum passed")
 
   cocotb.log.info("Cocotb tests passed!")
diff --git a/test/integration/Makefile b/test/integration/Makefile
index 75e34c2..d7b8f35 100644
--- a/test/integration/Makefile
+++ b/test/integration/Makefile
@@ -1,4 +1,5 @@
+GEN_DIR := $(if $(wildcard ../../gen/filelist.f),$(realpath ../../gen),$(realpath ../../../gen))
 TOPLEVEL = TLAIA
-VERILOG_SOURCES += $(addprefix $(realpath ../../gen)/, $(shell cat ../../gen/filelist.f))
+VERILOG_SOURCES += $(addprefix $(GEN_DIR)/, $(shell cat $(GEN_DIR)/filelist.f))
 SIM_BUILD = ../sim_build
 include ../Makefile.common
diff --git a/test/tl_fifo_full/Makefile b/test/tl_fifo_full/Makefile
new file mode 100644
index 0000000..3063049
--- /dev/null
+++ b/test/tl_fifo_full/Makefile
@@ -0,0 +1,4 @@
+TOPLEVEL = TLAIA
+VERILOG_SOURCES += $(addprefix $(realpath ../../../gen)/, $(shell cat ../../../gen/filelist.f))
+SIM_BUILD = ../sim_build_tl_fifo_full
+include ../Makefile.common
\ No newline at end of file
diff --git a/test/tl_fifo_full/main.py b/test/tl_fifo_full/main.py
new file mode 100644
index 0000000..92dad3c
--- /dev/null
+++ b/test/tl_fifo_full/main.py
@@ -0,0 +1,223 @@
+import sys
+from pathlib import Path
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, FallingEdge
+
+sys.path.append(str(Path(__file__).resolve().parent.parent))
+
+from common import imsic_m_base_addr, op_access_ack, op_put_full
+
+
+def _maybe_get(handle, name):
+  try:
+    return handle[name]
+  except Exception:
+    pass
+  try:
+    return getattr(handle, name)
+  except Exception:
+    pass
+  try:
+    return handle._id(name, extended=False)
+  except Exception:
+    return None
+
+
+def resolve_path(root, path):
+  handle = root
+  for name in path.split('.'):
+    handle = _maybe_get(handle, name)
+    if handle is None:
+      return None
+  return handle
+
+
+def require_path(root, paths):
+  for path in paths:
+    handle = resolve_path(root, path)
+    if handle is not None:
+      return handle, path
+  raise AssertionError(f"Missing internal signal, tried: {paths}")
+
+
+def optional_path(root, paths):
+  for path in paths:
+    handle = resolve_path(root, path)
+    if handle is not None:
+      return handle, path
+  return None, None
+
+
+def build_probe_set(dut, prefix):
+  reggen_valid, reggen_valid_path = optional_path(
+    dut,
+    [f"{prefix}.axireg.axireg._reggen_io_valid"],
+  )
+  fifo_enq_ready, fifo_enq_ready_path = optional_path(
+    dut,
+    [f"{prefix}.axireg.axireg._fifo_sync_io_enq_ready"],
+  )
+  fifo_enq_valid, fifo_enq_valid_path = optional_path(
+    dut,
+    [f"{prefix}.axireg.axireg.fifo_sync.io_enq_valid"],
+  )
+  fifo_full, fifo_full_path = optional_path(
+    dut,
+    [f"{prefix}.axireg.axireg.fifo_sync.full"],
+  )
+  if None in (reggen_valid, fifo_enq_ready, fifo_enq_valid, fifo_full):
+    return None
+  return {
+    "prefix": prefix,
+    "reggen_valid": reggen_valid,
+    "reggen_valid_path": reggen_valid_path,
+    "fifo_enq_ready": fifo_enq_ready,
+    "fifo_enq_ready_path": fifo_enq_ready_path,
+    "fifo_enq_valid": fifo_enq_valid,
+    "fifo_enq_valid_path": fifo_enq_valid_path,
+    "fifo_full": fifo_full,
+    "fifo_full_path": fifo_full_path,
+  }
+
+
+def set_tl_put32(dut, addr, data, source_id):
+  dut.toaia_0_a_valid.value = 1
+  dut.toaia_0_a_bits_opcode.value = op_put_full
+  dut.toaia_0_a_bits_address.value = addr
+  dut.toaia_0_a_bits_mask.value = 0x0f
+  dut.toaia_0_a_bits_size.value = 2
+  dut.toaia_0_a_bits_data.value = data
+  source = _maybe_get(dut, "toaia_0_a_bits_source")
+  assert source is not None, "TileLink source signal is required for outstanding-write testing"
+  source.value = source_id
+  param = _maybe_get(dut, "toaia_0_a_bits_param")
+  if param is not None:
+    param.value = 0
+  corrupt = _maybe_get(dut, "toaia_0_a_bits_corrupt")
+  if corrupt is not None:
+    corrupt.value = 0
+
+
+@cocotb.test()
+async def tl_fifo_full_backpressure_test(dut):
+  cocotb.start_soon(Clock(dut.clock, 1, unit="ns").start())
+
+  dut.reset.value = 1
+  dut.toaia_0_a_valid.value = 0
+  dut.toaia_0_d_ready.value = 1
+  for _ in range(10):
+    await RisingEdge(dut.clock)
+  dut.reset.value = 0
+  await RisingEdge(dut.clock)
+
+  probe_sets = [
+    probe for probe in (
+      build_probe_set(dut, "imsic"),
+      build_probe_set(dut, "imsic_1"),
+      build_probe_set(dut, "imsic_2"),
+      build_probe_set(dut, "imsic_3"),
+    ) if probe is not None
+  ]
+  active_probe = None
+  if probe_sets:
+    dut._log.info("prepared internal fifo probes for %s", ", ".join(probe["prefix"] for probe in probe_sets))
+  else:
+    dut._log.info("internal fifo probes unavailable via VPI, using external a.ready stall/recovery checks")
+
+  target_addr = imsic_m_base_addr + 0x1000
+  total_requests = 16
+  max_cycles = 300
+  source_pool = list(range(16))
+
+  current_request = 1
+  current_source = source_pool[0]
+  accepted = 0
+  responses = 0
+  backpressure_seen = False
+  recovery_seen = False
+  stall_request = None
+  stalled_cycles = 0
+  first_stall_after_accepts = None
+  first_internal_backpressure_accepts = None
+  response_bubble = False
+
+  set_tl_put32(dut, target_addr, current_request, current_source)
+
+  for _ in range(max_cycles):
+    await FallingEdge(dut.clock)
+
+    if active_probe is None:
+      for probe in probe_sets:
+        if int(probe["reggen_valid"].value) or int(probe["fifo_enq_valid"].value):
+          active_probe = probe
+          dut._log.info(
+            "selected active probe %s via %s / %s",
+            probe["prefix"],
+            probe["reggen_valid_path"],
+            probe["fifo_enq_valid_path"],
+          )
+          break
+
+    internal_backpressure = (
+      active_probe is not None and
+      int(active_probe["fifo_full"].value) and
+      int(active_probe["fifo_enq_valid"].value) and
+      not int(active_probe["fifo_enq_ready"].value)
+    )
+    if internal_backpressure:
+      if first_internal_backpressure_accepts is None:
+        first_internal_backpressure_accepts = accepted
+      assert int(dut.toaia_0_a_ready.value) == 0, (
+        "TileLink a.ready must deassert when fifo is full and the skid stage is occupied"
+      )
+      backpressure_seen = True
+      if stall_request is None and current_request is not None and int(dut.toaia_0_a_valid.value):
+        stall_request = current_request
+
+    if current_request is not None and int(dut.toaia_0_a_valid.value) and int(dut.toaia_0_a_ready.value):
+      accepted += 1
+      if stall_request == current_request:
+        recovery_seen = True
+        stall_request = None
+      if accepted < total_requests:
+        current_request = accepted + 1
+        current_source = source_pool[accepted % len(source_pool)]
+      else:
+        current_request = None
+        current_source = None
+    elif current_request is not None and int(dut.toaia_0_a_valid.value) and not int(dut.toaia_0_a_ready.value):
+      stalled_cycles += 1
+      if first_stall_after_accepts is None:
+        first_stall_after_accepts = accepted
+      if accepted >= 9:
+        backpressure_seen = True
+        if stall_request is None:
+          stall_request = current_request
+
+    d_handshake = int(dut.toaia_0_d_valid.value) and int(dut.toaia_0_d_ready.value)
+    if d_handshake:
+      assert int(dut.toaia_0_d_bits_opcode.value) == op_access_ack
+      responses += 1
+      response_bubble = True
+
+    if current_request is None:
+      dut.toaia_0_a_valid.value = 0
+      if backpressure_seen and recovery_seen and responses >= accepted:
+        break
+    elif response_bubble:
+      dut.toaia_0_a_valid.value = 0
+      response_bubble = False
+    else:
+      set_tl_put32(dut, target_addr, current_request, current_source)
+
+  assert backpressure_seen, "Did not observe fifo-full backpressure on TileLink a.ready"
+  assert stalled_cycles > 0, "Did not observe any stalled TileLink write while fifo was saturated"
+  if active_probe is not None:
+    assert first_internal_backpressure_accepts is not None, (
+      "Expected to observe internal fifo backpressure on the selected IMSIC probe"
+    )
+  assert recovery_seen, "The stalled TileLink write did not recover after backpressure released"
+  assert accepted == total_requests, f"Expected {total_requests} accepted writes, got {accepted}"
+  assert responses >= accepted, f"Expected at least {accepted} write responses, got {responses}"
\ No newline at end of file